LTC6404IUD-1-PBF中文资料

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ltc2954的用法

ltc2954的用法摘要：1.简介2.特性3.应用领域4.使用方法4.1 接线4.2 配置4.3 操作5.常见问题及解决方案6.总结正文：【简介】LTC2954 是德州仪器（Texas Instruments）公司生产的一款高精度、低漂移的电压基准芯片，具有4 路输出，广泛应用于各种电子设备中，提供精确稳定的电压参考。

【特性】LTC2954 具有以下特性：1.4 路输出，输出电压分别为2.5V、1.25V、0.625V 和0.313V；2.低漂移，典型值为±2ppm/°C；3.高精度，典型值为±0.02%；4.低噪声，典型值为1μVp-p；5.宽工作电压范围，1.8V 至5.5V；6.紧凑型5 引脚SC70 封装。

【应用领域】LTC2954 电压基准芯片广泛应用于通信、工业控制、医疗设备、仪器仪表等领域，为这些设备提供精确稳定的电压参考。

【使用方法】【接线】使用时，将LTC2954 的VCC 引脚连接到1.8V 至5.5V 电源，GND 引脚连接到地，然后将输出引脚连接到需要提供电压参考的电路。

【配置】LTC2954 无需外部元件即可工作，但在某些应用场景下，可以通过外接电阻调整输出电压。

例如，通过连接一个电阻到OUT1 引脚，可以调整OUT1 的输出电压。

【操作】LTC2954 在接通电源后即可正常工作，无需额外的操作。

但在实际应用中，建议对电路进行适当的设计和布局，以降低噪声和干扰。

【常见问题及解决方案】1.输出电压不准确：可能是由于电源电压波动或负载电流变化导致的，可以通过使用稳压电源和使用合适的负载电阻来解决；2.温度漂移较大：可能是由于环境温度变化或电路布局不合理导致的，可以通过改善电路散热条件或使用散热片来解决。

【总结】LTC2954 是一款性能优异的电压基准芯片，具有高精度、低漂移、低噪声等优点，广泛应用于各种电子设备中。

艾德克斯电子IT6400通讯协议

高速高精度线性电源IT6400系列编程与语法指南声明© Itech Electronic, Co., Ltd. 2018根据国际版权法，未经Itech Electronic, Co., Ltd. 事先允许和书面同意，不得以任何形式（包括电子存储和检索或翻译为其他国家或地区语言）复制本手册中的任何内容。

手册部件号IT6400-402459版本第2版，2018年11月28日发布Itech Electronic, Co., Ltd.商标声明Pentium是Intel Corporation在美国的注册商标。

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LTC2140CUP-14#PBF;LTC2141CUP-14#PBF;LTC2142CUP-14#PBF;LTC2140CUP-14#TRPBF;中文规格书,Datasheet资料

121421014faT YPICAL APPLICATIONF EATURESA PPLICATIONSD ESCRIPTION 40Msps/25Msps Low PowerDual ADCsnCommunications n Cellular Base Stations n Software Defined Radios n Portable Medical Imagingn Multi-Channel Data Acquisition n Nondestructive TestingnT wo-Channel Simultaneously Sampling ADC n 73.2dB SNR n 90dB SFDRn Low Power: 95mW/67mW/50mW Total 48mW/34mW/25mW per Channel n Single 1.8V Supplyn CMOS, DDR CMOS, or DDR LVDS Outputs n Selectable Input Ranges: 1V P-P to 2V P-P n 750MHz Full Power Bandwidth S/H n Optional Data Output Randomizer n Optional Clock Duty Cycle Stabilizer n Shutdown and Nap Modesn Serial SPI Port for Configuration n 64-Pin (9mm × 9mm) QFN PackageThe L TC ®2142-14/L TC2141-14/L TC2140-14 are 2-channel simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applica-tions with AC performance that includes 73.2dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.08ps RMS allows undersampling of IF frequencies with excellent noise performance.DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is 1.2LSB RMS .The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V .The ENC + and ENC –inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer al-lows high performance at full speed for a wide range of clock duty cycles.L , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.2-Tone FFT , f IN = 70MHz and 69MHzCMOS,DDR CMOS,ORDDR LVDS OUTPUTSD1_13D1_0t t tD2_13D2_0t t t 65MHz CLOCKFREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–10021421014 TA01b051015202530/221421014faA BSOLUTE MAXIMUM RATINGS Supply Voltages (V DD , OV DD ) .......................–0.3V to 2V Analog Input Voltage (A IN +, A IN –,PAR/SER , SENSE) (Note 3) ..........–0.3V to (V DD + 0.2V)Digital Input Voltage (ENC +, ENC –, CS ,SDI, SCK) (Note 4) ....................................–0.3V to 3.9V SDO (Note 4) .............................................–0.3V to 3.9V(Notes 1, 2)P IN CONFIGURATIONS Digital Output Voltage ................–0.3V to (OV DD + 0.3V)Operating Temperature RangeLTC2142C, LTC2141C, LTC2140C .............0°C to 70°C LTC2142I, LTC2141I, LTC2140I ............–40°C to 85°C Storage Temperature Range ..................–65°C to 150°CFULL RATE CMOS OUTPUT MODEDOUBLE DATA RATE CMOS OUTPUT MODETOP VIEWUP PACKAGE64-LEAD (9mm s 9mm) PLASTIC QFNV DD 1V CM1 2GND 3A IN1+ 4A IN1– 5GND 6REFH 7REFL 8REFH 9REFL 10PAR/SER 11A IN2+ 12A IN2– 13GND 14V CM2 15V DD 1648 D1_347 D1_246 D1_145 D1_044 DNC 43 DNC 42 OV DD 41 OGND 40 CLKOUT +39 CLKOUT –38 D2_1337 D2_1236 D2_1135 D2_1034 D2_933 D2_865GND64 V D D63 S E N S E 62 V R E F61 S D O 60 O F 159 O F 258 D 1_1357 D 1_1256 D 1_1155 D 1_1054 D 1_953 D 1_852 D 1_751 D 1_650 D 1_549 D 1_4V D D 17E N C + 18E N C – 19C S 20S C K 21S D I 22D N C 23D N C 24D 2_0 25D 2_1 26D 2_2 27D 2_3 28D 2_4 29D 2_5 30D 2_6 31D 2_7 32T JMAX = 150°C, θJA = 20°C/WEXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCBTOP VIEWUP PACKAGE64-LEAD (9mm s 9mm) PLASTIC QFNV DD 1V CM1 2GND 3A IN1+ 4A IN1– 5GND 6REFH 7REFL 8REFH 9REFL 10PAR/SER 11A IN2+ 12A IN2– 13GND 14V CM2 15V DD 1648 D1_2_347 DNC 46 D1_0_145 DNC 44 DNC 43 DNC 42 OV DD 41 OGND 40 CLKOUT +39 CLKOUT –38 D2_12_1337 DNC36 D2_10_1135 DNC 34 D2_8_933 DNC65GND64 V D D 63 S E N S E 62 V R E F61 S D O 60 O F 2_159 D N C 58 D 1_12_1357 D N C 56 D 1_10_1155 D N C 54 D 1_8_953 D N C 52 D 1_6_751 D N C 50 D 1_4_549 D N CV D D 17E N C + 18E N C – 19C S 20S C K 21S D I 22D N C 23D N C 24D N C 25D 2_0_1 26D N C 27D 2_2_3 28D N C 29D 2_4_5 30D N C 31D 2_6_7 32T JMAX = 150°C, θJA = 20°C/WEXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB/321421014faORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE L TC2142CUP-14#PBF L TC2142CUP-14#TRPBF L TC2142UP-1464-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C L TC2142IUP-14#PBF L TC2142IUP-14#TRPBF L TC2142UP-1464-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C L TC2141CUP-14#PBF L TC2141CUP-14#TRPBF L TC2141UP-1464-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C L TC2141IUP-14#PBF L TC2141IUP-14#TRPBF L TC2141UP-1464-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C L TC2140CUP-14#PBF L TC2140CUP-14#TRPBF L TC2140UP-1464-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C L TC2140IUP-14#PBFL TC2140IUP-14#TRPBFL TC2140UP-1464-Lead (9mm × 9mm) Plastic QFN–40°C to 85°CConsult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container .Consult L TC Marketing for information on non-standard lead based finish parts.For more information on lead free part marking, go to: http://www.linear .com/leadfree/For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/P IN CONFIGURATIONS DOUBLE DATA RATE LVDS OUTPUT MODETOP VIEWUP PACKAGE64-LEAD (9mm s 9mm) PLASTIC QFNV DD 1V CM1 2GND 3A IN1+ 4A IN1– 5GND 6REFH 7REFL 8REFH 9REFL 10PAR/SER 11A IN2+ 12A IN2– 13GND 14V CM2 15V DD 1648 D1_2_3+47 D1_2_3–46 D1_0_1+45 D1_0_1–44 DNC 43 DNC 42 OV DD 41 OGND 40 CLKOUT +39 CLKOUT –38 D2_12_13+37 D2_12_13–36 D2_10_11+35 D2_10_11–34 D2_8_9+33 D2_8_9–65GND64 V D D63 S E N S E 62 V R E F61 S D O 60 O F 2_1+59 O F 2_1–58 D 1_12_13+57 D 1_12_13–56 D 1_10_11+55 D 1_10_11–54 D 1_8_9+53 D 1_8_9–52 D 1_6_7+51 D 1_6_7–50 D 1_4_5+49 D 1_4_5–V D D 17E N C + 18E N C – 19C S 20S C K 21S D I 22D N C 23D N C 24D 2_0_1– 25D 2_0_1+ 26D 2_2_3– 27D 2_2_3+ 28D 2_4_5– 29D 2_4_5+ 30D 2_6_7– 31D 2_6_7+ 32T JMAX = 150°C, θJA = 20°C/WEXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB/421421014faANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwisespecifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Analog Input Range (A IN + – A IN –)1.7V < V DD < 1.9Vl 1 to 2V P-P V IN(CM)Analog Input Common Mode (A IN + + A IN –)/2Differential Analog Input (Note 8)l 0.7V CM 1.25V V SENSE External Voltage Reference Applied to SENSE External Reference Model0.6251.250 1.300V I INCMAnalog Input Common Mode CurrentPer Pin, 65MspsPer Pin, 40Msps Per Pin, 25Msps 815031μA μA μAI IN1Analog Input Leakage Current (No Encode)0 < A IN +, A IN – < V DD l –1.5 1.5μA I IN2PAR/SER Input Leakage Current 0 < PAR/SER < V DD l –33μA I IN3SENSE Input Leakage Current0.625 < SENSE < 1.3V l –33μA t AP Sample-and-Hold Acquisition Delay Time 0ns t JITTER Sample-and-Hold Acquisition Delay Jitter Single-Ended Encode Differential Encode 0.080.10ps RMS ps RMSCMRR Analog Input Common Mode Rejection Ratio 80dB BW-3BFull-Power BandwidthFigure 6 Test Circuit750MHzCONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. (Note 5)PARAMETERCONDITIONSL TC2142-14L TC2141-14L TC2140-14UNITS MIN TYPMAXMIN TYP MAX MIN TYP MAX Resolution (No Missing Codes)l141414Bits Integral Linearity Error Differential Analog Input (Note 6)l–2.4±1 2.4–2.4±1 2.4–2.4±1 2.4LSB Differential Linearity Error Differential Analog Input l –0.8±0.30.8–0.8±0.30.8–0.8±0.30.8LSB Offset Error (Note 7)l –9±1.59–9±1.59–9±1.59mV Gain Error Internal Reference External Reference l–1.5±1.5–0.3 1.1–1.5±1.5–0.3 1.1–1.5±1.5–0.3 1.1%FS %FS Offset Drift ±10±10±10μV/°C Full-Scale Drift Internal ReferenceExternal Reference ±30±10±30±10±30±10ppm/°C ppm/°C Gain Matching ±0.2±0.2±0.2%FS Offset Matching ±1.5±1.5±1.5mV T ransition Noise1.231.311.19LSB RMS/521421014faINTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over thefull operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)PARAMETER CONDITIONS MIN TYP MAX UNITSV CM Output Voltage I OUT = 00.5 • V DD – 25mV0.5 • V DD 0.5 • V DD + 25mVV V CM Output Temperature Drift ±25ppm/°CV CM Output Resistance –600μA < I OUT < 1mA 4ΩV REF Output Voltage I OUT = 01.225 1.250 1.275V V REF Output Temperature Drift ±25ppm/°CV REF Output Resistance –400μA < I OUT < 1mA 7ΩV REF Line Regulation1.7V < V DD < 1.9V0.6mV/VDYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,otherwise specifications are at T A = 25°C. A IN = –1dBFS. (Note 5)SYMBOL PARAMETER CONDITIONS L TC2142-14L TC2141-14L TC2140-14UNITS MIN TYP MAXMIN TYP MAXMIN TYP MAXSNRSignal-to-Noise Ratio5MHz Input30MHz Input 70MHz Input 140MHz Inputl71.873.273.273.172.771.572.872.872.772.47273.773.773.673.2dBFS dBFS dBFS dBFS SFDRSpurious Free Dynamic Range 2nd Harmonic 5MHz Input 30MHz Input70MHz Input 140MHz Input l 799090898481909089848190908984dBFS dBFS dBFS dBFS Spurious Free Dynamic Range 3rd Harmonic 5MHz Input 30MHz Input70MHz Input 140MHz Input l 829090898482909089848290908984dBFS dBFS dBFS dBFS Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 30MHz Input70MHz Input 140MHz Inputl 869595959586959595958895959595dBFS dBFS dBFS dBFS S/(N+D)Signal-to-Noise Plus Distortion Ratio5MHz Input 30MHz Input 70MHz Input 140MHz Input l 71.573.173.172.972.271.172.772.772.57271.873.573.573.472.7dBFS dBFS dBFS dBFS Crosstalk10MHz Input–110–110–110dBc/DIGITAL INPUTS AND OUTPUTSThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ENCODE INPUTS (ENC+, ENC– )Differential Encode Mode (ENC– Not Tied to GND)V ID Differential Input Voltage(Note 8)l0.2VV ICM Common Mode Input Voltage Internally SetExternally Set (Note 8)l 1.11.21.6VVV IN Input Voltage Range ENC+, ENC– to GND l0.2 3.6V R IN Input Resistance(See Figure 10)10kΩC IN Input Capacitance(Note 8) 3.5pF Single-Ended Encode Mode (ENC– Tied to GND)V IH High Level Input Voltage V DD = 1.8V l 1.2V V IL Low Level Input Voltage V DD = 1.8V l0.6V V IN Input Voltage Range ENC+ to GND l0 3.6V R IN Input Resistance(See Figure 11)30kΩC IN Input Capacitance(Note 8) 3.5pF DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)V IH High Level Input Voltage V DD = 1.8V l 1.3V V IL Low Level Input Voltage V DD = 1.8V l0.6V I IN Input Current V IN = 0V to 3.6V l–1010μA C IN Input Capacitance(Note 8)3pF SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)R OL Logic Low Output Resistance to GND V DD = 1.8V, SDO = 0V200ΩI OH Logic High Output Leakage Current SDO = 0V to 3.6V l–1010μA C OUT Output Capacitance(Note 8)3pF DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)OV DD = 1.8VV OH High Level Output Voltage I O = –500μA l 1.750 1.790V V OL Low Level Output Voltage I O = 500μA l0.0100.050V OV DD = 1.5VV OH High Level Output Voltage I O = –500μA 1.488V V OL Low Level Output Voltage I O = 500μA0.010V OV DD = 1.2VV OH High Level Output Voltage I O = –500μA 1.185V V OL Low Level Output Voltage I O = 500μA0.010V DIGITAL DATA OUTPUTS (LVDS MODE)V OD Differential Output Voltage100Ω Differential Load, 3.5mA Mode100Ω Differential Load, 1.75mA Mode l247350175454mVmVV OS Common Mode Output Voltage100Ω Differential Load, 3.5mA Mode100Ω Differential Load, 1.75mA Mode l 1.125 1.2501.2501.375VVR TERM On-Chip Termination Resistance Termination Enabled, OV DD = 1.8V100Ω/621421014faPOWER REQUIREMENTSThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 9)SYMBOL PARAMETER CONDITIONSL TC2142-14L TC2141-14L TC2140-14UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXCMOS Output Modes: Full Data Rate and Double Data RateV DD Analog Supply Voltage(Note 10)l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9V OV DD Output Supply Voltage(Note 10)l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9VI VDD Analog Supply Current DC InputSine Wave Input l52.7535937.137.34227.928.133mAmAI OVDD Digital Supply Current Sine Wave Input, OV DD = 1.2V 4.4 2.7 1.7mAP DISS Power Dissipation DC InputSine Wave Input, OV DD = 1.2V l94.9100.710766.870.47650.252.660mWmWLVDS Output ModeV DD Analog Supply Voltage(Note 10)l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9V OV DD Output Supply Voltage(Note 10)l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9VI VDD Analog Supply Current Sine Input, 1.75mA ModeSine Input, 3.5mA Mode l 54.455.86338.740.24629.530.937mAmAI OVDD Digital Supply Current(0V DD = 1.8V)Sine Input, 1.75mA ModeSine Input, 3.5mA Mode l34.365.77533.965.37533.765.175mAmAP DISS Power Dissipation Sine Input, 1.75mA ModeSine Input, 3.5mA Mode l 160219249131190218114173202mWmWAll Output ModesP SLEEP Sleep Mode Power111mW P NAP Nap Mode Power101010mW P DIFFCLK Power Increase with Differential Encode Mode Enabled(No Increase for Nap or Sleep Modes)202020mWTIMING CHARACTERISTICSThel denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONSL TC2142-14L TC2141-14L TC2140-14UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXf S Sampling Frequency(Note 10)l165140125MHzt L ENC Low Time (Note 8)Duty Cycle Stabilizer OffDuty Cycle Stabilizer On ll7.327.697.6950050011.88212.512.55005001922020500500nsnst H ENC High Time (Note 8)Duty Cycle Stabilizer OffDuty Cycle Stabilizer On ll7.327.697.6950050011.88212.512.55005001922020500500nsnst AP Sample-and-HoldAcquisition Delay Time000nsSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)t D ENC to Data Delay C L = 5pF (Note 8)l 1.1 1.7 3.1ns t C ENC to CLKOUT Delay C L = 5pF (Note 8)l1 1.4 2.6ns t SKEW DATA to CLKOUT Skew t D – t C (Note 8)l00.30.6nsPipeline Latency Full Data Rate ModeDouble Data Rate Mode66.5CyclesCycles/721421014fa821421014faSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSDigital Data Outputs (LVDS Mode)t D ENC to Data Delay C L = 5pF (Note 8)l 1.1 1.8 3.2ns t C ENC to CLKOUT Delay C L = 5pF (Note 8)l 1 1.5 2.7ns t SKEWDATA to CLKOUT Skew t D – t C (Note 8)l0.30.6ns Pipeline Latency6.5CyclesSPI Port Timing (Note 8)t SCK SCK PeriodWrite ModeReadback Mode, C SDO = 20pF , R PULLUP = 2kll 40250ns ns t S CS to SCK Setup Time l 5ns t H SCK to CS Setup Time l 5ns t DS SDI Setup Time l 5ns t DH SDI Hold Time l 5nst DOSCK Falling to SDO ValidReadback Mode, C SDO = 20pF , R PULLUP = 2k l125nsTIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at T A = 25°C. (Note 5)Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All voltage values are with respect to GND with GND and OGND shorted (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above V DD , they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup.Note 4: When these pin voltages are taken below GND they will beclamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup.Note 5: V DD = OV DD = 1.8V , f SAMPLE = 65MHz (L TC2142), 40MHz(L TC2141), or 25MHz (L TC2140), LVDS outputs, differential ENC +/ENC – = 2V P-P sine wave, input range = 2V P-P with differential drive, unless otherwise noted.Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band.Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode.Note 8: Guaranteed by design, not subject to test.Note 9: V DD = 1.8V , f SAMPLE = 65MHz (L TC2142), 40MHz (L TC2141), or 25MHz (L TC2140), CMOS outputs, ENC + = single-ended 1.8V square wave, ENC – = 0V , input range = 2V P-P with differential drive, 5pF load on each digital output unless otherwise noted. The supply current and power dissipation specifications are totals for the entire IC, not per channel.Note 10: Recommended operating conditions./921421014faT YPICAL PERFORMANCE CHARACTERISTICS L TC2142-14: IntegralNonlinearity (INL)L TC2142-14: Differential Nonlinearity (DNL)L TC2142-14: 64k Point FFT , f IN = 5MHz, –1dBFS, 65MspsL TC2142-14: 64k Point FFT , f IN = 30MHz, –1dBFS, 65MspsL TC2142-14: 64k Point FFT , f IN = 70MHz, –1dBFS, 65MspsL TC2142-14: 64k Point FFT , f IN = 140MHz, –1dBFS, 65MspsL TC2142-14: 64k Point 2-Tone FFT , f IN = 69MHz, 70MHz, –7dBFS, 65MspsL TC2142-14: Shorted Input HistogramL TC2142-14: SNR vs Input Frequency, –1dBFS, 65Msps,2V RangeOUTPUT CODE–2.0–1.0–0.5–1.5I N L E R R O R (L S B )00.51.01.52.021421014 G01409681921228816384OUTPUT CODE–1.0–0.4–0.2–0.6–0.8D N L E R R O R (L S B )00.40.20.60.81.021421014 G02409681921228816384FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–10021421014 G03102030FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–10021421014 G04102030FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–10021421014 G05102030FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–10021421014 G06102030FREQUENCY (MHz)–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–10021421014 G07051015202530OUTPUT CODE8183020001000C O U N T3000400060005000818781918189818521421014 G08INPUT FREQUENCY (MHz)0717069747273S N R (d B F S )5010015020025030021421014 G09/1021421014faT YPICAL PERFORMANCE CHARACTERISTICS L TC2142-14: SFDR vs Input Level, f IN = 70MHz, 65Msps, 2V RangeL TC2142-14: I VDD vs Sample Rate, 5MHz, –1dBFS, Sine Wave Input on Each ChannelL TC2142-14: 2nd, 3rd Harmonicvs Input Frequency, –1dBFS, 65Msps, 2V RangeL TC2142-14: I OVDD vs Sample Rate, 5MHz, –1dBFS, Sine Wave Input on Each ChannelL TC2142-14: SNR vs SENSE, f IN = 5MHz, –1dBFSL TC2141-14: Integral Nonlinearity (INL)L TC2141-14: Differential Nonlinearity (DNL)L TC2141-14: 64k Point FFT , f IN = 5MHz, –1dBFS, 40MspsL TC2142-14: 2nd, 3rd Harmonic vs Input Frequency, –1dBFS, 65Msps, 1V Range050100150200250300INPUT FREQUENCY (MHz)908580757065100952N D A N D 3R D H A R M O N I C (d B F S )21421014 G1050100150200250300INPUT FREQUENCY (MHz)908580757065100952N D A N D 3R D H A R M O N I C (d B F S )21421014 G11INPUT LEVEL (dBFS)1201309080100110S F D R (d B c A N D d B F S )70506040302021421014 G12–80–70–60–50–40–30–20–10SAMPLE RATE (Msps)504055453560I V D D (m A )10206021421014 G13304050SAMPLE RATE (Msps)50603040201070I O V D D (m A )2040506021421014 G141030SENSE PIN (V)0.6707168696766727374S N R (d B F S )0.810.70.9 1.1 1.21.321421014 G15OUTPUT CODE–2.0–1.0–0.5–1.5I N L E R R O R (L S B )00.51.01.52.021421014 G16409681921228816384OUTPUT CODE–1.0–0.4–0.2–0.6–0.8D N L E R R O R (L S B )00.40.20.60.81.021421014 G17409681921228816384FREQUENCY (MHz)0–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–100510152021421014 G18/分销商库存信息:LINEAR-TECHNOLOGYLTC2140CUP-14#PBF LTC2141CUP-14#PBF LTC2142CUP-14#PBF LTC2140CUP-14#TRPBF LTC2140IUP-14#TRPBF LTC2141CUP-14#TRPBF LTC2140IUP-14#PBF LTC2141IUP-14#PBF LTC2142CUP-14#TRPBF LTC2142IUP-14#TRPBF LTC2142IUP-14#PBF DC1620A-JDC1620A-K DC1620A-L。

TDA6404资料

399.25 MHz 855.25 MHz − − − − − − dB dB dB dB dBµV dBµV
407.25 −
ORDERING INFORMATION TYPE NUMBER TDA6404TS; TDA6405TS; TDA6405ATS PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm VERSION SOT341-1
handbook, full pagewidth
IFFIL1
IFFIL2 6 (23)
VCC 17 (12) BSVHF (4) 25 (3) 26 VHF OSCILLATOR VHFOSCIB1 VHFOSCOC1 VHFOSCOC2 VHFOSCIB2
5 (
RF INPUT VHF
1999 Jan 13
2
元器件交易网
Philips Semiconductors
Product speciﬁcation
5 V mixer/oscillator-PLL synthesizers for hyperband tuners
QUICK REFERENCE DATA SYMBOL VCC ICC fXTAL Io(PNP) Tstg Tamb f(i)RF GV F Vo PARAMETER supply voltage supply current crystal oscillator frequency PNP port output current IC storage temperature operating ambient temperature RF input frequency voltage gain noise ﬁgure output voltage causing 1% cross modulation in channel VHF band UHF band VHF band UHF band VHF band UHF band VHF band UHF band CONDITIONS operating all PNP ports are ‘OFF’ RXTAL = 25 to 150 Ω

三汇示波器说明书(Ver1.0)

5.3.1 XY格式............................................................................. 24 5.4 菜单框和菜单框选择按钮............................................................ 25 5.5 水平控制..................................................................................... 26
DST4000 和 DST1000 系列数字存储示波器用户手册
i
目录
5.1 显示区 ........................................................................................ 20 5.2 信息区域..................................................................................... 23 5.3 波形显示..................................................................................... 23
三汇系列产品
DST4000 和 DST1000 系列数字存储示波器
Version 1.0
杭州三汇科技有限公司 www.
目录
目录
目录 ...........................................................................................................i 版权申明 .......................................................................................................................................................................v 第 1 章安全事项......................................................................................... 1

LTC4213 1 4213f 电子电路保护器说明书

2µs/DIV4213 TA01b124213fBias Supply Voltage (V CC )...........................–0.3V to 9V Input VoltagesON, SENSEP, SENSEN.............................–0.3V to 9V I SEL ..........................................–0.3V to (V CC + 0.3V)Output VoltagesGATE .....................................................–0.3V to 15V READY.....................................................–0.3V to 9V Operating Temperature RangeLTC4213C ...............................................0°C to 70°C LTC4213I.............................................–40°C to 85°C Storage Temperature Range.................–65°C to 150°C Lead Temperature (Soldering, 10sec)...................300°CORDER PART NUMBER DDB PART*MARKING T JMAX = 125°C, θJA = 250°C/WEXPOSED PAD (PIN 9)PCB CONNECTION OPTIONALConsult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.LBHVLTC4213CDDB LTC4213IDDB ABSOLUTE AXI U RATI GSW W WU PACKAGE/ORDER I FOR ATIOUUW (Note 1)ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V, I SEL = 0 unless otherwise noted. (Note 2)SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITSV CC Bias Supply Voltage ● 2.36V V SENSEP SENSEP Voltage ●06V I CC V CC Supply Current●1.63mA V CC(UVLR)V CC Undervoltage Lockout Release V CC Rising● 1.8 2.07 2.23V ∆V CC(UVHYST)V CC Undervoltage Lockout Hysteresis ●30100160mV I SENSEP SENSEP Input Current V SENSEP = V SENSEN = 5V, Normal Mode 154080µA V SENSEP = V SENSEN = 0, Normal Mode –1±15µA I SENSENSENSEN Input CurrentV SENSEP = V SENSEN = 5V, Normal Mode 154080µA V SENSEP = V SENSEN = 0, Normal Mode –1±15µA V SENSEP = V SENSEN = 5V,50280µAReset Mode or Fault ModeV CBCircuit Breaker Trip Voltage I SEL = 0, V SENSEP = V CC●22.52527.5mV V CB = V SENSEP – V SENSEN I SEL = Floated, V SENSEP = V CC ●455055mV I SEL = V CC, V SENSEP = V CC ●90100110mV V CB(FAST)Fast Circuit Breaker Trip Voltage I SEL = 0, V SENSEP = V CC●63100115mV V CB(FAST)= V SENSEP – V SENSEN I SEL = Floated, V SENSEP = V CC ●126175200mV I SEL = V CC, V SENSEP = V CC ●252325371mV I GATE(UP)GATE Pin Pull Up Current V GATE = 0V●–50–100–150µA I GATE(DN)GATE Pin Pull Down Current ∆V SENSEP – V SENSEN = 200mV, V GATE = 8V ●1040mA ∆V GSMAX External N-Channel Gate Drive V SENSEN = 0, V CC ≥ 2.97V, I GATE = –1µA ● 4.8 6.58V V SENSEN = 0, V CC = 2.3V, I GATE = –1µA ● 2.65 4.38V ∆V GSARMV GS Voltage to Arm Circuit BreakerV SENSEN = 0, V CC ≥ 2.97V ● 4.4 5.47.6V V SENSEN = 0, V CC = 2.3V●2.53.57VTOP VIEWDDB PACKAGE8-LEAD (3mm × 2mm) PLASTIC DFN567894321READY ON I SEL GND V CC SENSEP SENSEN GATE34213f∆V GSMAX – ∆V GSARM Difference Between ∆V GSMAX and V SENSEN = 0, V CC ≥ 2.97V ●0.3 1.1V ∆V GSARMV SENSEN = 0, V CC = 2.3V●0.150.8VV READY(OL)READY Pin Output Low Voltage I READY = 1.6mA, Pull Down Device On ●0.20.4V I READY(LEAK)READY Pin Leakage Current V READY = 5V, Pull Down Device Off ●0±1µA V ON(TH)ON Pin High Threshold ON Rising, GATE Pulls Up ●0.760.80.84V ∆V ON(HYST)ON Pin Hysteresis ON Falling, GATE Pulls Down104090mV V ON(RST)ON Pin Reset Threshold ON Falling, Fault Reset, GATE Pull Down ●0.360.40.44V I ON(IN)ON Pin Input Current V ON = 1.2V●0±1µA ∆V OV Overvoltage Threshold ●0.410.7 1.1V ∆V OV = V SENSEP – V CCt OVOvervoltage Protection Trip Time V SENSEP = V SENSEN = Step 5V to 6.2V 2565160µs t FAULT(SLOW)V CB Trips to GATE Discharging ∆V SENSE Step 0mV to 50mV,●71627µs V SENSEN Falling, V CC = V SENSEP = 5V t FAULT(FAST)V CB(FAST) Trips to GATE Discharging ∆V SENSE Step 0V to 0.3V, V SENSEN Falling,●12.5µs V SENSEP = 5Vt DEBOUNCE Startup De-Bounce Time V ON = 0V to 2V Step to Gate Rising,2760130µs (Exiting Reset Mode)t READY READY Delay Time V GATE = 0V to 8V Step to READY Rising,2250115µs V SENSEP = V SENSEN = 0t OFF Turn-Off Time V ON = 2V to 0.6V Step to GATE Discharging 1.5510µs t ON Turn-On Time V ON = 0.6V to 2V Step to GATE Rising,4816µs (Normal Mode)t RESETReset TimeV ON Step 2V to 0V2080150µsNote 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V, I SEL = 0 unless otherwise noted. (Note 2)SYMBOLPARAMETERCONDITIONSMIN TYP MAX UNITSNote 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.4564213ft RESET vs Temperaturet FAULT(SLOW) vs V CCt FAULT(SLOW) vs Temperaturet FAULT(FAST) vs V CCt FAULT(FAST) vs TemperatureTYPICAL PERFOR A CE CHARACTERISTICSU WSpecifications are at T A = 25°C. V CC = 5Vunless otherwise noted.t F A U L T (F A S T ) (µs )4213 G230.90.80.71.01.11.21.3TEMPERATURE (°C)–50050100125–252575BIAS SUPPLY VOLTAGE (V)2.010t F A U L T (S L O W ) (µs )14121618 3.0 4.0 5.0 6.04213 G202022 2.53.54.55.5TEMPERATURE (°C)–500501001254213 G21–25257510t F A U L T (S L O W ) (µs )141216182022TEMPERATURE (°C)–500501001254213 G19–252575t R E S E T (µs )60708090100BIAS SUPPLY VOLTAGE (V)2.0t F A U L T (F A S T ) (µs )3.04.05.06.04213 G222.53.54.55.50.90.80.71.01.11.21.374213fPI FU CTIO SU U UREADY (Pin 1): READY Status Output. Open drain output that goes high impedance when the external MOSFET is on and the circuit breaker is armed. Otherwise this pin pulls low.ON (Pin 2): ON Control Input. The LTC4213 is in reset mode when the ON pin is below 0.4V. When the ON pin increases above 0.8V, the device starts up and the GATE pulls up with a 100µA current source. When the ON pin drops below 0.76V, the GATE pulls down. To reset a circuit breaker fault, the ON pin must go below 0.4V.I SEL (Pin 3): Threshold Select Input. With the I SEL pin grounded, float or tied to V CC the V CB is set to 25mV, 50mV or 100mV, respectively. The corresponding V CB(FAST)values are 100mV, 175mV and 325mV.GND (Pin 4): Device Ground.GATE (P in 5): GATE D rive Output. An internal charge pump supplies 100µA pull-up current to the gate of the external N-channel MOSFET. Internal circuitry limits thevoltage between the GATE and SENSEN pins to a safe gate drive voltage of less than 8V. When the circuit breaker trips, the GATE pin abruptly pulls to GND.SENSEN (Pin 6): Circuit Breaker Negative Sense Input.Connect this pin to the source of the external MOSFET.During reset or fault mode, the SENSEN pin discharges the output to ground with 280µA.SENSEP (P in 7): Circuit Breaker Positive Sense Input.Connect this pin to the drain of external N-channel MOSFET.The circuit breaker trips when the voltage across SENSEP and SENSEN exceeds V CB . The input common mode range of the circuit breaker is from ground to V CC + 0.2V when V CC < 2.5V. For V CC ≥ 2.5V, the input common mode range is from ground to V CC + 0.4V.V CC (Pin 8): Bias Supply Voltage Input. Normal operation is between 2.3V and 6V. An internal under-voltage lockout circuit disables the device when V CC < 2.07V.Exposed Pad (Pin 9): Exposed pad may be left open or connected to device ground.8910114213fsupply transient dips below 1.97V of less than 80µs are ignored.ON FunctionWhen V ON is below comparator COMP1’s threshold of 0.4V for 80µs, the device resets. The system leaves reset mode if the ON pin rises above comparator COMP2’s threshold of 0.8V and the UVLO condition is met. Leaving reset mode, the GATE pin starts up after a t DEBOUNCE delay of 60µs. When ON goes below 0.76V, the GATE shuts off after a 5µs glitch filter delay. The output is discharged by the external load when V ON is in between 0.4V to 0.8V. At this state, the ON pin can re-enable the GATE if V ON exceeds 0.8V for more than 8µs. Alternatively, the device resets if the ON pin is brought below 0.4V for 80µs. Once reset, the GATE pin restarts only after the t DEBOUNCE 60µs delay at V ON rising above 0.8V. To protect the ON pin from overvoltage stress due to supply transients, a series resistor of greater than 10k is recommended when the ON pin is connected directly to the supply. An external resis-tive divider at the ON pin can be used with COMP2 to set a supply undervoltage lockout value higher than the inter-nal UVLO circuit. An RC filter can be implemented at the ON pin to increase the powerup delay time beyond the internal 60µs delay.Gate FunctionThe GATE pin is held low in reset mode. 60µs after leaving reset mode, the GATE pin is charged up by an internal 100µA current source. The circuit breaker arms when V GATE > V SENSEN + ∆V GSARM . In normal mode operation,the GATE peak voltage is internally clamped to ∆V GSMAX above the SENSEN pin. When the circuit breaker trips, an internal MOSFET shorts the GATE pin to GND, turning off the external MOSFET.READY StatusThe READY pin is held low during reset and at startup. It is pulled high by an external pullup resistor 50µs after the circuit breaker arms. The READY pin pulls low if the circuit breaker trips or the ON pin is pulled below 0.76V, or V CC drops below undervoltage lockout.∆V GSARM and V GSMAXEach MOSFET has a recommended V GS drive voltage where the channel is deemed fully enhanced and R DSON is minimized. Driving beyond this recommended V GS volt-age yields a marginal decrease in R DSON . At startup, the gate voltage starts at ground potential. The GATE ramps past the MOSFET threshold and the load current begins to flow. When V GS exceeds ∆V GSARM , the circuit breaker is armed and enabled. The chosen MOSFET should have a recommended minimum V GS drive level that is lower than ∆V GSARM . Finally, V GS reaches a maximum at ∆V GSMAX.Trip and Reset Circuit BreakerFigure 2 shows the timing diagram of V GATE and V READY after a fault condition. A tripped circuit breaker can be reset either by cycling the V CC bias supply below UVLO thresh-old or pulling ON below 0.4V for >t RESET . Figure 3 shows the timing diagram for a tripped circuit breaker being reset by the ON pin.Calculating Current LimitThe fault current limit is determined by the R DSON of the MOSFET and the circuit breaker voltage V CB .I V R LIMIT CB DSON=()2The R DSON value depends on the manufacturer’s distribu-tion, V GS and junction temperature. Short Kelvin-sense connections between the MOSFET drain and source to the LTC4213 SENSEP and SENSEN pins are strongly recommended.For a selected MOSFET, the nominal load limit current is given by:I V R LIMIT NOM CB NOM DSON NOM ()()()()=3The minimum load limit current is given by:I V R LIMIT MIN CB MIN DSON MAX ()()()()=4APPLICATIO S I FOR ATIOW UUU1213144213fOperating temperature of 0° to 70°C.R DSON @ 25°C = 100%R DSON @ 0°C = 90%R DSON @ 70°C = 120%MOSFET resistance variation:R DSON(NOM) = 15m • 0.82 = 12.3m ΩR DSON(MAX) = 15m • 1.333 • 0.93 • 1.2 = 15m • 1.488= 22.3m ΩR DSON(MIN) = 15m • 0.667 • 0.80 • 0.90 = 15m • 0.480= 7.2m ΩV CB variation:NOM V CB = 25mV = 100%MIN V CB = 22.5mV = 90%MAX V CB = 27.5mV = 110%The current limits are:I LIMIT(NOM) = 25mV/12.3m Ω = 2.03A I LIMIT(MIN) = 22.5mV/22.3m Ω = 1.01A I LIMIT(MAX) = 27.5mV/7.2m Ω = 3.82AFor proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. So this system is suitable for operating load current up to 1A. From this calculation, we can start with the general rule for MOSFET R DSON by assuming maxi-mum operating load current is roughly half of the I LIMIT(NOM). Equation 7 shows the rule of thumb.I V R OPMAX CB NOM DSON NOM =()()•()27Note that the R DSON(NOM) is at the LTC4213 nominal operating ∆V GSMAX rather than at typical vendor spec.Table 1 gives the nominal operating ∆V GSMAX at the various operating V CC . From this table users can refer to the MOSFET’s data sheet to obtain the R DSON(NOM) value.Table 1. Nominal Operating ∆V GSMAX for Typical Bias Supply VoltageV CC (V)∆V GSMAX (V)2.3 4.32.5 5.02.7 5.63.0 6.53.37.05.07.06.07.0Load Supply Power-Up after Circuit Breaker Armed Figure 4 shows a normal power-up sequence for the circuit in Figure 1 where the V IN load supply power-up after circuit breaker is armed. V CC is first powered up by an auxiliary bias supply. V CC rises above 2.07V at time point 1. V ON exceeds 0.8V at time point 2. After a 60µs debounce delay, the GATE pin starts ramping up at time point 3. The external MOSFET starts conducting at time point 4. At time point 5, V GATE exceed ∆V GSARM and the circuit breaker is armed. After 50µs (t READY delay), READY pulls high by an external resistor at time point 6. READY signals the V IN load supply module to start its ramp. The load supply begins soft-start ramp at time point 7. The load supply ramp rate must be slow to prevent circuit breaker tripping as in equation (8).∆∆V t I I C IN OPMAX LOADLOAD<−()8Where I OPMAX is the maximum operating current defined by equation 7.For illustration, V CB = 25mV and R DSON = 3.5m Ω at the nominal operating ∆V GSMAX . The maximum operating current is 3.5A (refer to equation 7). Assuming the load can draw a current of 2A at power-up, there is a margin of 1.5A available for C LOAD of 100µF and V IN ramp rate should be <15V/ms. At time point 8, the current through the MOSFET reduces after C LOAD is fully charged.APPLICATIO S I FOR ATIOW UUU1516174213fThe selected MOSFET V GS absolute maximum rating should meet the LTC4213 maximum ∆V GSMAX of 8V.Other MOSFET criteria such as V BDSS , I DMAX , and R DSON should be reviewed. Spikes and ringing above maximum operating voltage should be considered when choosing V BDSS . I DMAX should be greater than the current limit. The maximum operating load current is determined by the R DSON value. See the section on “Calculating Current Limit” for details.Supply RequirementsThe LTC4213 can be powered from a single supply or dual supply system. The load supply is connected to the SENSEP pin and the drain of the external MOSFET. In the single supply case, the V CC pin is connected to the load supply, preferably with an RC filter. With dual supplies,V CC is connected to an auxiliary bias supply V AUX where V AUX voltage should be greater or equal to the load supply voltage. The load supply voltage must be capable of sourcing more current than the circuit breaker limit. If the load supply current limit is below the circuit breaker trip current, the LTC4213 may not react when the output overloads. Furthermore, output overloads may trigger UVLO if the load supply has foldback current limit in a single supply system.V IN Transient and Overvoltage ProtectionInput transient spikes are commonly observed whenever the LTC4213 responds to overload. These spikes can be large in amplitude, especially given that large decoupling capacitors are absent in hot swap environments. These short spikes can be clipped with a transient suppressor of adequate voltage and power rating. In addition, the LTC4213can detect a prolonged overvoltage condition. WhenAPPLICATIO S I FOR ATIOW UUU point 6 should be within the circuit breaker limits. Other-wise, the system fails to start and the circuit breaker trips immediately after arming. In most applications additional external gate capacitance is not required unless C LOAD is large and startup becomes problematic. If an external gate capacitor is employed, its capacitance value should not be excessive unless it is used with a series resistor. This is because a big gate capacitor without resistor slows down the GATE turn off during a fault. An alternative method would be a stepped I SEL pin to allow a higher current limit during startup.In the event of output short circuit or a severe overload, the load supply can collapse during GATE ramp up due to load supply current limit. The chosen MOSFET must withstand this possible brief short circuit condition before time point 6 where the circuit breaker is allowed to trip. Bench short circuit evaluation is a practical verification of a reliable design. To have current limit while powering a MOSFET into short circuit conditions, it is preferred that the load supply sequences to turn on after the circuit breaker is armed as described in an earlier section.Power-Off CycleThe system can be powered off by toggling the ON pin low.When ON is brought below 0.76V for 5µs, the GATE and READY pins are pulled low. The system resets when ON is brought below 0.4V for 80µs.MOSFET SelectionThe LTC4213 is designed to be used with logic (5V) and sub-logic (3V) MOSFETs for V CC potentials above 2.97V with ∆V GSMAX exceeding 4.5V. For a V CC supply range between 2.3V and 2.97V, sub-logic MOSFETs should be used as the minimum ∆V GSMAX is less than 4.5V.1819Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.201630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2005LT/TP 0405 500 • PRINTED IN USA。

LTC1871IMS-1#PBF资料

118711fbT YPICAL APPLICATIONF EATURESA PPLICATIONSD ESCRIPTION Current Mode Boost,Flyback and SEPIC Controller The L TC ®1871-1 is a wide input range, current mode, boost, ﬂ yback or SEPIC controller that drives an N-channel power MOSFET and requires very few external components. It eliminates the need for a current sense resistor by utilizing the power MOSFET’s on-resistance, thereby maximizing efﬁ ciency. Higher output voltage applications are possible with the L TC1871-1 by connecting the SENSE pin to a resistor in the source of the power MOSFET .The IC’s operating frequency can be set with an external resistor over a 50kHz to 1MHz range, and can be synchro-nized to an external clock using the MODE/SYNC pin.The L TC1871-1 differs from the L TC1871 by having a lower pulse skip threshold, making it ideal for applica-tions requiring constant frequency operation at light loads. The lower pulse skip threshold also helps maintain constant frequency operation in applications with a wide input voltage range. For applications requiring primary-to-secondary side isolation, please refer to the L TC1871 datasheet.The L TC1871-1 is available in the 10-lead MSOP package.Efﬁ ciency of Figure 1nHigh Efﬁ ciency (No Sense Resistor Required)n Wide Input Voltage Range: 2.5V to 36V n Current Mode Control Provides Excellent T ransient Responsen High Maximum Duty Cycle (92% Typ)n ±2% RUN Pin Threshold with 100mV Hysteresis n ±1% Internal Voltage Referencen Ultra Low Pulse Skip Threshold for Wide Input Range Applicationsn Micropower Shutdown: I Q= 10μA n Programmable Operating Frequency(50kHz to 1MHz) with One External Resistor n Synchronizable to an External Clock Up to 1.3 × f OSCn User-Controlled Pulse Skip or Burst Mode ® Operationn Internal 5.2V Low Dropout Voltage Regulator n Output Overvoltage Protectionn Capable of Operating with a Sense Resistor for High Output Voltage Applications n Small 10-Lead MSOP PackagenTelecom Power Suppliesn Portable Electronic EquipmentL , L T , L TC, L TM and Burst Mode are registered trademarks of Linear Technology Corporation. No R SENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.Figure 1. High Efﬁ ciency 3.3V Input, 5V Output Boost Converter (Bootstrapped)INOUTC IN : TAIYO YUDEN JMK325BJ226MM C OUT1: PANASONIC EEFUEOJ151RC OUT2: TAIYO YUDEN JMK325BJ226MMD1: MBRB2515LL1: SUMIDA CEP125-H 1R0MH M1: FAIRCHILD FDS7760AOUTPUT CURRENT (A)30E F F I C I E N C Y (%)9010080507060400.0010.111018711 F01b0.01218711fbP IN CONFIGURATIONA BSOLUTE MAXIMUM RATINGS V IN Voltage ............................................... –0.3V to 36V INTV CC Voltage ............................................ –0.3V to 7V INTV CC Output Current .......................................... 50mA GATE Voltage ............................ –0.3V to V INTVCC + 0.3V I TH , FB Voltages ....................................... –0.3V to 2.7V RUN, MODE/SYNC Voltages ....................... –0.3V to 7V FREQ Voltage ............................................–0.3V to 1.5V SENSE Pin Voltage .................................... –0.3V to 36V Operating Junction Temperature Range (Note 2)L TC1871E-1 .........................................–40°C to 85°C L TC1871I-1 ........................................–40°C to 125°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ..................300°C(Note 1)12345RUNI TH FB FREQ MODE/SYNC109876SENSE V IN INTV CC GATE GNDTOP VIEWMS PACKAGE10-LEAD PLASTIC MSOP T JMAX = 125°C, θJA = 120°C/WORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC1871EMS-1#PBF L TC1871EMS-1#TRPBF L TCTV 10-Lead Plastic MSOP –40°C to 85°C L TC1871IMS-1#PBF L TC1871IMS-1#TRPBF L TCTV 10-Lead Plastic MSOP –40°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC1871EMS-1L TC1871EMS-1#TR L TCTV 10-Lead Plastic MSOP –40°C to 85°C L TC1871IMS-1L TC1871IMS-1#TRL TCTV10-Lead Plastic MSOP–40°C to 125°CConsult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges.For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear .com/tapeandreel/SYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITSMain Control LoopV IN(MIN)Minimum Input Voltage2.5V I-Grade (Note 2)●2.5VI QInput Voltage Supply Current (Note 4)Continuous ModeV MODE/SYNC = 5V , V FB = 1.4V , V ITH = 0.75V 5501000μA V MODE/SYNC = 5V , V FB = 1.4V , V ITH = 0.75V ,I-Grade (Note 2)●5501000μA Burst Mode Operation, No LoadV MODE/SYNC = 0V , V ITH = 0V (Note 5)250500μA V MODE/SYNC = 0V , V ITH = 0V (Note 5),I-Grade (Note 2)●250500μA Shutdown ModeV RUN = 0V1020μA V RUN = 0V , I-Grade (Note 2)●1020μAELECTRICAL CHARACTERISTICSThe l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V IN = 5V , V RUN = 1.5V , R FREQ = 80k, V MODE/SYNC = 0V , unless otherwise speciﬁ ed.E LECTRICAL CHARACTERISTICSThel denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V IN = 5V, V RUN = 1.5V, R FREQ = 80k, V MODE/SYNC = 0V, unless otherwise speciﬁ ed. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V RUN+Rising RUN Input Threshold Voltage 1.348VV RUN–Falling RUN Input Threshold Voltage●1.2231.1981.248 1.2731.298VVV RUN(HYST)RUN Pin Input Threshold Hysteresis50100150mVI-Grade (Note 2)●35100175mV I RUN RUN Input Current160nAV FB Feedback Voltage V ITH = 0.4V (Note 5)●1.2181.2121.230 1.2421.248VVV ITH = 0.4V (Note 5), I-Grade (Note 2)● 1.205 1.255V I FB FB Pin Input Current V ITH = 0.4V (Note 5)1860nAΔV FB ΔV IN Line Regulation 2.5V ≤ V IN ≤ 30V0.0020.02%/V2.5V ≤ V IN ≤ 30V, I-Grade (Note 2)●0.0020.03%/VΔV FB ΔV ITH Load Regulation V MODE/SYNC = 0V, V ITH = 0.5V to 0.9V (Note 5)●–1–0.1%V MODE/SYNC = 0V, V ITH = 0.5V to 0.9V (Note 5)I-Grade (Note 2)●–1–0.1%ΔV FB(OV)ΔFB Pin, Overvoltage Lockout V FB(OV) – V FB(NOM) in Percent 2.5610% g m Error Ampliﬁ er T ransconductance I TH Pin Load = ±5μA (Note 5)650μmho V ITH(BURST)Burst Mode Operation I TH Pin Voltage Falling I TH Voltage (Note 5)195mV V SENSE(MAX)Maximum Current Sense Input Threshold Duty Cycle < 20%120150180mVDuty Cycle < 20%, I-Grade (Note 2)●100200mV I SENSE(ON)SENSE Pin Current (GATE High)V SENSE = 0V3550μA I SENSE(OFF)SENSE Pin Current (GATE Low)V SENSE = 30V0.15μA Oscillatorf OSC Oscillator Frequency R FREQ = 80k250300350kHzR FREQ = 80k, I-Grade (Note 2)●250300350kHz Oscillator Frequency Range501000kHzI-Grade (Note 2)●501000kHz D MAX Maximum Duty Cycle879297%I-Grade (Note 2)●879297%f SYNC/f OSC Recommended Maximum SynchronizedFrequency Ratio f OSC = 300kHz (Note 6) 1.25 1.30 f OSC = 300kHz (Note 6), I-Grade (Note 2)● 1.25 1.30t SYNC(MIN)MODE/SYNC Minimum Input Pulse Width V SYNC = 0V to 5V25ns t SYNC(MAX)MODE/SYNC Maximum Input Pulse Width V SYNC = 0V to 5V0.8/f OSC ns V IL(MODE)Low Level MODE/SYNC Input Voltage0.3VI-Grade (Note 2)●0.3V V IH(MODE)High Level MODE/SYNC Input Voltage 1.2VI-Grade (Note 2)● 1.2V R MODE/SYNC MODE/SYNC Input Pull-Down Resistance50kΩV FREQ Nominal FREQ Pin Voltage0.62V318711fb418711fbE LECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The L TC1871E-1 is guaranteed to meet performance speciﬁ cations from 0°C to 85°C junction temperature. Speciﬁ cations over the –40°C to 85°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TC1871I-1 is guaranteed over the full –40°C to 125°C operating junction temperature range.Note 3: T J is calculated from the ambient temperature T A and power dissipation P D according to the following formula: T J = T A + (P D • 110°C/W)Note 4: The dynamic input supply current is higher due to power MOSFET gate charging (Q G • f OSC ). See Applications Information.Note 5: The L TC1871-1 is tested in a feedback loop which servos V FB to the reference voltage with the I TH pin forced to the midpoint of its voltage range (0.3V ≤ V ITH ≤ 1.2V , midpoint = 0.75V).Note 6: In a synchronized application, the internal slope compensation gain is increased by 25%. Synchronizing to a signiﬁ cantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%.Note 7: Rise and fall times are measured at 10% and 90% levels.The l denotes the speciﬁ cations which apply over the full operatingtemperature range, otherwise speciﬁ cations are at T A = 25°C. V IN = 5V , V RUN = 1.5V , R FREQ = 80k, V MODE/SYNC = 0V , unless otherwise speciﬁed.SYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITSLow Dropout RegulatorV INTVCC INTV CC Regulator Output Voltage V IN = 7.5V5.0 5.2 5.4V V IN = 7.5V , I-Grade (Note 2)●5.05.2 5.4V ΔV INTVCC ΔV IN1INTV CC Regulator Line Regulation 7.5V ≤ V IN ≤ 15V 825mV ΔV INTVCC ΔV IN2INTV CC Regulator Line Regulation15V ≤ V IN ≤ 30V70200mV V LDO(LOAD)INTV CC Load Regulation 0 ≤ I INTVCC ≤ 20mA, V IN = 7.5V –2–0.2%V DROPOUT INTV CC Regulator Dropout Voltage INTV CC Load = 20mA 280mVI INTVCC Bootstrap Mode INTV CC SupplyRUN = 0V , SENSE = 5V 1020μA I-Grade (Note 2)●30μAGATE Driver t r GATE Driver Output Rise Time C L = 3300pF (Note 7)17100ns t fGATE Driver Output Fall TimeC L = 3300pF (Note 7)8100nsTYPICAL PERFORMANCE CHARACTERISTICSFB Voltage vs TempFB Voltage Line RegulationFB Pin Current vs TemperatureTEMPERATURE (°C)–50F B V O L T A G E (V )1.231.2415018711 G011.221.2150100–2525751251.25V IN (V)01.229F B V O L T AG E (V )1.2301.231510152018711 G02253035TEMPERATURE (°C)–500F B P I N C U R R E N T (n A )1020304060–25250501007518711 G0312515050518711fbT YPICAL PERFORMANCE CHARACTERISTICS Shutdown Mode I Q vs V INShutdown Mode I Q vs TemperatureBurst Mode I Q vs V INBurst Mode I Q vs TemperatureDynamic I Q vs FrequencyGate Drive Rise and Fall Time vs C LV IN (V)00S H U T D O W N M O D E I Q (μA )10201020304018711 G0430TEMPERATURE (°C)–500S H U T D O W N M O D E I Q (μA )5101520–25255018711 G0575100125150V IN (V)00B u r s t M o d e I Q (μA )100200300400600102018711 G063040500TEMPERATURE (°C)–500B u r s t M o d e I Q (μA )200500507518711 G07100400300–2525100125150FREQUENCY (kHz)00I Q (m A )268108001818711 G08440012006002001000121416C L (pF)00T I M E (n s )1020304060200040006000800018711 G09100001200050RUN Thresholds vs V INRUN Thresholds vs TemperatureR T vs FrequencyV IN (V)01.2R U N T H R E S H O L D S (V )1.31.41020304018711 G101.5TEMPERATURE (°C)–50R U N T H R E S H O L D S (V )1.301.3515018711 G111.251.2050100–2525751251.40FREQUENCY (kHz)100R T (k Ω)300100018711 G12101002001000900800700600500400618711fbTYPICAL PERFORMANCE CHARACTERISTICSFrequency vs TemperatureMaximum Sense Threshold vs TemperatureSENSE Pin Current vs TemperatureINTV CC Load RegulationINTV CC Line RegulationINTV CC Dropout Voltage vs Current, TemperatureRUN (Pin 1): The RUN pin provides the user with an accurate means for sensing the input voltage and pro-gramming the start-up threshold for the converter . The falling RUN pin threshold is nominally 1.248V and the comparator has 100mV of hysteresis for noise immunity. When the RUN pin is below this input threshold, the IC is shut down and the V IN supply current is kept to a low value (typ 10μA). The Absolute Maximum Rating for the voltage on this pin is 7V .I TH (Pin 2): Error Ampliﬁ er Compensation Pin. The current comparator input threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.40V .FB (Pin 3): Receives the feedback voltage from the external resistor divider across the output. Nominal voltage for this pin in regulation is 1.230V .FREQ (Pin 4): A resistor from the FREQ pin to ground programs the operating frequency of the chip. The nominal voltage at the FREQ pin is 0.6V .TEMPERATURE (°C)–50275G A T E F R E Q U E N C Y (k H z )2802902953003253100507518711 G13285315320305–2525100125150TEMPERATURE (°C)–50140M A X S E N S E T H R E S H O L D (m V )145150155160–25255018711 G1475100125150TEMPERATURE (°C)–5025S E N S E P I N C U R R E N T (μA )3035507518711 G15–2525100125150INTV CC LOAD (mA)0I N T V C C V O L T A G E (V )5.230508018711 G165.15.01020406070V IN (V)05.1I N T V C C V O L T A G E (V )5.25.31020304018711 G175.45152535INTV CC LOAD (mA)00D R O P O U T V O L T A GE (m V )5015020025050035051018711 G181004004503001520PIN FUNCTIONS718711fbP IN FUNCTIONS MODE/SYNC (Pin 5): This input controls the operating mode of the converter and allows for synchronizing the operating frequency to an external clock. If the MODE/SYNC pin is connected to ground, Burst Mode operation is enabled. If the MOD E/SYNC pin is connected to INTV CC , or if an external logic-level synchronization signal is ap-plied to this input, Burst Mode operation is disabled and the IC operates in a continuous mode.GND (Pin 6): Ground Pin. GATE (Pin 7): Gate Driver Output.I NTV CC (Pin 8): The Internal 5.20V Regulator Output. The gate driver and control circuits are powered from this voltage. Decouple this pin locally to the IC groundwith a minimum of 4.7μF low ESR tantalum or ceramiccapacitor .V IN (Pin 9): Main Supply Pin. Must be closely decoupledto ground.SENSE (Pin 10): The Current Sense Input for the Control Loop. Connect this pin to the drain of the power MOSFET for V DS sensing and highest efﬁ ciency. Alternatively, theSENSE pin may be connected to a resistor in the sourceof the power MOSFET . Internal leading edge blanking isprovided for both sensing methods.BLOCK DIAGRAMIN–+–+818711fbOPERATIONFigure 2. Using the SENSE Pin On the L TC1871-1Main Control LoopThe L TC1871-1 is a constant frequency, current mode controller for DC/DC boost, SEPIC and ﬂ yback converter applications. The L TC1871-1 is distinguished from con-ventional current mode controllers because the current control loop can be closed by sensing the voltage drop across the power MOSFET switch instead of across a discrete sense resistor , as shown in Figure 2. This sensing technique improves efﬁ ciency, increases power density, and reduces the cost of the overall solution.which causes the current comparator C1 to trip at a higher peak inductor current value. The average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation.The nominal operating frequency of the L TC1871-1 is programmed using a resistor from the FREQ pin to ground and can be controlled over a 50kHz to 1000kHz range. In addition, the internal oscillator can be synchronized to an external clock applied to the MODE/SYNC pin and can be locked to a frequency between 100% and 130% of its nominal value. When the MODE/SYNC pin is left open, it is pulled low by an internal 50k resistor and Burst Mode operation is enabled. If this pin is taken above 2V or an external clock is applied, Burst Mode operation is disabled and the IC operates in continuous mode. With no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple.The RUN pin controls whether the IC is enabled or is in a low current shutdown state. A micropower 1.248V reference and comparator C2 allow the user to program the supply voltage at which the IC turns on and off (comparator C2 has 100mV of hysteresis for noise immunity). With the RUN pin below 1.248V , the chip is off and the input supply current is typically only 10μA.An overvoltage comparator OV senses when the FB pin exceeds the reference voltage by 6.5% and provides a reset pulse to the main RS latch. Because this RS latch is reset-dominant, the power MOSFET is actively held off for the duration of an output overvoltage condition.The L TC1871-1 can be used either by sensing the voltage drop across the power MOSFET or by connecting the SENSE pin to a conventional shunt resistor in the source of the power MOSFET , as shown in Figure 2. Sensing the voltage across the power MOSFET maximizes converter efﬁ ciency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36V). By connecting the SENSE pin to a resistor in the source of the power MOSFET , the user is able to program output voltages signiﬁ cantly greater than 36V .OUT2a. SENSE Pin Connection forMaximum Efﬁciency (V SW < 36V)OUTV INGNDOUT18711 F022b. SENSE Pin Connection for Precise Control of Peak Current or for V SW > 36V OUTV INGNDFor circuit operation, please refer to the Block Diagram of the IC and Figure 1. In normal operation, the power MOSFET is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the latch. The divided-down output voltage is compared to an internal 1.230V reference by the error ampliﬁ er EA, which outputs an error signal at the I TH pin. The voltage on the I TH pin sets the current comparator C1 input threshold. When the load current increases, a fall in the FB voltage relative to the reference voltage causes the I TH pin to rise,918711fbO PERATION MOSFET R DS(ON). If the I TH pin drops below 0.175V , the Burst Mode comparator B1 will turn off the power MOSFET and scale back the quiescent current of the IC to 250μA (sleep mode). In this condition, the load current will be supplied by the output capacitor until the I TH voltage rises above the 50mV hysteresis of the burst comparator . At light loads, short bursts of switching (where the average inductor current is 20% of its maximum value) followed by long periods of sleep will be observed, thereby greatly improving converter efﬁ ciency. Oscilloscope waveforms illustrating Burst Mode operation are shown in Figure 3.Pulse-Skip Mode OperationWith the MODE/SYNC pin tied to a DC voltage above 2V , Burst Mode operation is disabled. The internal, 0.525V buffered I TH burst clamp is removed, allowing the I TH pin to directly control the current comparator from no load to full load. With no load, the I TH pin is driven below 0.175V , the power MOSFET is turned off and sleep mode is invoked. Oscilloscope waveforms illustrating this mode of operation are shown in Figure 4.When an external clock signal drives the MOD E/SYNC pin at a rate faster than the chip’s internal oscillator , the oscillator will synchronize to it. In this synchronized mode, Burst Mode operation is disabled. The constant frequency associated with synchronized operation provides a more controlled noise spectrum from the converter , at the ex-pense of overall system efﬁ ciency of light loads.Programming the Operating ModeFor applications where maximizing the efﬁ ciency at very light loads (e.g., <100μA) is a high priority, the current in the output divider could be decreased to a few micro-amps and Burst Mode operation should be applied (i.e., the MODE/SYNC pin should be connected to ground). In applications where ﬁ xed frequency operation is more critical than low current efﬁ ciency, or where the lowest output ripple is desired, pulse-skip mode operation should be used and the MODE/SYNC pin should be connected to the INTV CC pin. This allows discontinuous conduction mode (DCM) operation down to near the limit deﬁ ned by the chip’s minimum on-time (about 175ns). Below this output current level, the converter will begin to skip cycles in order to maintain output regulation. Figures 3 and 4 show the light load switching waveforms for Burst Mode and pulse-skip mode operation for the converter in Figure 1.Burst Mode OperationBurst Mode operation is selected by leaving the MODE/SYNC pin unconnected or by connecting it to ground. In normal operation, the range on the I TH pin corresponding to no load to full load is 0.30V to 1.2V . In Burst Mode opera-tion, if the error ampliﬁ er EA drives the I TH voltage below 0.525V , the buffered I TH input to the current comparator C1 will be clamped at 0.525V (which corresponds to 25% of maximum load current). The inductor current peak is then held at approximately 30mV divided by the powerFigure 3. L TC1871-1 Burst Mode Operation (MODE/SYNC = 0V) at Low Output Current Figure 4. L TC1871-1 Low Output Current Operation with Burst Mode Operation Disabled (MODE/SYNC = INTV CC )UTIVI L IV V IN = 3.3V V OUT = 5V I OUT = 500mAMODE/SYNC = 0V(Burst Mode OPERATION)V OUT 50mV/DIVI L 5A/DIV2μs/DIV18711 F04V IN = 3.3V V OUT = 5V I OUT = 500mAMODE/SYNC = INTV CC (PULSE-SKIP MODE)1018711fbWhen the oscillator’s internal logic circuitry detects a synchronizing signal on the MOD E/SYNC pin, the in-ternal oscillator ramp is terminated early and the slope compensation is increased by approximately 30%. As a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the IC be programmed to be about 75% of the external clock frequency. Attempting to synchronize to too high an external frequency (above 1.3f O ) can result in inadequate slope compensation and possible subharmonic oscillation (or jitter).The external clock signal must exceed 2V for at least 25ns, and should have a maximum duty cycle of 80%, as shown in Figure 5. The MOSFET turn on will synchronize to the rising edge of the external clock signal.0.6V , and the current that ﬂ ows into the FREQ pin is used to charge and discharge an internal oscillator capacitor . A graph for selecting the value of R T for a given operating frequency is shown in Figure 6.APPLICATIONS INFORMATIONFigure 5. MODE/SYNC Clock Input and Switching Waveforms for Synchronized OperationFigure 6. Timing Resistor (R T ) Value18711 F05I LProgramming the Operating FrequencyThe choice of operating frequency and inductor value is a tradeoff between efﬁ ciency and component size. Low frequency operation improves efﬁ ciency by reducing MOSFET and diode switching losses. However , lower frequency operation requires more inductance for a given amount of load current.The L TC1871-1 uses a constant frequency architecture that can be programmed over a 50kHz to 1000kHz range with a single external resistor from the FREQ pin to ground, as shown in Figure 1. The nominal voltage on the FREQ pin isFREQUENCY (kHz)100R T (k Ω)300100018711 F061010020010009008007006005004000INTV CC Regulator Bypassing and OperationAn internal, P-channel low dropout voltage regulator pro-duces the 5.2V supply which powers the gate driver and logic circuitry within the L TC1871-1, as shown in Figure 7. The INTV CC regulator can supply up to 50mA and must be bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7μF tantalum or ceramic capacitor . Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver .For input voltages that don’t exceed 7V (the absolute maximum rating for this pin), the internal low dropout regulator in the L TC1871-1 is redundant and the INTV CC pin can be shorted directly to the V IN pin. With the INTV CC pin shorted to V IN , however , the divider that programs the regulated INTV CC voltage will draw 10μA of current from the input supply, even in shutdown mode. For applications that require the lowest shutdown mode input supply cur-rent, do not connect the INTV CC pin to V IN . Regardless of whether the INTV CC pin is shorted to V IN or not, it is always necessary to have the driver circuitry bypassed with a 4.7μF tantalum or low ESR ceramic capacitor to ground immediately adjacent to the INTV CC and GND pins.In an actual application, most of the IC supply current is used to drive the gate capacitance of the power MOSFET .APPLICATIONS INFORMATIONFigure 7. Bypassing the LDO Regulator and Gate Driver SupplyAs a result, high input voltage applications in which a large power MOSFET is being driven at high frequencies can cause the L TC1871-1 to exceed its maximum junc-tion temperature rating. The junction temperature can be estimated using the following equations:I Q(TOT) ≈ I Q + f • Q GP IC = V IN • (I Q + f • Q G)T J = T A + P IC • R TH(JA)The total quiescent current I Q(TOT) consists of the static supply current (I Q) and the current required to charge and discharge the gate of the power MOSFET. The 10-pin MSOP package has a thermal resistance of R TH(JA) = 120°C/W. As an example, consider a power supply with V IN = 5V and V O = 12V at I O = 1A. The switching frequency is 500kHz, and the maximum ambient temperature is 70°C. The power MOSFET chosen is the IRF7805, which has a maximum R DS(ON) of 11mΩ (at room temperature) and a maximum total gate charge of 37nC (the temperature coefﬁ cient of the gate charge is low).I Q(TOT) = 600μA + 37nC • 500kHz = 19.1mAP IC = 5V • 19.1mA = 95mWT J = 70°C + 120°C/W • 95mW = 81.4°C This demonstrates how signiﬁ cant the gate charge current can be when compared to the static quiescent current in the IC.To prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high V IN. A tradeoff between the operating frequency and the size of the power MOSFET may need to be made in order to maintain a reliable IC junction temperature. Prior to lowering the operating frequency, however, be sure to check with power MOSFET manufacturers for their latest-and-greatest low Q G, low R DS(ON) devices. Power MOSFET manufacturing tech-nologies are continually improving, with newer and better performance devices being introduced almost yearly. Output Voltage ProgrammingThe output voltage is set by a resistor divider according to the following formula:V O=1.230V•1+R2R1The external resistor divider is connected to the output as shown in Figure 1, allowing remote voltage sensing. The resistors R1 and R2 are typically chosen so that theAPPLICATIONS INFORMATIONerror caused by the current ﬂ owing into the FB pin dur-ing normal operation is less than 1% (this translates to a maximum value of R1 of about 250k).Programming Turn-On and Turn-Off Thresholds with the RUN PinThe L TC1871-1 contains an independent, micropower volt-age reference and comparator detection circuit that remains active even when the device is shut down, as shown in Figure 8. This allows users to accurately program an input voltage at which the converter will turn on and off. The falling threshold voltage on the RUN pin is equal to the internal reference voltage of 1.248V . The comparator has 100mV of hysteresis to increase noise immunity.The turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas:V IN(OFF)=1.248V •1+R2R1V IN(ON)=1.348V •1+R2R1The resistor R1 is typically chosen to be less than 1M.For applications where the RUN pin is only to be used as a logic input, the user should be aware of the 7V Absolute Maximum Rating for this pin! The RUN pin can be con-nected to the input voltage through an external 1M resistor , as shown in Figure 8c, for “always on” operation.Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN PinFigure 8c. External Pull-Up Resistor On RUN Pin for “Always On” OperationFigure 8b. On/Off Control Using External LogicINPUT SUPPLY+–INPUT SUPPLY+–。

ADuM6400_6401_6402_6403_6404-6400四路输入、四通道隔离芯片

Regulated 3.3 V or 5 V output Up to 500 mW output power Quad dc-to-25 Mbps (NRZ) signal isolation channels Schmitt trigger inputs 16-lead SOIC package with 7.6 mm creepage High temperature operation: 105°C High common-mode transient immunity: >25 kV/μs
Electrical Characteristics—5 V Primary Input Supply/5 V Secondary Isolated Supply .......................................................... 3 Electrical Characteristics—3.3 V Primary Input Supply/3.3 V Secondary Isolated Supply .......................................................... 5 Electrical Characteristics—5 V Primary Input Supply/3.3 V Secondary Isolated Supply .......................................................... 6 Package Characteristics ............................................................... 8 Regulatory Approvals................................................................... 8 Insulation and Safety-Related Specifications............................ 8 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 9 Recommended Operating Conditions ...................................... 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10

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16404fTYPICAL APPLICATIONFEATURESAPPLICATIONSDESCRIPTIONHigh Precision Fully Differential Input/Output Ampliﬁ er/DriverSingle-Ended Input to Differential Output with Common Mode Level ShiftingnFully Differential Input and Outputn Low Noise: 1.5nV/√Hz RTI n Very Low Distortion: L TC6404-1 (2V P-P , 10MHz): –91dBc L TC6404-2 (2V P-P , 10MHz): –96dBc L TC6404-4 (2V P-P , 10MHz): –101dBc n Closed-Loop –3dB Bandwidth: 600MHz n Slew Rate: 1200V/μs (L TC6404-4)n Adjustable Output Common Mode Voltage n Rail-to-Rail Output Swingn Input Range Extends to Ground n Large Output Current: 85mA (Typ)n DC Voltage Offset < 2mV (Max)n Low Power Shutdown n Tiny 3mm× 3mm × 0.75mm 16-Pin QFN Package nDifferential Input A/D Converter Drivern Single-Ended to Differential Conversion/Ampliﬁ cation n Common Mode Level T ranslationnLow Voltage, Low Noise, Signal ProcessingThe L TC ®6404 is a family of AC precision, very low noise,low distortion, fully differential input/output ampliﬁ ers optimized for 3V , single supply operation.The L TC6404-1 is unity-gain stable. The L TC6404-2 is designed for closed-loop gains greater than or equal to 2V/V . The L TC6404-4 is designed for closed-loop gains greater than or equal to 4V/V . The L TC6404 closed-loop bandwidth extends from DC to 600MHz. In addition to the normal unﬁ ltered outputs (OUT + and OUT –), the L TC6404 has a built-in 88.5MHz differential single-pole lowpass ﬁ lter and an additional pair of ﬁ ltered outputs (OUTF +, OUTF –). An input referred voltage noise of 1.5nV/√Hz make the L TC6404 able to drive state-of-the-art 16-/18-bit ADCs while operating on the same supply voltage, saving system cost and power . The L TC6404 is characterized, and maintains its performance for supplies as low as 2.7V and can operate on supplies up to 5.25V . It draws only 27.3mA, and has a hardware shutdown feature which reduces cur-rent consumption to 250μA.The L TC6404 family is available in a compact 3mm × 3mm 16-pin leadless QFN package and operates over a –40°C to 125°C temperature range.L , L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.1.5VDC6404 TA011V P-P1.5VDC1V P-PL TC6404-4 Distortion vs FrequencyFREQUENCY (MHz)0.1–100H D 2, H D 3 (d B c )–90–80–70–6011010064044 G16–110–120–130–50–4026404fABSOLUTE MAXIMUM RATINGSTotal Supply Voltage (V + to V –) ................................5.5V Input Voltage:IN +, IN –, V OCM , SHDN (Note 2) ......................V + to V –Input Current:IN +, IN –, V OCM , SHDN (Note 2) ........................±10mA Output Short-Circuit Duration (Note 3) ............Indeﬁ nite Output Current (Continuous):(OUTF +, OUTF –) DC + AC RMS ...........................±40mA Operating Temperature Range (Note 4)..–40°C to 125°C Speciﬁ ed Temperature Range (Note 5) ..–40°C to 125°C Junction Temperature ...........................................150°C Storage Temperature Range ...................–65°C to 150°C(Note 1)16171514135678TOP VIEWUD PACKAGE16-LEAD (3mm s 3mm) PLASTIC QFN91011124321SHDN V +V –V OCMV –V +V +V –N CI N +O U T –O U T F –N CI N –O U T +O U T F +T JMAX = 150°C, θJA = 68°C/W , θJC = 4.2°C/WEXPOSED PAD (PIN 17) IS V –, MUST BE SOLDERED TO PCBORDER INFORMATIONPIN CONFIGURATIONLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTIONSPECIFIED TEMPERATURE RANGE L TC6404CUD-1#PBF L TC6404CUD-1#TRPBF LCLW 16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C L TC6404IUD-1#PBF L TC6404IUD-1#TRPBF LCLW 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C L TC6404HUD-1#PBF L TC6404HUD-1#TRPBF LCLW 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C L TC6404CUD-2#PBF L TC6404CUD-2#TRPBF LCLX 16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C L TC6404IUD-2#PBF L TC6404IUD-2#TRPBF LCLX 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C L TC6404HUD-2#PBF L TC6404HUD-2#TRPBF LCLX 16-Lead (3mm × 3mm) Plastic QFN –40°C to 125°C L TC6404CUD-4#PBF L TC6404CUD-4#TRPBF LCL Y 16-Lead (3mm × 3mm) Plastic QFN 0°C to 70°C L TC6404IUD-4#PBF L TC6404IUD-4#TRPBF LCL Y 16-Lead (3mm × 3mm) Plastic QFN –40°C to 85°C L TC6404HUD-4#PBFL TC6404HUD-4#TRPBFLCL Y16-Lead (3mm × 3mm) Plastic QFN–40°C to 125°CConsult L TC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container .Consult L TC Marketing for information on non-standard lead based ﬁ nish parts.For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear .com/tapeandreel/The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V+ = 3V, V– = 0V, V CM = V OCM = V ICM = Mid-Supply,V SHDN = OPEN, R L = OPEN, R BAL = 100k (See Figure 1). For the L TC6404-1: R I = 100Ω, R F = 100Ω. For the L TC6404-2: R I = 100Ω,R F = 200Ω. For the L TC6404-4: R I = 100Ω, R F = 402Ω, unless otherwise noted. V S is deﬁ ned (V+ – V–). V OUTCM = (V OUT+ + V OUT–)/2.V ICM is deﬁ ned (V IN+ + V IN–)/2. V OUTDIFF is deﬁ ned (V OUT+ – V OUT–). V INDIFF = (V INP – V INM)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OSDIFF Differential Offset Voltage (Input Referred)V S = 2.7V to 5.25V l±0.5±2mV ΔV OSDIFF/ΔT Differential Offset Voltage Drift (Input Referred)V S = 2.7V to 5.25V1μV/°C I B Input Bias Current (Note 6)V S = 2.7V to 5.25V l–60–230μA ΔI B/ΔT Input Bias Current Drift (Note 6)V S = 2.7V to 5.25V0.01μA/°C I OS Input Offset Current (Note 6)V S = 2.7V to 5.25V l±1±10μAR IN Input Resistance Common ModeDifferential Mode 10003kΩkΩC IN Input Capacitance1pF e n Differential Input Referred Noise Voltage Density f = 1MHz 1.5nV/√Hz i n Input Noise Current Density f = 1MHz3pA/√Hze nVOCM Input Referred Common Mode Noise VoltageDensity f = 1MHz, Referred to V OCM PinL TC6404-1L TC6404-2L TC6404-4910.527nV/√HznV/√HznV/√HzV ICMR (Note 7)Input Signal Common Mode Range V S = 3VV S = 5Vll1.63.6VVCMRRI (Note 8)Input Common Mode Rejection Ratio(Input Referred) ΔV ICM/ΔV OSDIFFV S = 3V, ΔV CM = 0.75VV S = 5V, ΔV CM = 1.25V6060dBdBCMRRIO (Note 8)Output Common Mode Rejection Ratio(Input Referred) ΔV OCM/ΔV OSDIFFV S = 5V, ΔV OCM = 1V66dBPSRR (Note 9)Differential Power Supply Rejection(ΔV S/ΔV OSDIFF)V S = 2.7V to 5.25V l6094dBPSRRCM (Note 9)Output Common Mode Power Supply Rejection(ΔV S/ΔV OSCM)V S = 2.7V to 5.25VL TC6404-1L TC6404-2L TC6404-4lll505040636351dBdBdBG CM Common Mode Gain (ΔV OUTCM/ΔV OCM)V S = 5V, ΔV OCM = 1VL TC6404-1L TC6404-2L TC6404-4lll110.99V/VV/VV/VCommon Mode Gain Error V S = 5V, ΔV OCM = 1VL TC6404-1L TC6404-2L TC6404-4lll–0.6–0.6–1.6–0.125–0.25–10.10.1–0.4%%%BAL Output Balance (ΔV OUTCM/ΔV OUTDIFF)ΔV OUTDIFF = 2V, Single-Ended InputL TC6404-1L TC6404-2L TC6404-4lll–60–60–53–40–40–40dBdBdBΔV OUTDIFF = 2V, Differential Input L TC6404-1L TC6404-2L TC6404-4lll–66–66–66–40–40–40dBdBdBV OSCM Common Mode Offset Voltage (V OUTCM – V OCM)V S = 2.7V to 5.25VL TC6404-1L TC6404-2L TC6404-4lll±10±20±40±25±50±100mVmVmVLTC6404 DC ELECTRICAL CHARACTERISTICS36404fSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITSΔV OSCM/ΔT Common Mode Offset Voltage Drift V S = 2.7V to 5.25VL TC6404-1L TC6404-2L TC6404-4±10±20±20μV/°CμV/°CμV/°CV OUTCMR (Note 7)Output Signal Common Mode Range(Voltage Range for the V OCM Pin)V S = 3VL TC6404-1L TC6404-2L TC6404-4lll1.11.11.1221.7VVVV S = 5VL TC6404-1L TC6404-2L TC6404-4lll1.11.11.1443.7VVVR INVOCM Input Resistance, V OCM Pin L TC6404-1L TC6404-2L TC6404-4lll158423.5147322010kΩkΩkΩV MID Voltage at the V OCM Pin V S = 3V l 1.45 1.5 1.55VV OUT Output Voltage High, Either Output Pin (Note 10)V S = 3V, I L = 0mAV S = 3V, I L = 5mAV S = 3V, I L = 20mA lll325360480550600750mVmVmVV S = 5V, I L = 0mA V S = 5V, I L = 5mA V S = 5V, I L = 20mA lll4605006507007501000mVmVmVOutput Voltage Low, Either Output Pin (Note 10)V S = 3V, I L = 0mAV S = 3V, I L = –5mAV S = 3V, I L = –20mA lll120140200230260350mVmVmVV S = 5V, I L = 0mA V S = 5V, I L = –5mA V S = 5V, I L = –20mA lll175200285320350550mVmVmVI SC Output Short-Circuit Current, Either Output Pin(Note 11)V S = 2.7VV S = 3VV S = 5Vlll±35±40±55±60±65±85mAmAmAA VOL Large-Signal Voltage Gain V S = 3V90dB V S Supply Voltage Range l 2.7 5.25VI S Supply Current (L TC6404-1)V S = 2.7V, V SHDN = V S – 0.6VV S = 3V, V SHDN = V S – 0.6VV S = 5V, V SHDN = V S – 0.6V lll27.227.327.835.535.536.5mAmAmASupply Current (L TC6404-2)V S = 2.7V, V SHDN = V S – 0.6VV S = 3V, V SHDN = V S – 0.6VV S = 5V, V SHDN = V S – 0.6V lll29.729.830.438.538.539.5mAmAmASupply Current (L TC6404-4)V S = 2.7V, V SHDN = V S – 0.6VV S = 3V, V SHDN = V S – 0.6VV S = 5V, V SHDN = V S – 0.6V lll30.030.231.0393940mAmAmAI SHDN Supply Current in Shutdown (L TC6404-1)V S = 2.7V, V SHDN = V S – 2.1VV S = 3V, V SHDN = V S – 2.1VV S = 5V, V SHDN = V S – 2.1V lll0.220.250.35112mAmAmASupply Current in Shutdown (L TC6404-2)V S = 2.7V, V SHDN = V S – 2.1VV S = 3V, V SHDN = V S – 2.1VV S = 5V, V SHDN = V S – 2.1V lll0.220.250.35112mAmAmASupply Current in Shutdown (L TC6404-4)V S = 2.7V, V SHDN = V S – 2.1VV S = 3V, V SHDN = V S – 2.1VV S = 5V, V SHDN = V S – 2.1V lll0.280.300.501.21.22.4mAmAmAThe l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V+ = 3V, V– = 0V, V CM = V OCM = V ICM = Mid-Supply,V SHDN = OPEN, R L = OPEN, R BAL = 100k (See Figure 1). For the L TC6404-1: R I = 100Ω, R F = 100Ω. For the L TC6404-2: R I = 100Ω,R F = 200Ω. For the L TC6404-4: R I = 100Ω, R F = 402Ω, unless otherwise noted. V S is deﬁ ned (V+ – V–). V OUTCM = (V OUT+ + V OUT–)/2. V ICM is deﬁ ned (V IN+ + V IN–)/2. V OUTDIFF is deﬁ ned (V OUT+ – V OUT–). V INDIFF = (V INP – V INM)LTC6404 DC ELECTRICAL CHARACTERISTICS46404f56404fThe l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V + = 3V , V – = 0V , V CM = V OCM = V ICM = Mid-Supply,V SHDN = OPEN, R I = 100Ω, R F = 100Ω, R L = 200Ω (See Figure 2) unless otherwise noted. V S is deﬁ ned (V + – V –). V OUTCM = (V OUT + + V OUT –)/2. V ICM is deﬁ ned as (V IN + + V IN –)/2. V OUTDIFF is deﬁ ned as (V OUT + – V OUT –). V INDIFF = (V INP – V INM ).LTC6404-1 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONSMINTYP MAXUNITS SR Slew RateV S = 3V to 5V450V/μs GBW Gain-Bandwidth Product V S = 3V to 5V , R I = 100Ω, R F = 499Ω, f TEST = 500MHz 500MHz f 3dB –3dB Frequency (See Figure 2)V S = 3V to 5Vl 300600MHzHD SEIN10MHz DistortionV S = 3V , V OUTDIFF = 2V P-P Single-Ended Input 2nd Harmonic 3rd Harmonic–88–91dBc dBcHD DIFFIN10MHz DistortionV S = 3V , V OUTDIFF = 2V P-P Differential Input 2nd Harmonic 3rd Harmonic–102–91dBc dBc IMD 10M Third-Order IMD at 10MHz f 1 = 9.5MHz, f 2 = 10.5MHz V S = 3V , V OUTDIFF = 2V P-P–93dBc OIP310M OIP3 at 10MHz (Note 12)50dBm t S Settling Time 2V Step at Output1% Settling 0.1% Settling 0.01% Settling 101317ns ns ns NF Noise Figure, R S = 50Ωf = 10MHz13.4dB f 3dBFIL TERDifferential Filter 3dB Bandwidth (Note 13)88.5MHzThe l denotes the speciﬁ cations which apply overthe full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V + = 3V , V –= 0V , V CM = V OCM = V ICM = Mid-Supply,V SHDN = OPEN, R L = OPEN, R BAL = 100k (See Figure 1). For the L TC6404-1: R I = 100Ω, R F = 100Ω. For the L TC6404-2: R I = 100Ω, R F = 200Ω. For the L TC6404-4: R I = 100Ω, R F = 402Ω, unless otherwise noted. V S is deﬁ ned (V + – V –). V OUTCM = (V OUT + + V OUT –)/2. V ICM is deﬁ ned (V IN + + V IN –)/2. V OUTDIFF is deﬁ ned (V OUT + – V OUT –). V INDIFF = (V INP – V INM )LTC6404 DC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETERCONDITIONS MINTYPMAX UNITSV IL SHDN Input Logic Low V S = 2.7V to 5V l V + – 2.1V V IH SHDN Input Logic High V S = 2.7V to 5Vl V + – 0.6V R SHDN SHDN Pin Input Impedance V S = 5V , V SHDN = 2.9V to 0V l386694kΩt ON Turn-On Time V S = 3V , V SHDN = 0.5V to 3V 750ns t OFFTurn-Off TimeV S = 3V , V SHDN = 3V to 0.5V300nsThe l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V+ = 3V, V– = 0V, V CM = V OCM = V ICM = Mid-Supply, V SHDN = OPEN, R I = 100Ω, R F = 200Ω, R L = 200Ω (See Figure 2) unless otherwise noted. V S is deﬁ ned (V+ – V–).V OUTCM = (V OUT+ + V OUT–)/2. V ICM is deﬁ ned as (V IN+ + V IN–)/2. V OUTDIFF is deﬁ ned as (V OUT+ – V OUT–). V INDIFF = (V INP – V INM). LTC6404-2 AC ELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SR Slew Rate V S = 3V to 5V700V/μs GBW Gain-Bandwidth Product V S = 3V to 5V, R I = 100Ω, R F = 499Ω,f TEST = 500MHz900MHz f3dB–3dB Frequency (See Figure 2)V S = 3V to 5V l300600MHz HD SEIN10MHz Distortion V S = 3V, V OUTDIFF = 2V P-PSingle-Ended Input2nd Harmonic 3rd Harmonic –95–96dBcdBcHD DIFFIN10MHz Distortion V S = 3V, V OUTDIFF = 2V P-PDifferential Input2nd Harmonic 3rd Harmonic –98–99dBcdBcIMD10M Third-Order IMD at 10MHzf1 = 9.5MHz, f2 = 10.5MHzV S = 3V, V OUTDIFF = 2V P-P–100dBc OIP310M OIP3 at 10MHz (Note 12)53dBmt S Settling Time2V Step at Output 1% Settling0.1% Settling0.01% Settling91215nsnsnsNF Noise Figure, R S = 50Ω f = 10MHz10dB f3dBFIL TER Differential Filter 3dB Bandwidth (Note 13)88.5MHzThe l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at T A = 25°C. V+ = 3V, V– = 0V, V CM = V OCM = V ICM = Mid-Supply, V SHDN = OPEN, R I = 100Ω, R F = 402Ω, R L = 200Ω (See Figure 2) unless otherwise noted. V S is deﬁ ned (V+ – V–).V OUTCM = (V OUT+ + V OUT–)/2. V ICM is deﬁ ned as (V IN+ + V IN–)/2. V OUTDIFF is deﬁ ned as (V OUT+ – V OUT–). V INDIFF = (V INP – V INM). LTC6404-4 AC ELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SR Slew Rate V S = 3V to 5V1200V/μs GBW Gain-Bandwidth Product V S = 3V to 5V, R I = 100Ω, R F = 499Ω,f TEST = 500MHz1700MHz f3dB–3dB Frequency (See Figure 2)V S = 3V to 5V l300530MHz HD SEIN10MHz Distortion V S = 3V, V OUTDIFF = 2V P-PSingle-Ended Input2nd Harmonic 3rd Harmonic –97–98dBcdBcHD DIFFIN10MHz Distortion V S = 3V, V OUTDIFF = 2V P-PDifferential Input2nd Harmonic 3rd Harmonic –100–101dBcdBcIMD10M Third-Order IMD at 10MHzf1 = 9.5MHz, f2 = 10.5MHzV S = 3V, V OUTDIFF = 2V P-P–101dBc OIP310M OIP3 at 10MHz (Note 12)54dBmt S Settling Time2V Step at Output 1% Settling0.1% Settling0.01% Settling81114nsnsnsNF Noise Figure, R S = 50Ω f = 10MHz8dB f3dBFIL TER Differential Filter 3dB Bandwidth (Note 13)88.5MHz66404fNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The inputs IN+, IN– are protected by a pair of back-to-back diodes. If the differential input voltage exceeds 1.4V, the input current should be limited to less than 10mA. Input pins (IN+, IN–, V OCM and SHDN) are also protected by steering diodes to either supply. If the inputs should exceed either supply voltage, the input current should be limited to less than10mA.Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shortedindeﬁ nitely. Long-term application of output currents in excess of the absolute maximum ratings may impair the life of the device.Note 4: The L TC6404C/L TC6404I are guaranteed functional over the operating temperature range –40°C to 85°C. The L TC6404H is guaranteed functional over the operating temperature range –40°C to 125°C.Note 5: The L TC6404C is guaranteed to meet speciﬁ ed performance from 0°C to 70°C. The L TC6404C is designed, characterized, and expectedto meet speciﬁ ed performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The L TC6404I is guaranteed to meet speciﬁ ed performance from –40°C to 85°C. The L TC6404H is guaranteed to meet speciﬁ ed performance from –40°C to 125°C.Note 6: Input bias current is deﬁ ned as the average of the input currents ﬂ owing into Pin 6 and Pin 15 (IN– and IN+). Input offset current is deﬁ ned as the difference of the input currents ﬂ owing into Pin 15 and Pin 6(I OS = I B+ – I B–)Note 7: Input common mode range is tested using the test circuit of Figure 1 by measuring the differential gain with a ±1V differential output with V ICM = mid-supply, and with V ICM at the input common mode range limits listed in the Electrical Characteristics table, verifying the differential gain has not deviated from the mid-supply common mode input caseby more than 1%, and the common mode offset (V OSCM) has not deviated from the zero bias common mode offset by more than ±15mV (L TC6404-1), ±20mV (L TC6404-2) or ±40mV (L TC6404-4).The voltage range for the output common mode range is tested using the test circuit of Figure 1 by applying a voltage on the V OCM pin and testing at both mid-supply and at the Electrical Characteristics table limits to verify that the the common mode offset (V OSCM) has not deviated by more than ±15mV (L TC6404-1), ±20mV (L TC6404-2) or ±40mV (L TC6404-4).Note 8: Input CMRR is deﬁ ned as the ratio of the change in the input common mode voltage at the pins IN+ or IN– to the change in differential input referred voltage offset. Output CMRR is deﬁ ned as the ratio of the change in the voltage at the V OCM pin to the change in differential input referred voltage offset. These speciﬁ cations are strongly dependent on feedback ratio matching between the two outputs and their respective inputs, and is difﬁ cult to measure actual ampliﬁ er performance. (See “The Effects of Resistor Pair Mismatch” in the Applications Information section of this data sheet. For a better indicator of actual ampliﬁ er performance independent of feedback component matching, refer to the PSRRspeciﬁ cation.Note 9: Differential power supply rejection (PSRR) is deﬁ ned as the ratio of the change in supply voltage to the change in differential input referred voltage offset. Common mode power supply rejection (PSRRCM) isdeﬁ ned as the ratio of the change in supply voltage to the change in the common mode offset, V OUTCM – V OCM.Note 10: This parameter is pulse tested. Output swings are measured as differences between the output and the respective power supply rail. Note 11: This parameter is pulse tested. Extended operation with the output shorted may cause junction temperatures to exceed the 125°C limit and is not recommended. See Note 3 for more details.Note 12: Since the L TC6404 is a voltage feedback ampliﬁ er with low output impedance, a resistive load is not required when driving an ADC. Therefore, typical output power is very small. In order to compare theL TC6404 with ampliﬁ ers that require 50Ω output loads, output swing of the L TC6404 driving an ADC is converted into an “effective” OIP3 as if the L TC6404 were driving a 50Ω load.Note 13: The capacitors used to set the ﬁ lter pole might have up to ±15% variation. The resistors used to set the ﬁ lter pole might have up to ±12% variation.ELECTRICAL CHARACTERISTICS76404fLTC6404-1 TYPICAL PERFORMANCE CHARACTERISTICSActive Supply Current vs Temperature Shutdown Supply Current vsTemperatureDifferential Voltage Offset (InputReferred) vs TemperatureCommon Mode Voltage Offset vs Temperature Active Supply Current vs SupplyVoltage and TemperatureSHDN Supply Current vs SupplyVoltage and TemperatureSHDN Pin Current vs SHDN Pin Voltage and Temperature Supply Current vs SHDN PinVoltage and TemperatureSmall-Signal FrequencyTEMPERATURE (°C)–7524ICC(mA)25272829–25255015064041 G0126–5007510012530TEMPERATURE (°C)–75ICC(mA)0.10.30.40.5–25255015064041 G020.2–50075100125TEMPERATURE (°C)–75–1.0VOSDIFF(mV)–0.8–0.4–0.21.00.4–25255015064041 G03–0.60.60.80.2–50075100125 TEMPERATURE (°C)–75–10VOSCM(mV)–8–4–2104–25255015064041 G04–6682–50075100125V SUPPLY (V)ICC(mA)510152024564041 G05253013V SUPPLY (V)ICC(mA)0.10.20.324564041 G060.40.513 SHDN PIN VOLTAGE (V)–30SHDNPINCURRENT(μA)–5–10–15–201.50.5 2.5 3.064041 G07–251.02.0SHDN PIN VOLTAGE (V)ICC(mA)1.50.5 2.5 3.064041 G081.02.051015202530FREQUENCY (MHz)10GAIN(dB)100100064041 G09–20–15–10–5586404f96404fSmall-Signal Frequency Response vs Gain Setting Resistor ValuesSmall-Signal FrequencySmall-Signal Frequency Response vs TemperatureSmall-Signal FrequencyLarge-Signal Step ResponseSmall-Signal Step ResponseDistortion vs FrequencyDistortion vs Input Common Mode VoltageFREQUENCY (MHz)10G A I N (d B )100100064041 G10–30–20–25–15–10–505FREQUENCY (MHz)10G A I N (d B )100100064041 G11–20–15–10–50105FREQUENCY (MHz)10G A I N (d B )100100064041 G12–20–15–10–5105FREQUENCY (MHz)10G A I N (d B )100100064041 G13–35–30–20–25–15–10–505TIME (ns)–1.5V O U T D I F F (O U T + – O U T –) (V )–1.0–0.506121564041 G140.51.01.539TIME (ns)–0.50V O U T D I F F (O U T + – O U T –) (V )–0.250.256121564041 G150.5039FREQUENCY (MHz)0.1–80H D 2, H D 3 (d B c )–60–40 1.01010064041 G16–100–90–70–50–110–120H D 2, H D 3 (d B c )64041 G17DC COMMON MODE INPUT (AT IN+ AND IN – PINS) (V)–110–40–50–60–70–80–90–1000 1.50.5 2.5 3.01.02.0Distortion vs Output AmplitudeH D 2, H D 3 (d B c )64041 G18V OUTDIFF (V P-P )–110–30–40–50–60–70–80–90–1000315624LTC6404-1 TYPICAL PERFORMANCE CHARACTERISTICS106404fDistortion vs Output AmplitudeL TC6404-1 Driving L TC2207 16-Bit ADCL TC6404-1 Driving L TC2207 16-Bit ADCVoltage Noise Density vs FrequencyH D 2, H D 3 (d B c )64041 G19V OUTDIFF (V P-P )–110–30–40–50–60–70–80–90–100031524(d B )64041 G20HD2HD3HD7HD9HD5HD4FREQUENCY (MHz)–1200–20–40–60–80–100V CM = V OCM = 1.7V V S = 3.3VR F = R I = 100ΩV IN = 2V P-P DIFFERENTIAL f SAMPLE = 105Msps 10MHz, 4092 POINT FFT FUNDAMENTAL = –1dBFS HD2 = –98.8dBc HD3 = –90.2dBc03010502040FREQUENCY (MHz)0.01V O L T A G E N O I S E D E N S I T Y (n V /√H z )110010000.11064041 G22110100(d B )64041 G21FREQUENCY (MHz)–1200–20–40–60–80–10003010502040L TC6404-1 Noise Figure vs FrequencyFREQUENCY (MHz)12842824201664041 G23N O I S E F I G U R E (d B )101000100LTC6404-1 TYPICAL PERFORMANCE CHARACTERISTICSLTC6404-2 TYPICAL PERFORMANCE CHARACTERISTICSActive Supply Current vs TemperatureShutdown Supply Current vs TemperatureDifferential Voltage Offset (Input Referred) vs TemperatureCommon Mode Voltage Offset (Input Referred) vs TemperatureActive Supply Current vs Supply Voltage and TemperatureSHDN Supply Current vs Supply Voltage and TemperatureSHDN Pin Current vs SHDN Pin Voltage and TemperatureSupply Current vs SHDN Pin Voltage and TemperatureSmall-Signal Frequency ResponseTEMPERATURE (°C)–7527I C C (m A )28303132–25255015064042 G0129–5007510012533TEMPERATURE (°C)–750I C C (m A )0.10.30.40.5–25255015064042 G020.2–50075100125TEMPERATURE (°C)–75–1.0V O S D I F F (m V )–0.8–0.4–0.201.00.4–25255015064042 G03–0.60.60.80.2–50075100125TEMPERATURE (°C)–75–10V O S C M (m V )–8–4–20104–25255015064042 G03–6682–50075100125V SUPPLY (V)0I C C (m A )1520253564042 G051050124303540V SUPPL Y (V)I C C (m A )0.10.20.324564042 G060.40.513SHDN PIN VOL TAGE (V)–30S H D N P I N C U R R E N T (μA )–5–10–15–20 1.50.52.53.064042 G07–250 1.0 2.0SHDN PIN VOL TAGE (V)I C C (m A )1.50.52.53.064042 G081.02.05101520253035FREQUENCY (MHz)10G A I N (d B )100100064042 G09–20–15–10–5051015Small-Signal Frequency Response vs Gain Setting Resistor ValuesSmall-Signal Frequency Response vs C LOADSmall-Signal Frequency Response vs TemperatureSmall-Signal Frequency Response vs TemperatureLarge-Signal Step ResponseSmall-Signal Step ResponseDistortion vs FrequencyDistortion vs Input Common Mode VoltageDistortion vs Output AmplitudeLTC6404-2 TYPICAL PERFORMANCE CHARACTERISTICSFREQUENCY (MHz)10G A I N (d B )100100064042 G10–25–10–20–5051015FREQUENCY (MHz)10G A I N (d B )100100064042 G11–15–10–5525101520FREQUENCY (MHz)10G A I N (d B )100100064042 G12–15–10–5051510FREQUENCY (MHz)10F I L T E R E D G A I N (d B )100100064042 G13–30–20–25–10–15–5051015TIME (ns)–1.5VO U T D I F F (O U T + – O U T –) (V )–1.0–0.506121564042 G140.51.01.539TIME (ns)0–1.00V O U T D IF F (O U T + – O U T –) (V )–0.75–0.50–0.2500.250.500.756121564042 G151.0039FREQUENCY (MHz)0.1–100H D 2, H D 3 (d B c )–90–80–70–6011010064042 G16–110–120–130–140–50–40H D 2, H D 3 (d B c )64042 G17DC COMMON MODE INPUT (AT IN + AND IN – PINS) (V)–110–40–50–60–70–80–90–1000 1.50.5 2.51.02.0H D 2, H D 3 (d B c )64042 G18V OUTDIFF (V P-P )–120–40–50–60–70–80–90–100–1100315624。