5. 外文翻译1
本科毕业论文外文翻译
本科毕业论文外文翻译Undergraduate Thesis External Translation (700 Words)Title: The Impact of Social Media on Consumer Behavior Abstract:With the rapid development of social media, its influence on consumer behavior has drawn increasing attention from scholars and marketers. This paper aims to explore the impact of social media on consumer behavior from the perspective of information acquisition, interpersonal communication, and brand evaluation. Through a literature review and analysis, it is found that social media has a significant impact on consumer behavior by providing easy access to information, facilitating communication between consumers, and influencing brand perception. This research provides valuable insights for marketers in understanding and utilizing social media platforms to effectively engage with consumers and influence their purchasing decisions.1. IntroductionSocial media has become an integral part of people's daily lives, and its impact on consumer behavior cannot be ignored. This paper aims to investigate the impact of social media on consumer behavior and provide practical implications for marketers. The research question is: How does social media influence consumer behavior in terms of information acquisition, interpersonal communication, and brand evaluation?2. Information Acquisition2.1 Social media provides a platform for consumers to easilyaccess information about products and services. Through social media platforms such as Facebook, Instagram, and Twitter, consumers can obtain product reviews, comparisons, and recommendations from peers. This information influences consumers' purchasing decisions and enhances their knowledge about products.2.2 Social media also serves as a source of entertainment and inspiration, enabling users to discover new trends and products. Influencers and celebrities, who gain popularity through social media, often endorse products and create consumer desire for these items. This form of indirect advertising through social media has a significant impact on consumer behavior.3. Interpersonal CommunicationSocial media platforms enable users to interact with friends, family, and even strangers. This communication aspect of social media hasa direct influence on consumer behavior.3.1 Word-of-mouth (WOM) communication through social media is prevalent. Consumers often share their positive or negative experiences with products on social media platforms, which influence others' opinions and purchasing decisions. These online conversations have a wide reach and can greatly impact brand perception.3.2 Social media facilitates communication between consumers and brands. Consumers can directly communicate with brands through social media channels, providing feedback, asking questions, and seeking assistance. This two-way communicationimproves customer satisfaction and loyalty.4. Brand Evaluation4.1 Social media plays a crucial role in brand evaluation. Consumers often seek information about brands, their values, and their reputation on social media platforms. Positive or negative brand mentions and reviews on social media greatly influence consumers' perceptions of brands, leading to either increased or decreased brand trust and loyalty.4.2 Social media influencers and celebrities endorsing particular brands also impact brand evaluation. These individuals' recommendations and opinions can greatly influence consumers' perceptions and preferences for specific brands.5. ConclusionIn conclusion, social media has a significant impact on consumer behavior by influencing information acquisition, interpersonal communication, and brand evaluation. Marketers should utilize and engage with social media platforms to effectively reach and influence their target customers. This research provides insights for marketers to enhance their social media strategies and create effective brand-consumer interactions.。
播音与主持外文翻译(1)
The three models we focus on in this issue—framing, agenda setting, and priming—have received significant scholarly attention since they were introduced. Agenda setting refers to the idea that there is a strong correlation between the emphasis that mass media place on certain issues (e.g., based on relative placement or amount of coverage) and the importance attributed to these issues by mass audiences (McCombs & Shaw, 1972). As defined in the political communication literature, Priming refers to‘changes in the standards that people use to make political evaluations’(Iyengar & Kinder, 1987, p. 63). Priming occurs when news content suggests to news audiences that they ought to use specific issues as benchmarks for evaluating the performance of leaders and governments. It is often understood as an extension of agenda setting.
毕业论文外文翻译格式【范本模板】
因为学校对毕业论文中的外文翻译并无规定，为统一起见,特做以下要求：1、每篇字数为1500字左右，共两篇；2、每篇由两部分组成:译文+原文.3 附件中是一篇范本，具体字号、字体已标注。
外文翻译（包含原文)(宋体四号加粗）外文翻译一（宋体四号加粗）作者：(宋体小四号加粗）Kim Mee Hyun Director, Policy Research & Development Team，Korean Film Council（小四号）出处：(宋体小四号加粗)Korean Cinema from Origins to Renaissance(P358～P340) 韩国电影的发展及前景（标题：宋体四号加粗）1996～现在数量上的增长(正文:宋体小四）在过去的十年间，韩国电影经历了难以置信的增长。
上个世纪60年代，韩国电影迅速崛起，然而很快便陷入停滞状态,直到90年代以后，韩国电影又重新进入繁盛时期。
在这个时期，韩国电影在数量上并没有大幅的增长，但多部电影的观影人数达到了上千万人次。
1996年，韩国本土电影的市场占有量只有23.1%。
但是到了1998年，市场占有量增长到35。
8%，到2001年更是达到了50%。
虽然从1996年开始，韩国电影一直处在不断上升的过程中，但是直到1999年姜帝圭导演的《生死谍变》的成功才诞生了韩国电影的又一个高峰。
虽然《生死谍变》创造了韩国电影史上的最高电影票房纪录，但是1999年以后最高票房纪录几乎每年都会被刷新。
当人们都在津津乐道所谓的“韩国大片”时，2000年朴赞郁导演的《共同警备区JSA》和2001年郭暻泽导演的《朋友》均成功刷新了韩国电影最高票房纪录.2003年康佑硕导演的《实尾岛》和2004年姜帝圭导演的又一部力作《太极旗飘扬》开创了观影人数上千万人次的时代。
姜帝圭和康佑硕导演在韩国电影票房史上扮演了十分重要的角色。
从1993年的《特警冤家》到2003年的《实尾岛》，康佑硕导演了多部成功的电影。
智能交通系统中英文对照外文翻译文献
智能交通系统中英文对照外文翻译文献(文档含英文原文和中文翻译)原文:Traffic Assignment Forecast Model Research in ITS IntroductionThe intelligent transportation system (ITS) develops rapidly along with the city sustainable development, the digital city construction and the development of transportation. One of the main functions of the ITS is to improve transportation environment and alleviate the transportation jam, the most effective method to gain the aim is to forecast the traffic volume of the local network and the important nodes exactly with GIS function of path analysis and correlation mathematic methods, and this will lead a better planning of the traffic network. Traffic assignment forecast is an important phase of traffic volume forecast. It will assign the forecasted traffic to every way in the traffic sector. If the traffic volume of certain road is too big, which would bring on traffic jam, planners must consider the adoption of new roads or improving existing roads to alleviate the traffic congestion situation. This study attempts to present an improved traffic assignment forecast model, MPCC, based on analyzing the advantages and disadvantages of classic traffic assignment forecast models, and test the validity of the improved model in practice.1 Analysis of classic models1.1 Shortcut traffic assignmentShortcut traffic assignment is a static traffic assignment method. In this method, the traffic load impact in the vehicles’ travel is not considered, and the traffic impedance (travel time) is a constant. The traffic volume of every origination-destination couple will be assigned to the shortcut between the origination and destination, while the traffic volume of other roads in this sector is null. This assignment method has the advantage of simple calculation; however, uneven distribution of the traffic volume is its obvious shortcoming. Using this assignment method, the assignment traffic volume will be concentrated on the shortcut, which isobviously not realistic. However, shortcut traffic assignment is the basis of all theother traffic assignment methods.1.2 Multi-ways probability assignmentIn reality, travelers always want to choose the shortcut to the destination, whichis called the shortcut factor; however, as the complexity of the traffic network, thepath chosen may not necessarily be the shortcut, which is called the random factor.Although every traveler hopes to follow the shortcut, there are some whose choice isnot the shortcut in fact. The shorter the path is, the greater the probability of beingchosen is; the longer the path is, the smaller the probability of being chosen is.Therefore, the multi-ways probability assignment model is guided by the LOGIT model:∑---=n j ii i F F p 1)exp()exp(θθ (1)Where i p is the probability of the path section i; i F is the travel time of thepath section i; θ is the transport decision parameter, which is calculated by the followprinciple: firstly, calculate the i p with different θ (from 0 to 1), then find the θwhich makes i p the most proximate to the actual i p .The shortcut factor and the random factor is considered in multi-ways probabilityassignment, therefore, the assignment result is more reasonable, but the relationshipbetween traffic impedance and traffic load and road capacity is not considered in thismethod, which leads to the assignment result is imprecise in more crowded trafficnetwork. We attempt to improve the accuracy through integrating the several elements above in one model-MPCC.2 Multi-ways probability and capacity constraint model2.1 Rational path aggregateIn order to make the improved model more reasonable in the application, theconcept of rational path aggregate has been proposed. The rational path aggregate,which is the foundation of MPCC model, constrains the calculation scope. Rationalpath aggregate refers to the aggregate of paths between starts and ends of the trafficsector, defined by inner nodes ascertained by the following rules: the distancebetween the next inner node and the start can not be shorter than the distance betweenthe current one and the start; at the same time, the distance between the next innernode and the end can not be longer than the distance between the current one and theend. The multi-ways probability assignment model will be only used in the rationalpath aggregate to assign the forecast traffic volume, and this will greatly enhance theapplicability of this model.2.2 Model assumption1) Traffic impedance is not a constant. It is decided by the vehicle characteristicand the current traffic situation.2) The traffic impedance which travelers estimate is random and imprecise.3) Every traveler chooses the path from respective rational path aggregate.Based on the assumptions above, we can use the MPCC model to assign thetraffic volume in the sector of origination-destination couples.2.3 Calculation of path traffic impedanceActually, travelers have different understanding to path traffic impedance, butgenerally, the travel cost, which is mainly made up of forecast travel time, travellength and forecast travel outlay, is considered the traffic impedance. Eq. (2) displaysthis relationship. a a a a F L T C γβα++= (2)Where a C is the traffic impedance of the path section a; a T is the forecast traveltime of the path section a; a L is the travel length of the path section a; a F is theforecast travel outlay of the path section a; α, β, γ are the weight value of that threeelements which impact the traffic impedance. For a certain path section, there aredifferent α, β and γ value for different vehicles. We can get the weighted average of α,β and γ of each path section from the statistic percent of each type of vehicle in thepath section.2.4 Chosen probability in MPCCActually, travelers always want to follow the best path (broad sense shortcut), butbecause of the impact of random factor, travelers just can choose the path which is ofthe smallest traffic impedance they estimate by themselves. It is the key point ofMPCC. According to the random utility theory of economics, if traffic impedance is considered as the negativeutility, the chosen probability rs p of origination-destinationpoints couple (r, s) should follow LOGIT model:∑---=n j jrs rs bC bC p 1)exp()exp( (3) where rs p is the chosen probability of the pathsection (r, s);rs C is the traffic impedance of the path sect-ion (r, s); j C is the trafficimpedance of each path section in the forecast traffic sector; b reflects the travelers’cognition to the traffic impedance of paths in the traffic sector, which has reverseratio to its deviation. If b → ∞ , the deviation of understanding extent of trafficimpedance approaches to 0. In this case, all the travelers will follow the path whichis of the smallest traffic impedance, which equals to the assignment results withShortcut Traffic Assignment. Contrarily, if b → 0, travelers ’ understanding error approaches infinity. In this case, the paths travelers choose are scattered. There is anobjection that b is of dimension in Eq.(3). Because the deviation of b should beknown before, it is difficult to determine the value of b. Therefore, Eq.(3) is improvedas follows:∑---=n j OD j OD rsrs C bC C bC p 1)exp()exp(，∑-=n j j OD C n C 11（4） Where OD C is the average of the traffic impedance of all the as-signed paths; bwhich is of no dimension, just has relationship to the rational path aggregate, ratherthan the traffic impedance. According to actual observation, the range of b which is anexperience value is generally between 3.00 to 4.00. For the more crowded cityinternal roads, b is normally between 3.00 and 3.50.2.5 Flow of MPCCMPCC model combines the idea of multi-ways probability assignment anditerative capacity constraint traffic assignment.Firstly, we can get the geometric information of the road network and OD trafficvolume from related data. Then we determine the rational path aggregate with themethod which is explained in Section 2.1.Secondly, we can calculate the traffic impedance of each path section with Eq.(2),Fig.1 Flowchart of MPCC which is expatiated in Section 2.3.Thirdly, on the foundation of the traffic impedance of each path section, we cancalculate the respective forecast traffic volume of every path section with improvedLOGIT model (Eq.(4)) in Section 2.4, which is the key point of MPCC.Fourthly, through the calculation processabove, we can get the chosen probability andforecast traffic volume of each path section, but itis not the end. We must recalculate the trafficimpedance again in the new traffic volumesituation. As is shown in Fig.1, because of theconsideration of the relationship between trafficimpedance and traffic load, the traffic impedanceand forecast assignment traffic volume of everypath will be continually amended. Using therelationship model between average speed andtraffic volume, we can calculate the travel timeand the traffic impedance of certain path sect-ionunder different traffic volume situation. For theroads with different technical levels, therelationship models between average speeds totraffic volume are as follows: 1) Highway: 1082.049.179AN V = (5) 2) Level 1 Roads: 11433.084.155AN V = (6) 3) Level 2 Roads: 66.091.057.112AN V = (7) 4) Level 3 Roads: 3.132.01.99AN V = (8) 5) Level 4 Roads: 0988.05.70A N V =(9) Where V is the average speed of the path section; A N is the traffic volume of thepath section.At the end, we can repeat assigning traffic volume of path sections with themethod in previous step, which is the idea of iterative capacity constraint assignment,until the traffic volume of every path section is stable.译文智能交通交通量分配预测模型介绍随着城市的可持续化发展、数字化城市的建设以及交通运输业的发展，智能交通系统（ITS）的发展越来越快。
5电气自动化 单片机 外文文献 英文文献 外文翻译 中英对照大学毕设论文
Single-chip1.The definition of a single-chipSingle-chip is an integrated on a single chip a complete computer system .Even though most of his features in a small chip，but it has a need to complete the majority of computer components：CPU，memory，internal and external bus system，most will have the Core.At the same time，such as integrated communication interfaces，timers，real-time clock and other peripheral equipment.And now the most powerful single-chip microcomputer system can even voice ，image，networking，input and output complex system integration on a single chip.Also known as single-chip MCU（Microcontroller），because it was first used in the field of industrial control.Only by the single-chip CPU chip developed from the dedicated processor. The design concept is the first by a large numberof peripherals and CPU in a single chip，the computer system so that smaller，more easily integrated into the complex and demanding on the volume control devices.INTEL the Z80 is one of the first design in accordance with the idea of the processor，From then on，the MCU and the development of a dedicated processor parted ways.Early single-chip 8-bit or all the four.One of the most successful is INTELs 8031，because the performance of a simple and reliable access to a lot of good praise.Since then in 8031to develop a single-chip microcomputer system MCS51 series.based on single-chip microcomputer system of the system is still widely used until now.As the field of industrial control requirements increase in the beginning of a 16-bit single-chip，but not ideal because the price has not been very widely used.After the90s with the big consumer electronics product development，single-chip technology is a huge improvement.INTEL i960 series with subsequent ARM in particular ，a broad range of application，quickly replaced by 32-bit single-chip 16-bit single-chip performance has been the rapid increase in processing power compared to the 80s to raise a few hundred times.At present，the high-end 32-bit single-chip frequency over 300MHz，the performance of the mid-90s close on the heels of a special processor，while the ordinary price of the model dropped to one U.S dollars，the most high-end models，only 10 U.S dollars.Contemporary single-chip microcomputer system is no longer only the bare-metal environment in the development and use of a large number of dedicated embedded operating system is widely used in the full range of single-chip microcomputer.In PDAs and cellphones as the coreprocessing of high-end single-chip or even a dedicated direct access to Windows and Linux operating systems.More than a dedicated single-chip processor suitable for embedded systems，so it was up to the application.In fact the number of single-chip is the worlds largest computer.Modern human life used in almost every piece of electronic and mechanical products will have a single-chip integration.Phone，telephone，calculator，home applicances，electronic toys，handheld computers and computer accessories such as a mouse in the Department are equipped with 1-2 single chip.And personal computers also have a large number of single-chip microcomputer in the workplace.Vehicles equipped with more than 40 Department of the general single-chip ，complex industrial control systems and even single-chip may have hundreds of work at the same time!SCM is not only far exceeds the number of PC and other integrated computing,even more than the number of human beings.2.single-chip introducedSingle-chip,also known as single-chip microcontroller,it is not the completion of a logic function of the chip,but a computer system integrated into a chip.Speaking in general terms: a single chip has become a computer .Its small size,light weight,cheap,for the learning,application and development of facilities provided .At the same time,learning to use the principle of single-chip computer to understand and structure the best choice.Single-chip and computer use is also similar to the module,such as CPU,memory,parallel bus, as well as the role and the same hard memory,is it different from the performance of these components are relatively weak in our home computer a lot,but the price is low ,there is generally no more than 10yuan,,can use it to make some control for a class of electrical work is not very complex is sufficient.We are using automatic drum washing machines, smoke hood,VCD and so on inside the home appliances can see its shadow! It is mainly as part of the core components of the control.It is an online real-time control computer,control-line is at the scene,we need to have a stronger anti-interference ability,low cost,and this is off-line computer(such as home PC)The main difference.By single-chip process,and can be amended.Through different procedures to achieve different functions,in particular the special unique features,this is the need to charge other devices can do a great effort,some of it is also difficult to make great efforts to do so .A function is not very complicated fi the United States the development of the 50s series of 74 or 60 during the CD4000series to get these pure hardware,the circuit must be a big PCB board !However,if the United States if the successful 70s seriesof single-chip market ,the result will be different!Simply because the adoption of single-chip preparation process you can achieve high intelligence,high efficiency and high reliability!Because of cost of single-chip is sensitive,so the dominant software or the lowest level assembly language,which is in addition to the lowest level for more than binary machine code of the language ,since such a low-level so why should we use ?Many of the seniors language has reached a level of visual programming why is it not in use ?The reason is simple ,that is,single-chip computer as there is no home of CPU,also not as hard as the mass storage device.A visualization of small high-level language program,even if there is only one button which will reach the size of dozens of K! For the home PCs hard drive is nothing,but in terms of the single-chip microcomputer is unacceptable.Single-chip in the utilization of hardware resources have to do very high ,so the compilation of the original while still in heavy use .The same token ,if the computer giants operating system and appplications run up to get the home PC,homePCcan not afford to sustain the same.It can be said that the twentieth century across the three “power”of the times,that is ,the electrical era,the electronic age and has now entered the computer age. However ,such a computer,usually refers to a personal computer,or PC.It consisits of the host ,keyboards,displays .And other components.There is also a type of computer,not how most people are familiar with . This computer is smart to give a variety of mechanical single-chip(also known as micro-controller).As the name suggests,these computer systems use only the minimum of an integrated circuit to make a simple calculation and control. Because of its small size,are usually charged with possession of machine in the “belly”in. It in the device,like the human mind plays a role, it is wrong,the entire device was paralyzed .Now,this single chip has a very wide field of use,such as smart meters,real-time industrial control,communications equipment,navigation systems,and household appliances. Once a variety of products with the use of the single-chip ,will be able to play so that the effectiveness of product upgrading,product names often adjective before the word “intelligent”,such as was hing machines and so intelligent.At present,some technical personnel of factories or other amateur electrtonics developers from engaging in certain products ,not the circuit is too complex ,that is functional and easy to be too simple imitation.The reason may be the product not on the cards or the use of single-chip programmable logic device on the other.3.single-chip historysingle-chip 70 was born in the late 20th century,experienced a SCM,MCU,SOC three stages.Single-chip micro-computer 1.SCM that(Single Chip Microcomputer)stage,is mainly a single from to find the best of the best embedded systems architecture.”Innovation model”to be successful,lay the SCM with the general-purpose computers,a completely different path of development . In embedded systems to create an independent development path,Intel Corporation credit.That is 2.MCU microcontroller(Micro Controller Unit)stage,the main direction of technology development: expanding to meet the embedded applications,the target system requirements for the various peripheral circuits and interface circuits,to highlingt the target of intelligent control.It covers all areas related with the objectSystem,therefore,the development of MCU inevitably fall on the heavy electrical,electronics manufacturers. From this point of view ,Intels development gradually MCU has its objective factors.MCU in the development ,the most famous manufacturers when the number of Philips Corporation.Philips in embedded applications for its enormous advantages,the MCS-51 from the rapid deveploment of single-chip micro-computer to the microcontroller.Therefore,when we look back at the path of development of embedded systems,Intel and Philips do not forget the historical merits.3.Single-chip is an independent embedded systems development,to the MCU an important factor in the development stage,is seeking applications to maximize the natural trend .With the mico-electronics technology,IC design,EDA tools development,based on the single-chip SOC design application systems will have greater development. Therefore,the understanding of single-chip micro-computer from a single ,monolithic single-chip microcontroller extends to applications.4.Single-chip applicationsAt present,single-chip microcomputer to infiltrate all areas of our lives,which is very difficult to find the area of almost no traces of single-chip microcomputer.Missile navigation equipment,aircraft control on a variety of instruments,compuer network communications and data transmission,industrial automation,real-time process control and data processing ,are widely used in a variety of smart IC card,limousine civilian security systems,video recorders,cameras,the control of automatic washing machines,as well as program-controllde toys,electronic pet,etc,which are inseparable from the single-chip microcomputer.Not to mention the field of robot automation ,intelligent instrumentation,medical equipment has been. Therefore,the single- chip learning ,development and application to a large number of computer applications and intelligent control of scientists,engineers.Single-chip widely used in instruments and meters,household appliances，medical equipment ,acrospace,specialized equipment and the intellingent management in areas such as process control,generally can be divided into the following areas:1.In the smart application of instrumentationSingle-chip with small size,low power consumption,control,and expansion flexibility , miniaturization and ease of sensors,can be realized,suchvoltage,power,frequency,humidity,temperature,flow,speed,thickness,angle,length,hardness,elemen t,measurement of physical pressure. SCM makes use of digital instrumentation,intelligence,miniaturization and functional than the use of electronic or digital circuitry even stronger.For example,precision measurement equipment(power meter,oscilloscope,and analyzer).2.In the industrial controlMCU can constitute a variety of control systems,data acquisition system.Such as factory assembly line of intelligent management ,intelligent control of the lift ,all kinds of alarm systems ,and computer networks constitute a secondary control system.3.In the applicationof household appliancesIt can be said that almost all home appliances are using the single-chip control,electric rice from favorable,washing machines,refrigerators,air conditioners,color TV and other audio video equipment,and then to the electronic weighing equipment,all kinds ,everywhere.4.On computer networks and communication applications in the field ofGenerally with the modern single-chip communication interface,can be easily carried out with computer carried out with computer data communications,computer networks and in inter-application communications equipment to provide an excellent material conditions,the communications equipment to provide an excellent material condition,from the mobile phone ,telephone , mini-program-controlled switchboards,buiding automated communications system call,the train wireless communications,and then you can see day-to-day work of mobile phones,Mobile communications,such as radios.5.Single-chip in the field of medical equipment applicationsSingle-chip microcomputer in medical devices have a wide range of purpose,such as medical ventilator,various analyzers,monitors,ultrasonic diagnostic equipment and hospital call systems.6.In a variety of large-scale electrical applications of modularSome special single-chip design to achieve a specific function to carry out a variety of modular circuitapplications,without requiring users to understand its internal structure.Integrated single-chip microcomputer such as music ,which seems to be simpleFunctions,a miniature electronic chip in a pure(as distinct from the principle of tape machine),would require a complex similar to the principle of the computer. Such as :music signal to digital form stored in memory(similar to ROM),read out by the microcontroller into analog music signal(similar to the sound card).In large circuits,modular applications that greatly reduces the size ,simplifying the circuit and reduce the damage,error rate ,but also to facilitate the replacement.In addition,single-chip microcomputer in the industrial,commercial,financial,scientific research ,education,defense aerospace and other fields have a wide range of uses.单片机1.单片机定义单片机是一种集成在电路芯片上的完整计算机系统。
外文翻译(1)(1)
注：红色字体表示语句不明白的地方，请求学姐帮忙。
聚亚烷基二醇的化学结构和它们在含水环境中的好氧生物降解性之间的关系简要：使用一组聚合流体，其中包括聚乙二醇、聚丙二烯（PPG）、不同EO/PO 比率的环氧乙烷（EO）的无规共聚物和环氧丙烷（PO），对聚亚烷基醇（PAG）的化学结构和它们的生物降解性之间的关系进行研究以及用PAG的醚和酰基部分封端。
被测试的PAG中有一个均分子量范围在350-3600Da，它们的差异是由其聚合物主链的直链（二醇型）或支链（三元醇型）分子。
PAG的最终生物降解能力是根据ISO14593（CO2顶空试验）用非预曝光（如在OECD310试验）和预曝光（改编）接种物来确定。
带有PPG结构和二元醇或三元醇的EO/PO共聚物，均分子量不超过1000沓的PAG，被认为是易于生物降解的。
他们的最终生物降解可超过60％的限制（根据OECD310测试标准）。
具有共聚结构并且MW值在1000-3600之间的PAG不易生物降解，但它们可以被看做是那些固有的最终降解物。
在PAG结构中EO含量的增长和末端羟基的酰化与羧酸基团有利地影响了他们的生物降解性。
含末端醚基团封端的PAG似乎是耐生物降解的。
关键词生物降解、聚亚烷基二醇、PAG、PPG、封顶PAG、ISO14593。
引言：术语中的聚亚烷基二醇-PAG，以及在相关文献中的PAG，例如，聚乙二醇，聚醚和聚（烯化氧）中使用的PAG术语都是带有环氧化物结构烯化氧聚合得到的化合物。
PAG主要是通过使用乙烯和丙烯的氧化物合成的，不常使用丁二醇和更高的烯烃氧化物。
PAG类化合物（不同的分子量，性能和应用）最常用的包括氧化乙烯或丙烯均聚物氧化物以及乙烯和丙烯氧化物的无规或嵌段共聚物。
PAG的分子结构不仅取决于种类和亚烷基氧化物的比例，而且还取决于用于聚合反应的引发剂分子的类型（单-，二-或多官能分子具有2个以上活泼氢原子）。
引发剂影响PAG分子的末端羟基基团和聚合物链的类型，其可以是线性的（单醇及二醇型）或支链的（多元醇的数类型）。
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编号：毕业设计(论文)外文翻译（原文）学院：计算机科学与工程学院专业：计算机科学与技术专业学生姓名：覃龙学号：0700720222指导教师单位：计算机科学与工程学院姓名：黄廷磊职称：教授2011年5月30 日Block RAM SummaryThe block RAM in Virtex-5 FPGAs stores up to 36K bits of data and can be configured aseither two independent 18 Kb RAMs, or one 36 Kb RAM. Each 36 Kb block RAM can beconfigured as a 64K x 1 (when cascaded with an adjacent 36 Kb block RAM), 32K x 1,16K x 2, 8K x 4, 4K x 9, 2K x 18, or 1K x 36 memory. Each 18 Kb block RAM can beconfigured as a 16K x 1, 8K x2 , 4K x 4, 2K x 9, or 1K x 18 memory.Similar to the Virtex-4 FPGA block RAMs, Write and Read are synchronous operations; thetwo ports are symmetrical and totally independent, sharing only the stored data. Each portcan beconfigured in one of the available widths, independent of the other port. Inaddition, the read port width can be different from the write port width for eac h port. Thememory content can be initialized or cleared by the configuration bitstream. During awrite operation the memory can be set to have the data output either remain unchanged,reflect the new data being written or the previous data now being overwritten.Virtex-5 FPGA block RAM enhancements include:I ncreased memory storage capability per block. Each block RAM can store up to 36Kbits of data.S upport of two independent 18K blocks, or a single 36K block RAM.E ach 36K block RAM can be set to simple dual-port mode, doubling data width of theblock RAM to 72 bits. The 18K block RAM can also be set to simple dual-port mode,doubling data width to 36 bits.Simple dual-port mode is defined as having one readonlyport and one write-only port with independent clocks.T wo adjacent block RAMs can be combined to one deeper 64K x 1 memory withoutany external logic.O ne 64-bit Error Correction Coding block is provided per 36 Kb block RAM or 36 KbFIFO. Separate encode/decode functionality is available.S ynchronous Set/Reset of the outputs to an initial value is available for both the latchand register modes of the block RAM output.A n attribute to configure the block RAM as a synchronous FIFO to eliminate flaglatency uncertainty.T he Virtex-5 FIFO does not have FULL flag assertion latency.Virtex-5 FPGA block RAM features:18, 36, or 72-bit wide ports can have an individual write enable per byte. This featureis popular for interfacing to an on-chip microprocessor.E ach block RAM contains optional address sequencing and control circuitry to operate as a built-in multirate FIFO memory. In Virtex-5 architecture, the block RAM can be configured as an18Kb or 36Kb FIFO.A ll inputs are registered with the port clock and have a setup-to-clock timing specification.A ll outputs have a read function or a read-during-write function, depending on the state of the write enable (WE) pin. The outputs are available after the clock-to-out timing interval. The read-during-write outputs have one of three operating modes:WRITE_FIRST, READ_FIRST, and NO_CHANGE.A write o peration requires one clock edge.A read operation requires one clock edge.A ll output ports are latched. The state of the output port does not change until the port executes another read or write operation. The default block RAM output is latch mode.T he output data path has an optional internal pipeline register. Using the regist ermode is strongly recommended. This allows a higher clock rate, however, it adds a clock cycle latency of one. Virtex-5 FPGA block RAM usage rules:T he Synchronous Set/R eset (SSR) port cannot be used when the ECC decoder is enabled (EN_ECC_READ = TRUE).T he setup time of the block RAM address and write enable pins must not be violated. Violating the address setup time (even if write enable is Low) will corrupt the datacontents of the block RAM.T he block RAM register mode SSR requires REGCE = 1 to reset the output DO register value. The block RAM array data output latch does not get reset in this mode. The block RAM latch mode SSR requires the block RAM enable, EN = 1, to reset the output DO latch value.A lthough RAMB18SDP (x36 18k block RAM) and RAMB36SDP (x72 36k block RAM)are simple dual-port primitives, the true dual-port primitives (RAMB18 and RAMB36) can be used with one read-only port and one write-only port. For example: a RAMB18s READ_WIDTH_A = 18, WRITE_WIDTH_B = 9, with WEA = 0 and WEB = 1 is effectively a simple dual-port block RAM with a smaller port width having been derived from the true dual-port primitive. Similarly, a ROM function can be built out of either the true dual-port (RAMB18 or RAMB36) or the simple dual-portblock RAM primitives (RAMB18SDP or RAMB36SDP).D ifferent read and write port width choices are available when using specific block RAM primitives. The parity bits are only available for the x9, x18, and x36 port widths. The parity bits should not be used when the read width is x1, x2, or x4. If the read width is x1, x2 or x4, the effective write width is x1, x2, x4, x8, x16, or x32. Similarly, when a write width is x1, x2, or x4, the actual available read width is x1, x2, x4, x8, x16, or x32 even though the primitive attribute isset to 1, 2, 4, 9, 18, or 36respectively. Table 4-1 shows some possible scenarios.Table 4-1: Parity Use SceneriesNotes:1. Do not use parity bits DIP/DOP when one port widths is less than nine and another port width is nineBlock RAM IntroductionIn addition to distributed RAM memory and high-speed SelectIO™ memory interfaces, Virtex-5devices feature a large number of 36 Kb block RAMs. Each 36 Kb block RAM contains two independently controlled 18 Kb RAMs. Block RAMs are placed in columns, and the total number of block RAM memory depends on the size of the Virtex-5 device. The 36 Kb blocks are cascadable to enable a deeper and wider memory implementation, with a minimal timing penalty. Embedded dual- or single-port RAM modules, ROM modules, synchronous FIFOs, and data width converters are easily implemented using the Xilinx CORE Generator™ block memory modules. Multirate FIFOs can be generated using the CORE Generator FIFO Generator module. The synchronous or asynchronous (multirate) FIFO implementation does not require additional CLB resources for the FIFO control logicsince it uses dedicated hardware resources.Synchronous Dual-Port and Single-Port RAMsData FlowThe true dual-port 36 Kb block RAM dual-port memories consist of a 36 Kb storage area and two completely independent access ports, A and B. Similarly, each 18 Kb b lock RAM dual-port memory consists of an 18 Kb storage area and two completely independent access ports, A and B. The structure is fully symmetrical, and both ports are interchangeable. Figure 4-1 illustrates the true dual-port data flow. Table 4-2 lists the port names and descriptions. Data can be written to either or both ports and can be read from either or both ports. Each write operation is synchronous, each port has its own address, data in, data out, clock, clock enable, and write enable. The read and write operations are synchronousand require a clock edge. There is no dedicated monitor to arbitrate the effect of identical addresses onboth ports. It is up to the user to time the two clocks appropriately. Conflicting simultaneous writes to the same location never cause any physical damage but can result in data uncertainty.Read OperationIn latch mode, the read operation uses one clock edge. The read address is registered on the read port, and the stored data is loaded into the output latches after the RAM access time. When using the outputregister, the read operation will take one extra latency cycle.Write OperationA write operation is a single clock-edge operation. The write address is registered on the write port, andthe data input is stored in memory.Write ModesThree settings of the write mode determines the behavior of the data available on the output latches after a write clock edge: W RITE_FIRST, REA D_FIRST, and NO_CHANGE. Write mode selection is set by configuration. The Write mode attribute can be individually selected for each port. The default mode is WRITE_FIRST. W RITE_FIRST outputs thenewly written data onto the output bus. REA D_FIRST outputs the previously stored data while new data is being written. NO_CHANGE maintains the output previously generated by a read operation. For the simple dual port block RAM, the Write mode is always READ_FIRST in ECC configuration,and therefore no collision can occur when used in synchronous mode.WRITE_FIRST or Transparent Mode (Default)In WRITE_FIRST mode, the input data is simultaneously written into memory an d stored in the data output (transparent write), as shown in Figure 4-2. These waveforms correspond to latch modewhetREAD_FIRST or Read-Before-Write ModeIn REA D_FIRST mode, data previously stored at the write address appears on the output latches, while the input data is being stored in memory (read before write). The waveforms in Figure 4-3 correspond to latch mode when the optional output pipeline register is not usdedNO_CHANGE ModeIn NO_CHANGE mode, the output latches remain unchanged during a write operation. As shown in Figure 4-4, data output remains the last read data and is unaffected by a write operation on the same port. These waveforms correspond to latch mode when the optional output pipeline register is not used.Conflict AvoidanceVirtex-5 FPGA block RAM memory is a true dual-port RAM where both ports can access any memory location at any time. When accessing the same memory location from both ports, the user must, however, observe certain restrictions. There are two fundamentally different situations: The two ports either have a common clock (synchronous clocking), or the clock frequency and phase is different for the two ports (asynchronous clocking).Asynchronous ClockingAsynchronous clocking is the more general case, where the active edges of both clocks do not occur simultaneously:T here are no timing constraints when both ports perform a read operation.W hen one port performs a write operation, the other port must not read- or writeaccess the same memory location. The simulation model will produce an error if this condition is violated. If this restriction is ignored, a read or write operation willproduce unpredictable results. There is, however, no risk of physical damage to the device. If a read and write operation is performed, then the write will store valid data at the write location. Synchronous ClockingSynchronous clocking is the special case, where the active edges of both port clocks occur simultaneously:T here are no timing constraints when both ports perform a read operation.W hen one port performs a write operation, the other port must not write into the same location, unless both ports write identical data.W hen one port performs a write operation, the write operation succeeds; the other port can reliably read data from the same location if the write port is in READ_FIRST mode. DATA_OUT on bothports will then reflect the previously stored data. If the write port is in either WRITE_FIRST or inNO_CHA NGE mode, then the DATAOUT on the read port would become invalid (unreliable). Themode setting of the read-port does not affect this operation.Additional Block RAM Features in Virtex-5 Devices Optional Output RegistersThe optional output registers improve design performance by eliminating routing delay to the CLB flip-flops for pipelined operation. An independent clock and clock enable input is provided for these output registers. As a result the output data registers hold the value independent of the input register operation. Figure 4-5 shows the optional output register.Independent Read and Write Port Width SelectionEach block RAM port has control over data width and address depth (aspect ratio). The true dual-portblock RAM in Virtex-5 FPGAs extends this flexibility to Read and Write where each individual portcan be configured with different data bit widths. For example, port A can have a 36-bit Read width anda 9-bit Write width, and port B can have a 18-bit Read width and a 36-bit Write width. See “BlockRAM Attributes,” page 126. If the Read port width differs from the Write port width, and is configuredin WRITE_FIRST mode, then DO shows valid new data for all the enabled write bytes. The DO portoutputs the original data stored in memory for all not enabled bytes. Independent Read and Write portwidth selection increases the efficiency of implementing a content addressable memory (CAM) inblock RAM. Th is option is available for all Virtex-5 FPGA true dual-port RAM port sizes and modes. Simple Dual-Port Block RAMEach 18 Kb block and 36 Kb block can also be configured in a simple dual-port RAM mode. In this mode, the block RAM port width doubles to 36 bits for the 18 Kb block RAM and 72 bits for the 36 Kb block RAM. In simple dual-port mode, independent Read and Write operations can occur simultaneously, where port A is designated as the Read port and port B as the Write port. When the Read and Write port access the same data location at the same time, it is treated as a collision, similar to the port collision in true dual-port mode. Readback through the configuration port is not supported in simple dual-port block RAM mode. Figure 4-6 shows the simple dual-port data flowCascadable Block RAMIn the Virtex-5 block RAM architecture, two 32K x 1 RAMs can be combined to form one 64K x 1 RAM without using local interconnect or additional CLB logic resources. Any two adjacent block RAMs can be cascaded to generate a 64K x 1 block RAM. Increasing the depth of the block RAM by cascading two block RAMs is available only in the 64K x 1 mode. Further information on cascadable block RAM is described in the “Additional RAMB18 and RAMB36 Primitive Design Considerations” section. For other wider and/or deeper sizes, consult the Creating Larger RAM Structures section. Figure 4-7 shows the block RAM with the appropriate ports connected in the Cascadable mode.Byte-wide Write EnableThe byte-wide write enable feature of the block RAM gives the capability to write eight bit (one byte) portions of incoming data. There are four independent byte-wide write enable inputs to the RAMB36 true dual-port RAM. There are eight independent byte-wide write enable inputs to block RAM in simple dual-port mode (RAMB36SDP). Table 4-4 summarizes the byte-wide write enables for the 36K and 18K block RAM. Each byte-wide write enable is associated with one byte of input data and one parity bit. A ll byte-wide write enable inputs must be driven in all data width configurations. This feature is useful when using block RAM to interface with a microprocessor. Byte-wide write enable is not available in the multirate FIFO or ECC mode. Byte-wide write enable is further described in the “Additional RAMB18 and RAMB36 Primitive Design Considerations” section.Figure 4-8 shows the byte-wide write-enable timing diagram for the RAMB36.When the RAMB36 is configured for a 36-bit or 18-bit wide data path, any port can restrict writing to specified byte locations within the data word. If configured in READ_FIRST mode, the DO bus shows the previous content of the whole addressed word. In WRITE_FIRST mode, DO shows a combination of the newly written enabled byte(s), and the initial memory contents of the unwritten bytes.Block RAM Error Correction CodeBoth block RAM and FIFO implementations of the 36 Kb block RAM support a 64-bit Error Correction Code (ECC) implementation. The code is used to detect single and double-bit errors inblock RAM data read out. Single-bit errors are then corrected in the output data.Block RAM Library PrimitivesThe Virtex-5 FPGA block RAM library primitives, RAMB18 and RAMB36, are the basic building blocks for all block RAM configurations. Other block RAM primitives and macros are based on these primitives. Some block RAM attributes can only be configured usingone of these primitives (e.g., pipeline register, cascade, etc.). See the “Block RAM Attributes” section. The input and output data buses are represented by two buses for 9-bit width (8 + 1), 18-bit width (16 + 2), and 36-bit width (32 + 4) configurations. The ninth bit associated with each byte can store parity/error correction bits or serve as additional data bits. No specific function is performed on the ninth bit. The separate bus for parity bits facilitates some designs. However, other designs safely use a 9-bit, 18-bit, or 36-bit bus by merging the regular data bus with the parity bus. Read/write and storage operations are identical for all bits, including the parity bits.Block RAM Port SignalsEach block RAM port operates independently of the other while accessing the same set of 36K-bit memory cells.Clock - CLK[A|B]Each port is fully synchronous with independent clock pins. All port input pins have setup time referenced to the port CLK pin. The output data bus has a clock-to-out time referenced to the CLK pin. Clock polarity is configurable (rising edge by default).Enable - EN[A|B]The enable pin affects the read, write, and set/reset functionality of the port. Ports with an inactive enable pin keep the output pins in the previous state and do not write data to the memory cells. Enable polarity is configurable (active High by default).Byte-wide Write Enable - WE[A|B]To write the content of the data input bus into the addressed memory location, both EN and WE must be active within a set-up time before the active clock edge. The output latches are loaded or not loaded according to the write configuration (W RITE_FIRST, READ_FIRST, NO_CHA NGE). When inactive, a read operation occurs, and the contents of the memory cells referenced by the address bus appear on the data-out bus, regardless of the write mode attribute. Write enable polarity is not configurable (active High).Register Enable - REGCE[A|B]The register enable pin (REGCE) controls the optional output register. When the RAM is in register mode, REGCE = 1 registers the output into a register at a clock edge. The polarity of REGCE is not configurable (active High).Set/Reset - SSR[A|B]In latch mode, the SSR pin forces the data output latches, to contain the value SRVA L. See“Block RAM Attributes,” pag e 126. When the optional output registers are enabled, the data output registers can also be forced by the SSR pin to contain the value SRVA L. SSR does not affect the latched value. The data output latches or output registers are synchronously asserted to 0 or 1, including the parity bit. Each port has an independent SRVA L[A|B] attribute of 36 bits. This operation does not affect RAM memory cells and does not disturb write operations on the other port. Similar to the read and write operation, the set/reset function is active only when the enable pin of the port is active. Set/reset polarity is configurable (active High by default).Address Bus - ADDR[A|B]<13:#><14:#><15:#>The address bus selects the memory cells for read or write. The data bit width of the port determinesthe required address bus width for a single RAMB18 or RAMB36, as shown in Table 4-6 and Table 4-7.For cascadable block RAM using the RAMB36, the data width is one bit, and the address bus is 16 bits <15:0>. The address bit 15 is only used in cascadable block RAM. For noncascading block RAM, connect High. Data and address pin mapping is further described in the “Additional RAMB18 and RAMB36 Prim itive Design Considerations”section.Data-In Buses - DI[A|B]<#:0> & DIP[A|B]<#:0>Data-in buses provide the new data value to be written into RAM. The regular data-in bus (DI), plus the parity data-in bus (DIP) when available, have a total width equal to the port width. For example the 36-bit port data width is represented by DI<31:0> and DIP<3:0>, as shown in Table 4-6 and Table 4-7. Data-Out Buses - DO[A|B]<#:0> and DOP[A|B]<#:0>Data-out buses reflect the contents of memory cells referenced by the address bus at the last active clock edge during a read operation. During a write operation (WRITE_FIRST or READ_FIRST configuration), the data-out buses reflect either the data being written or the stored value before write. During a write operation in NO_CHANGE mode, data-out buses are not changed. The regular data-out bus (DO) plus the parity data-out bus (DOP) (when available) have a total width equal to the port width, as shown in Table 4-6 and Table 4-7.Cascade In - CASCADEINLAT[A|B] and CASCADEINREG[A|B]The CASCA DEIN pins are used to connect two block RAMs to form the 64K x 1 mode (Figure 4-10.) This pin is used when the block RAM is the UPPER block RAM, and is connected to the CASCADEOUT pins of the LOW ER block RAM of the same port. When cascade mode is not used, this pin does not need to be connected. Refer to the “Cascadable Block RAM” for further information.CascadeOut - CASCADEOUTLAT[A|B] and CASCADEOUTREG[A|B]The CASCA DEOUT pins are used to connect two block RAMs to form the 64K x 1 mode. This pin is used when the block RAM is the LOW ER block RAM, and is connected to the CASCADEIN pins of the UPPER block RAM of the same port. When cascade mode is not used, this pin does not need to be connected. Refer to the “Cascadable Block RAM” for further information.Inverting Control PinsFor each port, the six control pins (CLK, EN, and SSR) each have an individual inversion option. EN and SSR control signals can be configured as active High or Low, and the clock can be active on a rising or falling edge (active High on rising edge by default), without requiring other logic resources. GSRThe global set/reset (GSR) signal of a Virtex-5 device is an asynchronous global signal that is active at the end of device configuration. The GSR can also restore the initial Virtex-5 device state at any time. The GSR signal initializes the output latches to the INIT (simple dual port), or to the INIT_A and INIT_B value (true dual port.) See “Block RAM Attributes.” A GSR signal has no impact on internal memory contents. Because it is a global signal, the GSR has no input pin at the functional level (block RAM primitive).Unused InputsUnused data and/or address inputs should be connected HighBlock RAM Address MappingEach port accesses the same set of 18,432 or 36,864 memory cells using an addressing scheme dependent on whether it is a RAMB18 or RAMB36. The physical RAM locations addressed for a particular width are determined using the following formula (of interest only when the two ports use different aspect ratios):END = ((A DDR + 1) Width) -1START = A DDR WidthTable 4-8 shows low-order address mapping for each port width.Block RAM AttributesAll attribute code examples are discussed in the “Block RAM Initialization in VHDL or Verilog Code” section. Further information on using these attributes is available in the“Additional RAMB18 and RAMB36 Primitive Design Considerations” section.Content Initialization - INIT_xxINIT_xx attributes define the initial memory contents. By default, block RAM memory is initialized with all zeros during the device configuration sequence. The 64 initialization attributes from INIT_00 through INIT_3F for the RAMB18, and the 128 initialization attributes from INIT_00 through INIT_7F for the RAMB36 represent the regular memory contents. Each INIT_xx is a 64-digit hex-encoded bit vector. The memory contents can be partially initialized and are automatically completed with zeros. The following formula is used for determining the bit positions for each INIT_xx attribute. Given yy = conversion hex-encoded to decimal (xx), INIT_xx corresponds to the memorycells as follows:f rom [(yy + 1) 256] – 1t o (yy) 256For example, for the attribute INIT_1F, the conversion is as follows:y y = conversion hex-encoded to decimal (xx) “1F” = 31f rom [(31+1) 256] – 1 = 8191t o 31 256 = 7936More examples are given in Table 4-9.Content Initialization - INITP_xxINITP_xx attributes define the initial contents of the memory cells corresponding to DIP/DOP buses (parity bits). By default these memory cells are also initialized to all zeros. The initialization attributes represent the memory contents of the parity bits. The eight initialization attributes are INITP_00 through INITP_07 for the RAMB18. The 16 initialization attributes are INITP_00 through INITP_0F for the RAMB36. Each INITP_xx is a 64-digit hex-encoded bit vector with a regular INIT_xx attribute behavior. The same formula can be used to calculate the bit positions initialized by a particular INITP_xx attribute.Output Latches Initialization - INIT (INIT_A or INIT_B)The INIT (single-port) or INIT_A and INIT_B (dual-port) attributes define the output latches or output register values after configuration. The width of the INIT (INIT_A andINIT_B) attribute is the port width, as shown in Table 4-10. These attributes are hexencoded bit vectors, and the default value is 0. In cascade mode, both the upper and lower block RAM should be initialized to the same value. Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B])The SRVA L (single-port) or SRVA L_A and SRVA L_B (dual-port) attributes define output latch values when the SSR input is asserted. The width of the SRVA L (SRVA L_A and SRVA L_B) attribute is the port width, as shown in Table 4-10. These attributes are hexencoded bit vectors and the default value is 0. This attribute sets the value of the output register when the optional output register attribute is set. When the register is not used, the latch gets set to the SRVA L instead. In the 36-bit mode, SRVA L[35:32] corresponds toDP[3:0].Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B])The SRVA L (single-port) or SRVA L_A and SRVA L_B (dual-port) attributes define output latch values when the SSR input is asserted. The width of the SRVA L (SRVA L_A and SRVA L_B) attribute is the port width, as shown in Table 4-10. These attributes are hexencoded bit vectors and the default value is 0. This attribute sets the value of the output register when the optional output register attribute is set. When the register is not used, the latch gets set to the SRVA L instead. In the 36-bit mode, SRVA L[35:32] corresponds toDP[3:0].Optional Output Register On/Off Switch - DO[A|B]_REGThis attribute sets the number of pipeline register at A/B output of the block RAM. The valid values are 0 (default) or 1.Extended Mode Address Determinant - RAM_EXTENSION_[A|B]This attribute determines whether the block RAM of interest has its A/B port as UPPER/LOW ER address when using the cascade mode. Refer to the “Cascadable Block RAM”section. When the block RAM is not used in cascade mode, the default value isNONE.Read Width - READ_WIDTH_[A|B]This attribute determines the A/B read port width of the block RAM. The valid values are:0 (default), 1, 2, 4, 9, 18, and 36.Write Width - WRITE_WIDTH_[A|B]This attribute determines the A/B write port width of the block RAM. The valid values are:0 (default), 1, 2, 4, 9, 18, and 36.Write Mode - WRITE_MODE_[A|B]This attribute determines the write mode of the A/B input ports. The possible values are WRITE_FIRST (default), READ_FIRST, and NO_CHANGE. Additional information on the write modes is in the “Write Modes” sectionBlock RAM Location ConstraintsBlock RAM instances can have LOC properties attached to them to constrain placement. Block RAM placement locations differ from the convention used for naming CLB locations, allowing LOC properties to transfer easily from array to array. The LOC properties use the following form:。
物流专业外文翻译5
1. The Definition of LogisticsAfter completing a commercial transaction, logistics will execute the transfer of goods from the supplier( seller) to the customer( buyer) in the most cost-effective manner. This is the definition of logistics. During the transfer process, hardware such as logistics facilities and equipment( logistics carriers) are needed, as well as information control and standardization. In addition, supports from the government and logistics association should be in place.Three major functions of logistics(1) Creating time value: same goods can be valued different at different times. Goods often stop during the transfer process, which is professionally called the storage of logistics. It creates the time value for goods.(2) Creating location value: same goods can be valued differently at different locations. The value added during the transfer process is the location value of logistics.(3) Distribution processing value: sometimes logistics create distribution processing value, which changes the length, thickness and packages of the goods. Like popular saying, “ cutting into smaller parts” is the most commonly seen distribution processing within logistics create added value for goods.2. Logistics is a new commercial area, developing from the traditional stage to a modern one. The main differences between these two stage include:(1) Modern logistics adopts containerization techniques. The goods transfer process starts with packaging, followed by transportation, storage and distribution. The whole process is operated under logistics standards. Based on the logistics base module of 600×400mm, from the logistics module of 1,200×1,000mm, and enlarge to the size of2,591×2,438mm-the size of high×wide of the container. It can be adjusted to the standard sizes of containers for trains, trucks and ships.(2) Information technologies are most important for modern logistics. Bar Code, POS, EDI and GPS systems dramatically improve the efficiency and accuracy of the logistics activities. Internet further assists the market development, operation and management of the logistics industry.3.International LogisticsAn increasing number of companies are involving in international markets through exporting, licensing, joins ventures, and ownership. This trend should continue. With such expansion there is a need to develop worldwide logistics networks. Integrated logistics management and cost analysis will be more complex and difficult to manage.There are some future trends in internationalization:(1) More logistics executives with international responsibilities(2) Expansion of the number and size of foreign trade zones.(3) Reduction in the amount of international paperwork and documentation(4) More foreign warehousing is owned and controlled by the exporting firm(5) Increasing number of smaller firm(6) Foreign ownership of logistics service firms, e. g., public warehousing and transportation carriers.(7) Increasing multiple distribution channelsThe international transport and the international logistics are same things in some way. So, when the international trading involved, the firm must establish international logistics systems to provide the products and service demanded. The most significant development in international logistics will be the increasing sophistication information system adopted and independent departments to operate.4.Packaging.Packaging performs two basic functions–marketing and logistics. In marketing the packaging acts promotion and advertising. Its size, weight, color, and printed information attract customers and convey knowledge of the product. When firms are involved in international marketing, packaging becomes even more important. Products sold to foreign countries travel greater distances and undergo more handling operations. The logistics package is to protect the products during the process of logistics.Scrap disposal. The logistics process must effectively and quickly handle, transport, and store waste products. If they can be reused or recycled, logistics company should arrange and move them to the re–production and re–processing locations.Return goods handling. The handling of return goods is often called reverse distribution. Buyers may return items to the seller for a number of reasons. Most logistics systems are not good enough to handle such cases. In many industries, consumers return products for warranty repair, replacement, or recycling, reverse distribution costs may be very high. Reverse distribution will become more important as customers demand more flexible and favorable return policies.5.Third Part Logistics ( TPL)Third Part Logistics provides all the logistics services. They act as a bridge or facilitator between the first part( supplier or producer) and the second part( buyer or customer). The primary objectives of third part logistics providers are to lower the total cost of logistics for the supplier and improve the service level to the customer.Third Part Logistics have been growing rapidly. Cost reduction and demands for batter and cheaper services are the main drives behind the growth. A third part logistics provider will be in a position to consolidate business from several companies and offer frequent pick–ups and deliveries, whereas in–house transportation cannot. Other reasons are as follows:* The company does not specialize in logistics;* The company does not have sufficient resources;* Eager to implement better logistics operation or does not have time to develop the required capabilities in–house;* The company is venturing into a new business with totally different logistics requirements;* Merger or acquisition may make outsourcing logistics operations more attractive than to integrate logistics operations.6.Global LogisticsDeveloped countries often deal with globalization in two ways: to be more cost competitive with third world countries, and to look for new partners in other countries to manufacture components, subassemblies and even the final products. The second approach forces most developed countrie s to get into a new area called “ global logistics”.Benefits of global operations include cheap raw materials and end products, lower labor cost, better quality, increased internal competition and better customer service. Some of the disadvantages are unreliable delivery, poor communication and longer time from design to finish production. Challenges are often cultural and linguistic differences, legal requirements, logistics suppliers or manufacturers, exchange rates.There are three major flows involved in global logistics: material flow, document flow and cash flow.7.Logistics into the FutureLogistics is changing at a rapid and acceleration rate. There are two reasons are its rapid growth:Firstly, pressure to change by the development of the system itself(1) High–speed computing and data transmission can instantly transmit and react to user demand(2) More flexible and accurate logistic planning and control through computers and data processing(3) Flexible computer facilities help problem solving and increase decisions accuracy(4) Awareness of total cost measurement and management accountingSecondly, pressures for changes from the wider economy.(1) Be flexible in handling markets of different sizes for better competition(2) There is increasing specialization in markets and growth in retailing.(3) Life cycles for products are shortening. Logistics systems need to be more efficient, faster and more flexible(4) Move from mass production towards flexible manufacturing system( FMS). These systems enable a company to switch production quickly from one product to another (5) Competitive pressures lead to more efforts to improve customer service.8.The process of logistical integration can be divided into four stages:Stage 1. Began in the early 1960s in the USA and involved the integration of all activities associated with distribution. Separate distribution departments were to coordinate the management of all processes within physical distributionmanagement( PDM).Stage 2. PDM was applied to the inbound movement of materials, components, and subassemblies, generally known as “ materials management”. By the late 1970s, many firms had established “ logistics department” with overall responsibility for the movement, storage, and handling of products upstream and downstream of the production operation.Stage 3. Logistics plays an important coordinating role, as it interfaces with most other functions. With the emergence of business process re–engineering( BPR) in the early 1990s, the relationship between logistics and related functions was redefined.“ System integration” occurred. Cross–functional integration should achieve greater results.物流的定义在完成商业交易之后,物流将以最低成本和最高效益的方式执行将商品从供应商(卖方)流转到顾客(买方)的过程。
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译文一：CuNi10Fe1Mn合金空心坯水平电磁连铸的研究Yan Zhiming a,b, Li Xintao a,c, Qi Kai a,b, Cao Zhiqiang a,b, Zhang Xiaoli a,b, Li Tingju a,b,*a School of Materials Science and Engineering, Dalian University of Technology, Dalian 116085, Chinab State Key Laboratory for Materials Modification by Laser, Ion and Electron Beams, Dalian University of Technology, Dalian 116085, Chinac Gaoxin Zhangtong Co. Ltd., Zhangjiagang 215600, China摘要：旋转磁场用于商业频率试验CuNi10Fe1Mn合金空心坯电磁连铸水平。
对于低倍组织下旋转磁场的凝固的影响，元素的分布和力学性能进行了研究。
结果表明，在旋转磁场的应用下，非宏观结构转变为宏观均匀柱状晶粒结构。
平均粒径降低从6.1到0.56毫米。
元素偏析也受到限制。
薄板的拉伸强度和伸长率增加20.3%，改进65.7%要高于没有旋转磁场。
此外，对于旋转磁场的作用机理进行讨论从而解释它的效果对提高凝固宏观结构，分析元素的分布和力学性能有所帮助。
关键词：有色金属及合金铸造金相1．介绍CuNi10Fe1Mn合金是一种铜合金材料,广泛作为冷却条件应用于海运方面，除了海水和海上电力行业。
如今，CuNi10Fe1Mn合金空心坯连续铸造通常产生坯穿孔、劈去。
以前这个过程很复杂，而且是个产量低，没有竞争力的市场。
如果可以使用空心铸坯直接，这个程序将会缩短时间，增加产量,大大降低了成本。
通过研究人员和生产工厂,使得更多的注意力集中在水平连续铸造，因为它的中间包函结晶器，从而防止次生氧化和获得清晰的熔体，获得高质量铸件，提高利用率和适应金属使用短程序。
得到网形铸件来节约能源。
MHD是一门近年来广泛应用于冶金行业和研究电液在电磁场的运动律法的课程。
电磁场也用在水平连铸坯的空洞。
罗德里奎兹用交变磁场的商业频率来制造30毫米~6毫米的水平连续铸造铜空心坯。
起到了明显细化金属凝固组织的作用。
李和他的研究小组把商业频率和平均频率应用到生产工艺上,使铜合金空心坯取得了明显的进步。
本文探讨了电磁连铸的工艺水平在83毫米~21毫米的CuNi10Fe1Mn合金空心坯。
研究了旋转磁场商业频率对于低倍组织凝固的影响，研究元素的分布和力学性能并探讨其作用机理。
2．实验2.1．实验仪器在实验室里建立一个试用的电磁连铸水平尺度系统。
图1显示的实验仪器,中间包，包含商业频率，结晶器，绘制系统、电磁系统。
图1.实验装置：(1)线圈；(2)冷却系统；(3)图系统；(4)石墨内模沙土；(5)冷却水；(6)中间包；(7)熔融金属结晶器是由石墨内模以及铜外的夹克组成。
石墨的长度为385毫米,内模沙土内芯的锥度是1°。
这是由RMF三相感应线圈外三杆石墨内模组成。
2.2.实验材料和工艺表1 CuNi10Fe1Mn标称成分的合金(wt. %)内模沙土以外的石墨距离(mm)图2.在石墨内模以及凝固壳RMF再不同频率的衰减曲线当频率为50Hz,穿越屏蔽石墨和凝固壳内模沙土的磁通密度仍然是63.3%；然而当频率为1000Hz时，磁通密度只剩下12.9%。
频率提高,它越被减弱，就像图2显示的。
所以为了在融化时加强磁通密度，频率选择50Hz。
在商业频率下加工玻璃，直到1230°才融化。
针对CuNi10Fe1Mn合金的特点，选择的铸造工艺是绘画-停留-换向-停止。
水平电磁连铸坯CuNi10Fe1Mn合金空心参数显示在表3。
表3 水平电磁连铸坯CuNi10Fe1Mn合金空心参数3. 结果和讨论3.1. RMF在凝固宏观结构上的影响在水平连铸时，只有在自由对流存在的情况下，高温度梯度高导致玻璃径向方向和柱状生长。
在底部区域,由于石墨的内部墙壁内模以自己的重力，空心坯基于较低的区域,因此允许良好的散热。
在最上面的区域，由于凝固壳和石墨内模沙土之间的差距形成初始收缩，影响散热。
因此，在横断面上的是非均匀凝固宏观结构，体现了一个细柱状粒的顶级区域划分，在底部区域有些地方由于空心坯非均匀散热导致出现粗的柱状颗粒,如图3所示。
从冷冻表面到中心的柱状颗粒的成长方向近乎平行于热流动的方向。
加入RMF之后，原非均匀宏观结构转变为均匀宏观结构柱状晶粒,如图3 b显示。
图3. RMF对CuNi10Fe1Mn合金空心铸坯的宏观组织在凝固过程的影响:(a)没有RMF(b)有RMF,I=120图4.平均粒径对RMF CuNi10Fe1Mn合金空心坯的影响图4显示了输入电流强度不同，平均晶粒尺寸不同对不同地区的合金空心坯CuNi10Fe1Mn周长的影响。
在空心坯周长上平均粒度参差不齐。
随输入电流强度的改变，宏观结构凝固的更加精细，相应的周长甚至变得更长。
当I=120A,平均晶粒尺寸约0.56毫米，与没有相比RMF少了6.1毫米。
然而，当I=140A,一些核核心产生的焦耳热会引起涡流，所以,平均晶粒尺寸较大。
当限制交流电时,产生的旋转电磁场使线圈融化。
这个领域，从另一方面说，熔体在通以交流电时，会产生一个相位相反感应涡流。
结果，熔体受到电磁身体力量的相互作用引起涡流和旋转磁场。
可以以如下表达：F=J×B=(1／μ)(▽×B)×B (2)J是诱发的涡流，B和μ分别代表磁通量密度和磁导率，▽是哈密顿算符。
由于冷却水寒冷，石墨内部墙内模到出口温度边界层,其中有一个深过冷程度。
在石墨内模沙土熔体产生异质核化的基础上，需要更少的形核密度以及成核的工作。
由于地心引力和凝固收缩而产生的非均匀散热效果，树枝晶日益增长的速度是不同的，在底部区域树枝晶生长快,顶部的树枝晶生长慢。
因此树枝晶从下到上贯穿整个空心坯的一侧。
因为不同的树枝晶长短变化的运动方向不同,强制对流驱动RMF诱导融化从边缘到中心的,然后再从中心到边。
所以由于高度梯度对接追踪的强制对流是螺旋的。
因此沿着石墨内核，熔体产生一个以径向和轴向的强制循环运动旋涡回流。
虚拟模型对熔体内流石墨内模强制与RMF被显示在图5。
图5.虚拟模型对熔体内流石墨内模强制与RMF低温熔体的边缘附近用电磁场把石墨内模带进中心空心坯，伴随着熔体温度降低。
熔体二次产生树枝晶地区温度波动所产生的磁场倾向于接近树干的主要枝干。
强制对流造成RMF产生的剪切力, 使大量的树枝晶是断裂。
那些融合或者折断的枝状突起在熔体内RMF均匀分布,成为核芯，所以成核速率增加。
温度和浓度波动,及在成核的界面的成分过冷温度梯度，以至于在这样的温度和浓度场下抑制晶体的生长从而均匀的内部消化。
RMF的应用，成核速率随温度梯度的转化增加而降低,促进树枝晶粒生长和晶粒均匀状态。
在存在剪切力的情况下,旋转晶粒消除剪切力的增长。
抑制生长的对接，提高固液界面的稳定性和促进成核芯继续呈球形有利于获得球形结构。
由于大量的晶粒颗粒形成，结晶发生同时,在整个横断面形成一个均匀结构。
3.2.RMF对元素的分布和力学性能的影响电子探针做定性分析时,揭示RMF对镍、铁、锰元素的分布的影响，如图6。
结果表明,无RMF，镍、铁、锰元素存在着明显的分布隔离，而RMF可以有效的抑制这种隔离。
图6.由电子探针分析得出RMF对CuNi10Fe1Mn合金空心坯元素分布的影响，红线、棕色路线、绿线,蓝色线分别代表了铜、镍、铁、锰元素(a)没有RMF(b)有RMF,I=120A。
元素的分布是原子扩散的过程,可以设定α来表示扩散程度，如下所示：α=Dτ／ι² （3）D是溶质扩散系数,τ是扩散时间，即部分凝固时间,ι是扩散长度。
根据阿伦尼斯方程,D也可以表达为：D=D0exp（-Q／RT）（4）D0是扩散常数，R是气体常数，Q是活化能，T是绝对温度。
RMF的应用，颗粒系数精确地减少ι，所以隔离距离和范围范围的减少，元素化学成分偏析受到限制。
取自CuNi10Fe1Mn合金空心坯顶部和底部的样品，与没有RMF作用的样品，进行拉伸试验的对比。
图7揭示了输入电流强度对CuNi10Fe1Mn合金空心坯的力学性能的影响。
在圆周方向上，两个最终拉伸强度和伸长率都不一样。
随着输入的电流强度的加强，他们的数值跟着增加和方向逐渐统一。
然而，在I=120A时可以找到一个转折点，力学性能开始减少。
图7.RMF对CuNi10Fe1Mn合金空心坯的力学性能的影响:(a)抗拉强度(b)伸长率图8.利用扫面电镜观察到的CuNi10Fe1Mn合金空心坯拉伸断口形貌:(a)没有RMF(b)有RMF,I=120A。
图8显示了在I=120A，以及是否存在RMF的情况下使用扫描电镜对空心坯表面拉伸断口形貌的观察。
没有存在RMF时，凹痕小而浅，当存在RMF时，凹痕又大又深，显示了良好的延展性。
与拉伸试验相符。
在颗粒细数精确之后，相邻颗粒的变形协调可以改善或者提高力学性能。
拉伸断口的凹痕的大小和深浅反映了塑性变形的能力，数量和分布沉淀阶段。
扫描电镜观察形貌和断口证明拉伸的作用,RMF对提高凝固结构元素的分布及其均匀性，提高力学性能的作用。
4.结论RMF在水平连续铸造CuNi10Fe1Mn合金空心坯的应用，熔体内树枝晶融为一体,然后断裂。
温度和浓度场使晶粒均匀的内部熔化，有利于形成颗粒。
原非均匀柱状孔结构化为晶粒宏观结构, 平均粒度从6.1毫米降低到0.56毫米，和有效地抑制了元素偏析。
与没有应用RMF相比，最终拉伸强度提高20.3%,伸长率提高了65.7%。
致谢感谢国家自然科学基金的支持(No. 50274017).指导教师评语：张海鹏同学在指定时间内认真翻译了铜合金制备工艺及材料检测技术领域的外文文献，了解了材料的制备工艺和检测设备的性能，掌握了当前人们在该领域所作的工作，为接下来文献综述的撰写奠定了基础。
该生具有较强的翻译外文资料的能力，译文的内容与原文较为相符，翻译的专业词汇较为贴切，语句通顺。
成绩：教师签名：。