DDR及DDR2内存供电电路

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内存供电电路工作原理

无复位先测量主板各个供电是否正常，包括内存供电、桥供电、总线供电和CPU 供电。

测量内存电压1.8V正常。

电脑主板内存供电电路分析内存供电电路工作原理SDRAM内存使用3.3V供电，DDR内存使用2.5V供电。

使用SDRAM内存的主板，常见的都是直接由ATX电源供电，只有少数高档主板上才采用独立供电。

如图5-1所示，用万用表测量电源插座的第1脚与SDRAM内存插槽3.3V电源输入脚，它们之间是直通的。

而使用DDR内存的主板，都设计有独立的内存供电电路。

内存供电电路工作原理内存供电电路人多采用集成运算放大器驱动场效应管的方式，其供电原理如图5-2所示，内存供电实际电路如图5-3所示。

图5-2内存供电电路的原理是这样的：从A点取得2.5V的基准电压进入到运算放大器的同相输入端IN+，运算放大器将IN+与IN-的电压相比较，如果IN+的电压大于IN-的电压，那么OUT的电压上升，OUT的电压上升使得Q1场效应管进一步导通，漏极（D）与源极（S）之间的管压降下降，使得B点的电压上升。

通过反馈，IN-的电压也上升，直到IN +=IN-，也就是IN+=B 。

这个过程可以简单地描述为：（IN+>IN-）→（OUT ↑）→（DS ↓）→（B ↑）→（IN-↑），直到IN+=IN-。

同理，当IN+<IN-时，它的稳压过程是这样的：（IN+<IN-）→（OUT↓）→（DS↑）→（B↓）→（IN-↓），直到IN+=IN-。

这个电路通过反馈比较，间接地控制B点的电压与基准电压相等，因此有时也称运算放大器为比较放大器。

要使B点的电压稳定，必须保证A点的电压稳定，也就是要求基准电压要稳定。

在图5-2的电路中，根据串联电路分压的原理，电阻两端的电压与其阻值的大小成正比，可以算出A点对地的电压为：3.3V×（3.24K/（IK+3.24K》≈2.5V这是使用最简单的串联分压方法取得2.5V的基准电压。

【主板内存供电电路分析】主板内存供电电路分析方法,主板内存供电电路知识

【主板内存供电电路分析】主板内存供电电路分析方法,主板内
存供电电路知识
本文关键词：
主板内存供电电路分析：
一、主板内存供电电路的功能
内存供电电路主要是向内存提供其所需的3. 3V电压、2.5V、1 .8V. 1.25V上拉电压、0.9V上拉电压等，如
果内存供电电路过于简单或设计不合理就会出现内存供电不足的现象，继而影响主板的稳定性。

二、主板内存供电电路的组成分类
1.内存供电电路主要包括两种供电方式，一种为开关电源组成的供电方式，采用这种方式的供电电路主要由
专业电源管理芯片、电感、场效应管、滤波电容等部件组成，如图上所示。

这种供电电路的工作原理和CPU供
电电路的原理比较相似。

2.另一种供电方式为采用低压差线性调压芯片组成的调压电路进行供电的方式，调压电路组成的内存供电电
路主要由运算放大器（如LM358）、精密稳压器（如TL431）、场效应管、电阻和电容等组成。

如图所示为采
用调压方式的内存供电电路。

三星DDR2内存电路资料

DDR2 Unbuffered SODIMM200pin Unbuffered SODIMM based on 1Gb Q-die64-bit Non-ECC60FBGA & 84FBGA with Lead-Free and Halogen-Free(RoHS compliant)INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similarapplications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Table of Contents1.0 DDR2 Unbuffered SODIMM Ordering Information (4)2.0 Features (4)3.0 Address Configuration (4)4.0 Pin Configurations (Front side/Back side) (5)5.0 Pin Description (5)6.0 Input/Output Function Description (6)7.0 Functional Block Diagram : (7)7.1 2GB, 256Mx64 Module - M470T5663QZ(H)3 (7)7.2 1GB, 128Mx64 Module - M470T2864QZ(H)3 (8)7.3 512MB, 64Mx64 Module - M470T6464QZ(H)3 (9)8.0 Absolute Maximum DC Ratings (10)9.0 AC & DC Operating Conditions (10)9.1 Recommended DC Operating Conditions (SSTL - 1.8) (10)9.2 Operating Temperature Condition (11)9.3 Input DC Logic Level (11)9.4 Input AC Logic Level (11)9.5 AC Input Test Conditions (11)10.0 IDD Specification Parameters Definition (12)11.0 Operating Current Table : (13)11.1 M470T5663QZ(H)3 : 256Mx64 2GB Module (13)11.2 M470T2864QZ(H)3 : 128Mx64 1GB Module (13)11.3 M470T6464QZ(H)3 : 64Mx64 512MB Module (13)12.0 Input/Output Capacitance (14)13.0 Electrical Characteristics & AC Timing for DDR2-800/667 (14)13.1 Refresh Parameters by Device Density (14)13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin (14)13.3 Timing Parameters by Speed Grade (15)14.0 Physical Dimensions : (17)14.1 128Mbx8 based 256Mx64 Module (2 Rank) (17)14.2 64Mbx16 based 128Mx64 Module (2 Rank) (18)14.3 64Mbx16 based 64Mx64 Module (1 Rank) (19)Revision HistoryRevision Month Year History1.0September2007 - Initial Release1.01April2008 - Typo Correction1.1July2008 - Applied JEDEC update(JESD79-2E) on AC timing table1.0 DDR2 Unbuffered SODIMM Ordering InformationPart Number Density Organization Component Composition Number of Rank Height M470T5663QZ(H)3-C(L)E7/F7/E62GB256Mx64128Mx8(K4T1G084QQ-HC(L)E7/F7/E6)*16230mm M470T2864QZ(H)3-C(L)E7/F7/E61GB128Mx6464Mx16(K4T1G164QQ-HC(L)E7/F7/E6)*8230mm M470T6464QZ(H)3-C(L)E7/F7/E6512MB64Mx6464Mx16(K4T1G164QQ-HC(L)E7/F7/E6)*4130mm Note :1. “Z” of Part number(12th digit) stands for Lead-Free products.2. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.3. “3” of Part number(13th digit) stands for Dummy Pad PCB products.2.0 Features•Performance rangeE7 (DDR2-800)F7 (DDR2-800)E6 (DDR2-667)UnitSpeed@CL3400-400MbpsSpeed@CL4533533533MbpsSpeed@CL5800667667MbpsSpeed@CL6-800-MbpsCL-tRCD-tRP5-5-56-6-65-5-5CK•JEDEC standard V DD = 1.8V ± 0.1V Power Supply•V DDQ = 1.8V ± 0.1V•333MHz f CK for 667Mb/sec/pin, 400MHz f CK for 800Mb/sec/pin•8 Banks•Posted CAS•Programmable CAS Latency: 3, 4, 5, 6•Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5•Write Latency(WL) = Read Latency(RL) -1•Burst Length: 4 , 8(Interleave/Nibble sequential)•Programmable Sequential / Interleave Burst Mode•Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)•Off-Chip Driver(OCD) Impedance Adjustment•On Die Termination with selectable values(50/75/150 ohms or disable)•Average Refresh Period 7.8us at lower than a T CASE 85°C, 3.9us at 85°C < T CASE < 95 °C- Support High Temperature Self-Refresh rate enable feature•Package: 60ball FBGA - 128Mx8 and 84ball FBGA - 64Mx16•All of base components are Lead-Free, Halogen-Free, and RoHS compliantNote : For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.3.0 Address ConfigurationOrganization Row Address Column Address Bank Address Auto Precharge 128Mx8(1Gb) based Module A0-A13A0-A9BA0-BA2A1064Mx16(1Gb) based Module A0-A12A0-A9BA0-BA2A10Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules.Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1V REF 2V SS 51DQS252DM2101A1102A0151DQ42152DQ463V SS 4DQ453V SS 54V SS 103V DD 104V DD 153DQ43154DQ475DQ06DQ555DQ1856DQ22105A10/AP 106BA1155V SS 156V SS 7DQ18V SS 57DQ1958DQ23107BA0108RAS 157DQ48158DQ529V SS 10DM059V SS 60V SS 109WE 110S0159DQ49160DQ5311DQS012V SS 61DQ2462DQ28111V DD 112V DD 161V SS 162V SS 13DQS014DQ663DQ2564DQ29113CAS 114ODT0163NC, TEST 164CK115V SS 16DQ765V SS 66V SS 115NC/S1116A13165V SS 166CK117DQ218V SS 67DM368DQS3117V DD 118V DD 167DQS6168V SS 19DQ320DQ1269NC 70DQS3119NC/ODT1120NC 169DQS6170DM621V SS 22DQ1371V SS 72V SS 121V SS 122V SS 171V SS 172V SS 23DQ824V SS 73DQ2674DQ30123DQ32124DQ36173DQ50174DQ5425DQ926DM175DQ2776DQ31125DQ33126DQ37175DQ51176DQ5527V SS 28V SS 77V SS 78V SS 127V SS 128V SS 177V SS 178V SS 29DQS130CK079CKE080NC/CKE1129DQS4130DM4179DQ56180DQ6031DQS132CK081V DD 82V DD131DQS4132V SS 181DQ57182DQ6133V SS 34V SS 83NC 84NC 133V SS 134DQ38183V SS 184V SS 35DQ1036DQ1485BA286NC 135DQ34136DQ39185DM7186DQS737DQ1138DQ1587V DD 88V DD 137DQ35138V SS 187V SS 188DQS739V SS 40V SS 89A1290A11139V SS 140DQ44189DQ58190V SS 41V SS 42V SS 91A992A7141DQ40142DQ45191DQ59192DQ6243DQ1644DQ2093A894A6143DQ41144V SS 193V SS 194DQ6345DQ1746DQ2195V DD 96V DD 145V SS 146DQS5195SDA 196V SS 47V SS 48V SS 97A598A4147DM5148DQS5197SCL 198SA049DQS250NC99A3100A2149V SS150V SS199V DDSPD200SA15.0 Pin Description*The V DD and V DDQ pins are tied to the single power-plane on PCB.Pin Name DescriptionPin Name DescriptionCK0,CK1Clock Inputs, positive line SDA SPD Data Input/OutputCK0,CK1Clock Inputs, negative line SA1,SA0SPD address CKE0,CKE1Clock Enables DQ0~DQ63Data Input/Output RAS Row Address Strobe DM0~DM7Data Masks CAS Column Address Strobe DQS0~DQS7Data strobesWE Write Enable DQS0~DQS7Data strobes complement S0,S1Chip Selects TEST Logic Analyzer specific test pin (No connect on So-DIMM)A0~A9, A11~A13Address InputsV DD Core and I/O Power A10/AP Address Input/Autoprecharge V SS GroundBA0~BA2SDRAM Bank Address V REF Input/Output Reference ODT0,ODT1On-die termination controlV DDSPD SPD PowerSCL Serial Presence Detect(SPD) Clock Input NC Spare pins, No connect CK0,CK1Clock Inputs, positive lineSDASPD Data Input/Output4.0 Pin Configurations (Front side/Back side)Symbol Type DescriptionCK0-CK1CK0-CK1Input The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output timing for read operations is synchronized to the input clock.CKE0-CKE1Input Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refesh mode.S0-S1Input Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0, Rank 1 is selected by S1. Ranks are also called “Physical banks”.RAS, CAS, WE Input When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE define the operation to be executed by the SDRAM.BA0~BA2Input Selects which DDR2 SDRAM internal bank is activated.ODT0~ODT1Input Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended Mode Register Set (EMRS).A0~A9, A10/AP, A11~A13InputDuring a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, auto-precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to con-trol which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.DQ0~DQ63In/Out Data Input/Output pins.DM0~DM7Input The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect.DQS0~DQS7 DQS0~DQS7In/OutThe data strobes, associated with one data byte, sourced with data transfers. In Write mode, the datastrobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe issourced by the DDR2 SDRAMs and is sent at the leading edge of the data window. DQS signals are com-plements, and timing is relative to the crosspoint of respective DQS and DQS If the module is to be oper-ated in single ended strobe mode, all DQS signals must be tied on the system board to V SS and DDR2SDRAM mode registers programmed appropriately.V DD,V DDSPD,V SS Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module.SDA In/Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be con-nected to V DD to act as a pull up.SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to V DD to act as a pull up.SA0~SA1Input Address pins used to select the Serial Presence Detect base address.TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SO-DIMMs).6.0 Input/Output Function DescriptionNote : There is no specific device V DD supply voltage requirement for SSTL-1.8 compliance. However under all conditions V DDQ must be less than or equalto V DD .1. The value of V REF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x V DDQ of the transmitting device and V REF is expected to track variations in V DDQ .2. Peak to peak AC noise on V REF may not exceed +/-2% V REF (DC).3. V TT of transmitting device must track V REF of receiving device.4. AC parameters are measured with V DD , V DDQ and V DDL tied together.5. SODIMMs that include an optional temperature sensor may require a restricted V DDSPD operating voltage range for proper operation of the temperature sensor. Refer to the thermal sensor specification for details regarding the supported voltage range. All other functions of the SODIMM SPD are supported across the full V DDSPD range.Symbol ParameterRatingUnits NotesMin.Typ. Max.V DD Supply Voltage 1.7 1.8 1.9V V DDL Supply Voltage for DLL 1.7 1.8 1.9V 4V DDQ Supply Voltage for Output 1.7 1.8 1.9V 4V REF Input Reference Voltage 0.49*V DDQ 0.50*V DDQ0.51*V DDQ mV 1,2V TTTermination VoltageV REF -0.04V REFV REF +0.04V3Symbol ParameterRatingUnits Notes Min.Max.V DDSPDCore Supply Voltage1.73.6V5Note :1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.Symbol ParameterRating Units Notes V DD Voltage on V DD pin relative to V SS - 1.0 V ~ 2.3 V V 1V DDQ Voltage on V DDQ pin relative to V SS - 0.5 V ~ 2.3 V V 1V DDL Voltage on V DDL pin relative to V SS - 0.5 V ~ 2.3 V V 1V IN, V OUT Voltage on any pin relative to V SS- 0.5 V ~ 2.3 V V1T STGStorage Temperature-55 to +100°C 1, 29.0 AC & DC Operating Conditions9.1 Recommended DC Operating Conditions (SSTL - 1.8)8.0 Absolute Maximum DC RatingsNote:1. Input waveform timing is referenced to the input signal crossing through the V IH/IL (AC) level applied to the device under test.2. The input signal minimum slew rate is to be maintained over the range from V REF to V IH (AC) min for rising edges and the range from V REF to V IL (AC)max for falling edges as shown in the below figure.3. AC timings are referenced with input waveforms switching from V IL (AC) to V IH (AC) on the positive transitions and V IH (AC) to V IL (AC) on the negative transitions.Symbol ConditionValue Units Notes V REF Input reference voltage0.5 * V DDQV 1V SWING(MAX)Input signal maximum peak to peak swing 1.0V 1SLEWInput signal minimum slew rate1.0V/ns2, 3V DDQ V IH (AC) minV IH (DC) min V REFV IL (DC) max V IL (AC) maxV SS< AC Input Test Signal Waveform >V SWING(MAX)delta TRdelta TFV REF - V IL (AC) maxdelta TFFalling Slew =Rising Slew =V IH (AC) min - V REFdelta TRNote :1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard.2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.Symbol Parameter Rating UnitsNotesT OPEROperating Temperature0 to 95°C 1, 29.3 Input DC Logic LevelSymbol Parameter Min.Max.Units NotesV IH (DC)DC input logic high V REF + 0.125V DDQ + 0.3V V IL (DC)DC input logic low- 0.3V REF - 0.125V9.4 Input AC Logic LevelSymbol Parameter DDR2-667, DDR2-800Units Min.Max.V IH (AC)AC input logic high V REF + 0.200V V IL (AC)AC input logic lowV REF - 0.200V9.5 AC Input Test Conditions 9.2 Operating Temperature Condition(IDD values are for full operating range of Voltage and Temperature)Symbol Proposed Conditions Units NoteIDD0Operating one bank active-precharge current;tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD1Operating one bank active-read-precharge current;IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data patternis same as IDD4WmAIDD2P Precharge power-down current;All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATINGmAIDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Databus inputs are FLOATINGmAIDD2N Precharge standby current;All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;Data bus inputs are SWITCHINGmAIDD3P Active power-down current;All banks open; tCK = tCK(IDD); CKE is LOW; Other control and addressbus inputs are STABLE; Data bus inputs are FLOATINGFast PDN Exit MRS(12) = 0mASlow PDN Exit MRS(12) = 1mAIDD3N Active standby current;All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD4W Operating burst write current;All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP= tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data businputs are SWITCHINGmAIDD4R Operating burst read current;All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-ING; Data pattern is same as IDD4WmAIDD5B Burst auto refresh current;tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands;Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHINGmAIDD6Self refresh current;CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs areFLOATING; Data bus inputs are FLOATINGNormal mALow Power mAIDD7Operating bank interleave read current;All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid com-mands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the followingpage for detailed timing conditionsmA10.0 IDD Specification Parameters Definition11.2 M470T2864QZ(H)3 : 128Mx64 1GB Module11.3 M470T6464QZ(H)3: 64Mx64 512MB Module(T A =0o C, V DD = 1.9V)* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.Symbol 800@CL=5800@CL=6667@CL=5Units NotesCE7LE7CF7LF7CE6LE6IDD0500500480mA IDD1540540520mA IDD2P 120641206412064mA IDD2Q 240240240mA IDD2N 280280280mA IDD3P-F 280280280mA IDD3P-S 144144144mA IDD3N 360360340mA IDD4W 660660600mA IDD4R 840840760mA IDD5720720700mA IDD6120641206412064mA IDD71,2001,2001,120mA(T A =0o C, V DD = 1.9V)* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.Symbol 800@CL=5800@CL=6667@CL=5Units NotesCE7LE7CF7LF7CE6LE6IDD0360360340mA IDD1400400380mA IDD2P 603260326032mA IDD2Q 120120120mA IDD2N 140140140mA IDD3P-F 140140140mA IDD3P-S 727272mA IDD3N 220220200mA IDD4W 520520460mA IDD4R 700700620mA IDD5580580560mA IDD6603260326032mA IDD71,0601,060980mA11.0 Operating Current Table :11.1 M470T5663QZ(H)3 : 256Mx64 2GB Module(T A =0o C, V DD = 1.9V)* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.Symbol800@CL=5800@CL=6667@CL=5Units NotesCE7LE7CF7LF7CE6LE6IDD0880880840mA IDD1960960920mA IDD2P 240128240128240128mA IDD2Q 480480480mA IDD2N 560560560mA IDD3P-F 560560560mA IDD3P-S 288288288mA IDD3N 720720680mA IDD4W 1,2001,2001,120mA IDD4R 1,3601,3601,240mA IDD51,4401,4401,400mA IDD6240128240128240128mA IDD72,2802,2802,120mA(V DD =1.8V, V DDQ =1.8V, TA=25o C)* DM is internally loaded to match DQ and DQS identically.Parameter Symbol Min Max Min Max Min Max UnitsNon-ECCM470T5663QZ(H)3M470T2864QZ(H)3M470T6464QZ(H)3Input capacitance, CK and CKCCK -48-32-24pF Input capacitance, CKE , CS, Addr, RAS, CAS, WE CI -42-34-34Input/output capacitance, DQ, DM, DQS, DQSCIO-9-9- 5.5ParameterSymbol256Mb 512Mb 1Gb 2Gb 4Gb Units Refresh to active/Refresh command time tRFC 75105127.5195327.5ns Average periodic refresh intervaltREFI0 °C ≤ T CASE ≤ 85°C 7.87.87.87.87.8µs 85 °C < T CASE ≤ 95°C 3.93.93.93.93.9µs(0 °C < T OPER < 95 °C; V DDQ = 1.8V + 0.1V; V DD = 1.8V + 0.1V)13.1 Refresh Parameters by Device DensitySpeedDDR2-800(E7)DDR2-800(F7)DDR2-667(E6)UnitsBin (CL - tRCD - tRP) 5 - 5 - 56 - 6- 6 5 - 5 - 5Parameter min max min max min max tCK, CL=358--58ns tCK, CL=4 3.758 3.758 3.758ns tCK, CL=5 2.583838ns tCK, CL=6-- 2.58--ns tRCD 12.5-15-15-ns tRP 12.5-15-15-ns tRC 57.5-60-60-ns tRAS457000045700004570000ns13.2 Speed Bins and CL, tRCD, tRP , tRC and tRAS for Corresponding Bin13.0 Electrical Characteristics & AC Timing for DDR2-800/66712.0 Input/Output Capacitance(Refer to notes for informations related to this table at the component datasheet)Parameter SymbolDDR2-800DDR2-667Units Notes min max min maxDQ output access time from CK/CK tAC-400400- 450450ps40 DQS output access time from CK/CK tDQSCK-350350- 400400ps40 Average clock HIGH pulse width tCH(avg)0.480.520.480.52tCK(avg)35,36 Average clock LOW pulse width tCL(avg)0.480.520.480.52tCK(avg)35,36CK half pulse period tHP Min(tCL(abs),tCH(abs))xMin(tCL(abs),tCH(abs))x ps37Average clock period tCK(avg)2500800030008000ps35,36DQ and DM input hold time tDH(base)125x175x ps6,7,8,21,28,31 DQ and DM input setup time tDS(base)50x100x ps6,7,8,20,28,31 Control & Address input pulse width for each input tIPW0.6x0.6x tCK(avg)DQ and DM input pulse width for each input tDIPW0.35x0.35x tCK(avg)Data-out high-impedance time from CK/CK tHZ x tAC(max)x tAC(max)ps18,40 DQS/DQS low-impedance time from CK/CK tLZ(DQS)tAC(min)tAC(max)tAC(min)tAC(max)ps18,40DQ low-impedance time from CK/CK tLZ(DQ)2*tAC(min)tAC(max)2*tAC(min)tAC(max)ps18,40 DQS-DQ skew for DQS and associated DQ signals tDQSQ x200x240ps13DQ hold skew factor tQHS x300x340ps38DQ/DQS output hold time from DQS tQH tHP - tQHS x tHP - tQHS x ps39 DQS latching rising transitions to associated clock edges tDQSS- 0.250.25-0.250.25tCK(avg)30 DQS input HIGH pulse width tDQSH0.35x0.35x tCK(avg)DQS input LOW pulse width tDQSL0.35x0.35x tCK(avg)DQS falling edge to CK setup time tDSS0.2x0.2x tCK(avg)30 DQS falling edge hold time from CK tDSH0.2x0.2x tCK(avg)30 Mode register set command cycle time tMRD2x2x nCKMRS command to ODT update delay tMOD012012ns32 Write postamble tWPST0.40.60.40.6tCK(avg)10 Write preamble tWPRE0.35x0.35x tCK(avg)Address and control input hold time tIH(base)250x275x ps5,7,9,23,29 Address and control input setup time tIS(base)175x200x ps5,7,9,22,29 Read preamble tRPRE0.9 1.10.9 1.1tCK(avg)19,41 Read postamble tRPST0.40.60.40.6tCK(avg)19,42 Activate to activate command period for 1KB page size products tRRD7.5x7.5x ns4,32 Activate to activate command period for 2KB page size products tRRD10x10x ns4,32 13.3 Timing Parameters by Speed GradeParameter SymbolDDR2-800DDR2-667Units Notes min max min maxFour Activate Window for 1KB page size products tFAW35x37.5x ns32 Four Activate Window for 2KB page size products tFAW45x50x ns32 CAS to CAS command delay tCCD2x2x nCKWrite recovery time tWR15x15x ns32 Auto precharge write recovery + precharge time tDAL WR + tnRP x WR + tnRP x nCK33 Internal write to read command delay tWTR7.5x7.5x ns24,32 Internal read to precharge command delay tRTP7.5x7.5x ns3,32 Exit self refresh to a non-read command tXSNR tRFC + 10x tRFC + 10x ns32 Exit self refresh to a read command tXSRD200x200x nCKExit precharge power down to any command tXP2x2x nCKExit active power down to read command tXARD2x2x nCK1 Exit active power down to read command(slow exit, lower power)tXARDS8 - AL x7 - AL x nCK1,2 CKE minimum pulse width (HIGH and LOW pulse width)tCKE3x3x nCK27 ODT turn-on delay tAOND2222nCK16 ODT turn-on tAON tAC(min)tAC(max)+0.7tAC(min)tAC(max)+0.7ns6,16,40ODT turn-on (Power-Down mode)tAONPD tAC(min)+22*tCK(avg)+tAC(max)+1tAC(min)+22*tCK(avg)+tAC(max)+1nsODT turn-off delay tAOFD 2.5 2.5 2.5 2.5nCK17,45 ODT turn-off tAOF tAC(min)tAC(max)+0.6tAC(min)tAC(max)+0.6ns17,43,45ODT turn-off (Power-Down mode)tAOFPD tAC(min)+22.5*tCK(avg)+tAC(max)+1tAC(min)+22.5*tCK(avg)+tAC(max)+1nsODT to power down entry latency tANPD3x3x nCKODT power down exit latency tAXPD8x8x nCKOCD drive mode output delay tOIT012012ns32Minimum time clocks remains ON after CKE asynchronously drops LOW tDelaytIS+tCK(avg)+tIHxtIS+tCK(avg)+tIHx ns1514.1 128Mbx8 based 256Mx64 Module (2 Rank)The used device is 128M x8 DDR2 SDRAM, FBGA.DDR2 SDRAM Part NO : K4T1G084QQUnits : Millimeters14.0 Physical Dimensions :- M470T5663QZ(H)33.8 mm 1.1mm maxmax67.60 ± 0.15 mm4.00 ± 0.1020.00 ± 0.15 m m30.00 ± 0.15 m m119911.40 ± 0.15 mm 47.40 ± 0.15 mm6.00 ± 0.15 m m63.00 ± 0.15 mm16.25 ± 0.15 mmmin 2.0067.60 ± 0.15 mm30.00 ± 0.15 m m2200SPDaba4.20 ± 0.152.70 ± 0.104.00 ± 0.101.0 ± 0.051.50 ± 0.10FRONT SIDE 4.20 ± 0.151.80 ± 0.104.00 ± 0.101.0 ± 0.052.40 ± 0.10BACK SIDE0.60 ± 0.150.45 ± 0.032.55 ± 0.150.20 ± 0.15DETAIL a DETAIL bThe used device is 64M x16 DDR2 SDRAM, FBGA.DDR2 SDRAM Part NO : K4T1G164QQUnits : Millimeters67.60 ± 0.15 mm4.00 ± 0.1020.00 ± 0.15 m m30.00 ± 0.15 m m119911.40 ± 0.15 mm 47.40 ± 0.15 mm6.00 ± 0.15 m mS P D3.8 mmMax1.1 mmMaxa 63.00 ± 0.15 mm16.25 ± 0.15 mmmin 2.0067.60 ± 0.15 mm30.00 ± 0.15 m m22004.20 ± 0.152.70 ± 0.104.00 ± 0.101.0 ± 0.051.50 ± 0.10FRONT SIDE 4.20 ± 0.151.80 ± 0.104.00 ± 0.101.0 ± 0.052.40 ± 0.10BACK SIDE0.60 ± 0.150.45 ± 0.032.55 ± 0.150.20 ± 0.15DETAIL a DETAIL bab- M470T2864QZ(H)314.2 64Mbx16 based 128Mx64 Module (2 Rank)The used device is 64M x16 DDR2 SDRAM, FBGA.DDR2 SDRAM Part NO : K4T1G164QQUnits : Millimeters67.60 ± 0.15 mm4.00 ± 0.1020.00 ± 0.15 m m30.00 ± 0.15 m m119911.40 ± 0.15 mm 47.40 ± 0.15 mm6.00 ± 0.15 m mS P Da 63.00 ± 0.15 mm16.25 ± 0.15 mmmin 2.0067.60 ± 0.15 mm30.00 ± 0.15 m m2200a b4.20 ± 0.152.70 ± 0.104.00 ± 0.101.0 ± 0.051.50 ± 0.10FRONT SIDE 4.20 ± 0.151.80 ± 0.104.00 ± 0.101.0 ± 0.052.40 ± 0.10BACK SIDE0.60 ± 0.150.45 ± 0.032.55 ± 0.150.20 ± 0.15DETAIL a DETAIL b3.8 mm Max1.1 mm Max- M470T6464QZ(H)314.3 64Mbx16 based 64Mx64 Module (1 Rank)。

DDR电源芯片文档

DDR再谈－－DDR的几个要点2011-10-26 09:08:22| 分类：Memorizer | 标签：|字号大中小订阅1. 电源DDR的电源可以分为三类：a>主电源VDD和VDDQ，主电源的要求是VDDQ=VDD，VDDQ是给IO buffer供电的电源，VDD是给但是一般的使用中都是把VDDQ 和VDD合成一个电源使用。

有的芯片还有VDDL，是给DLL供电的，也和VDD使用同一电源即可。

电源设计时，需要考虑电压，电流是否满足要求，电源的上电顺序和电源的上电时间，单调性等。

电源电压的要求一般在±5%以内。

电流需要根据使用的不同芯片，及芯片个数等进行计算。

由于DDR的电流一般都比较大，所以PCB设计时，如果有一个完整的电源平面铺到管脚上，是最理想的状态，并且在电源入口加大电容储能，每个管脚上加一个100nF~10nF的小电容滤波。

b>参考电源Vref，参考电源Vref要求跟随VDDQ，并且Vref=VDDQ/2，所以可以使用电源芯片提供，也可以采用电阻分压的方式得到。

由于Vref一般电流较小，在几个mA~几十mA的数量级，所以用电阻分压的方式，即节约成本，又能在布局上比较灵活，放置的离Vref管脚比较近，紧密的跟随VDDQ电压，所以建议使用此种方式。

需要注意分压用的电阻在100~10K均可，需要使用1%精度的电阻。

Vref参考电压的每个管脚上需要加10nF的点容滤波，并且每个分压电阻上也并联一个电容较好。

c>用于匹配的电压VTT(Tracking Termination Voltage)VTT为匹配电阻上拉到的电源，VTT=VDDQ/2。

DDR的设计中，根据拓扑结构的不同，有的设计使用不到VTT，如控制器带的DDR器件比较少的情况下。

如果使用VTT，则VTT的电流要求是比较大的，所以需要走线使用铜皮铺过去。

并且VTT要求电源即可以吸电流，又可以灌电流才可以。

一般情况下可以使用专门为DDR设计的产生VTT的电源芯片来满足要求。

精英主板DDR内存供电分析

Ｓ０一正常，即正常的工作状态，所有设备全开，功耗一般会超过８０Ｗ；
ｓｌ —ＣＰｕ停止工作，也称为ＰＯＳ（ＰｏｗｅｒｏｎＳｕｓｐｅｎｄ），这时除了通过ＣＰＵ时钟控制器将ＣＰＵ关
闭之外，其他的部件仍然正常工作，这时的功耗一般在３０Ｗ以下；ｓ２一ＣＰｕ关闭，这时ＣＰＵ处于停止运作状态，总线时钟也被关闭，但其余的设备仍然运转，Ｓ２状态一般未被实现；
关键词
精英（ＥＣＳ）主板是我校原２３８机房海尔快龙电脑主板，ＣＰＵ是ＩｎｔｅｌＰｅｎｔｉｕｍＩＶ１．５ＧＨｚ，北／南桥
芯片组是ＳＩＳ６５０／ＳＩＳ９６１，支持ＡＣＰＩ１．０规范，内存采用ＤＤＲ内存，ＤＤＲ内存需要２．５Ｖ工作电压和
内存总线终结电路１．２５Ｖ上拉电压，下面以该主板为例，分析兼容ＡＣＰＩ规范的ＤＤＲ内存供电特征。
ｌＡＣＰＩ睡眠状态定义
ＡＣＰＩ是高级配置与电源接口规范（ＡｄｖａｎｃｅｄＣｏｎｉｆｇｕｒａｔｉｏｎａｎｄＰｏｗｅｒＩｎｔｅｒｆａｃｅＳｐｅｃｉｉｆｃａｔｉｏｎ），在ＡＣＰＩ电源管理方式下，根据ＣＰＵ、内存、二级缓存、主控芯片、硬盘等设备挂起时所处的状态不同，它可以支持五种睡眠状态ｓｌ、ｓ２、Ｓ３、Ｓ４和Ｓ５。

内存供电产生原理

内存供电产生原理：
在静态时：sc486即获得了供电+5valw送给第20PIN和第5pin,此时SC486从第8pin生成参考电压dimm-vref0.9V供给内存作为内存的参考电压，同时从第14,15PIN产生+0.9VSUS供给内存和北桥的传输线，作为传输信号线的载体电压。

当EC发出SUS-ON3.3v给sc486的第一pin和第十一pin后，此时sc486从第23脚输出高电平给PQ31的G极，PQ31导通，将主供电导通1.8v给电感PL20充电，同时给PC311，PC312充电，当充满后，sc486发出高电平给pq77,pq78的G极，使pq77,pq78导通，pq31截止，此时充得的电通过PQ77，PQ78后给pc308充电，使pc308另一端的电压超过5v送给sc486的24pin,使sc486内部再次启动，依此循环，不断实现将主供电调节成1.8VSUS给内存供电，当供电完成后，SC486从第7pin生成DDR2_PWRGD 3.3v给EC，告诉ec内存供电产生完毕。

ddr2测试规范

DDR2 SDRAM接口硬件测试规范目录DDR2 SDRAM接口硬件测试规范 (I)1 范围 (3)2 术语和定义 (3)3 缩略语 (3)4 测试仪器仪表清单 (4)5 接口说明 (4)5.1 SDRAM接口信号说明 (4)5.2 DDR2 SDRAM接口功能指标 (5)5.2.1 电源完整性需要测试以下指标 (6)5.2.2 信号完整性需要测试以下指标 (7)5.2.3 时序需要测试以下指标 (7)5.2.4 时钟信号需要测试以下指标 (8)5.3 DDR2 SDRAM参数测试说明 (9)5.3.1 DDR2 SDRAM读写区分的方法 (9)5.3.2 单端信号AC输入参数测量 (11)5.3.2.1 VSWING(MAX)的测试方法 (11)5.3.2.2 SlewR参数测量方法 (12)5.3.2.3 SlewF参数的测量方法 (13)5.3.2.4 VIH的测试方法 (14)5.3.2.5 VIL的测试方法 (15)5.3.2.6 tDIPW的测试方法 (15)5.3.2.7 tIPW的测试方法 (15)5.3.3 输入信号过冲欠冲测试 (16)5.3.3.1 信号过冲测试方法 (16)5.3.3.2 信号欠冲测试方法 (17)5.3.4 差分信号AC参数测量 (17)5.3.4.1 SlewR测试方法 (17)5.3.4.2 SlewF测试方法 (18)5.3.4.3 VID测试方法 (19)5.3.4.4 VIX测试方法 (20)5.3.4.5 VOX的测试方法 (21)5.3.4.6 tDQSH的测试方法 (22)5.3.4.7 tDQSL的测试方法 (23)5.3.5 控制和地址信号时序测试 (24)5.3.5.1 tIS(base)测试方法 (24)5.3.5.2 tIH(base)测试方法 (26)5.3.6 数据信号时序测试 (26)5.3.6.1 tDS(base)测试方法 (26)5.3.6.2 tDH(base)测试方法 (27)5.3.6.3 tDS1(base)测试方法 (28)5.3.6.4 tDH1(base)测试方法 (30)5.3.6.5 tAC的测试方法 (32)5.3.6.6 tDQSCK的测试方法 (33)5.3.6.7 tDQSQ的测试方法 (34)5.3.6.8 tQH的测试方法 (35)5.3.6.9 tDQSS的测试方法 (36)5.3.6.10 tDSS的测试方法 (37)5.3.6.11 tDSH的测试方法 (38)5.3.6.12 tHZ的测试方法 (39)5.3.6.13 tLZ的测试方法 (40)5.3.6.14 tRPRE的测试方法 (42)5.3.6.15 tRPST的测试方法 (43)5.3.6.16 tWPRE的测试方法 (44)5.3.6.17 tWPST的测试方法 (45)5.3.7 时钟信号测试 (46)5.3.7.1 tCK(avg)的测试方法 (46)5.3.7.2 tCH(avg)/ tCL(avg)的测试方法 (47)5.3.7.3 Tj、Dj和Rj的测试方法 (47)5.3.7.4 tJIT(per)的测试方法 (48)5.3.7.5 tJIT(cc)的测试方法 (48)5.3.7.6 tJIT(duty)的测试方法 (49)5.3.7.7 tERR(nper)的测试方法 (49)6 测试内容 (50)6.1 电源完整性测试 (50)6.1.1.1 HS-DDR2 SDRAM-P-001 电源精度测试 (50)6.1.1.2 HS-DDR2 SDRAM-P-002 电源纹波测试 (51)6.1.1.3 HS-DDR2 SDRAM-P-003 电源上电波形测试 (53)6.1.1.4 HS-DDR2 SDRAM-P-003 电源上电时序测试 (53)6.2 信号完整性和时序测试 (54)6.2.1.1 HS-DDR2 SDRAM-S-001控制信号完整性测试 (54)6.2.1.2 HS-DDR2 SDRAM-S-002地址信号完整性测试 (55)6.2.1.3 HS-DDR2 SDRAM-S-003读操作数据信号完整性测试 (56)6.2.1.4 HS-DDR2 SDRAM-S-004写操作数据信号完整性测试 (56)6.3 时序测试 (58)6.3.1.1 HS-DDR2 SDRAM-T-001 读操作数据信号时序测试 (58)6.3.1.2 HS-DDR2 SDRAM-T-002 写操作数据信号时序测试 (59)6.3.1.3 HS-DDR2 SDRAM-T-003 控制信号时序测试 (60)6.3.1.4 HS-DDR2 SDRAM-T-004 地址信号时序测试 (60)6.4 时钟信号测试 (61)6.4.1.1 HS-DDR2 SDRAM-C-001 时钟信号波形测试 (61)6.4.1.2 HS-DDR2 SDRAM-C-002 时钟Jitter测试 (62)6.4.1.3 HS-DDR2 SDRAM-C-003 时钟精度测试 (63)7 引用 (63)1 范围本标准规定了DDR2 SDRAM接口的硬件测试方法和相关测试注意事项，并结合测试示例给以说明。

DDR及DDR2内存供电电路

DDR内存供电电路
DDR内存需要两种供电电压:2.5V的主供电压和1.25的基准供电电压(又称参考电压).2.5V 供电电压用来为内存芯片提供工作电压,1.25V供电电压用来为内存总线的数据线和地址线提供上拉工作电压.DDR内存供电电路主要有下面几种形式.
1\单场效应管60N03+基准电压源LM431(可以用XX431代换)+比较器LM358构成的2.5V供电电路.
2\单场效应管Q110+基准电压源Q31(SC431\SOT-23)构成的2.5V供电电路
3\专用芯片(ISL6520\RT9214)构成的2.5V内存供电电路
4\双场效应管Q71(15N03)和Q70(15N03)+比较器U42A(LM358)和U42B(LM358)构成的1.25V供电电路
5\双三极管Q4(HA8050D-D)\Q5(HA8550D-D)+比较器构成的1.25V供电电路
6\多端稳压器(RT9173或RT9173B)构成的1.25V供电电中路
7\专用芯片LP2995构成的1.25V供电电路
8\专用芯片ISL6537构成的混合型内存供电电路
DDR2内存需要两种供电电压:1.8V的主供电电压和0.9V的基准电电压(又称参考电压),1.8V 供电电压来为内存芯片提供工作电压,0.9V供电电压用来为内存总线的数据线和地址线提供上拉工作电压.
常用DDR2内存供电芯片有NCP5201\ISL6537等型号。

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