Two-stage_design_example_清华大学模拟集成电路分析与设计

scalegm1 :=
fc
fcaccurate
scalegm1 = 1.134
scalePM := PM − PMaccurate scalePM = 3.08 deg
Re-calculate transconductances
gm1 :=
1 β
⋅2⋅π
⋅fc⋅Cc⋅
scalegm1
k
:=
tan⎛⎜⎝π⋅
⎞ ⎠
⋅⎛⎜ ⎝
1
−
s p2
⎞⋅ ⎠
⎛⎜1 ⎝
−
s⎞ p3 ⎠
( ( )) PMaccurate := 180deg + arg T j⋅2⋅π⋅fc
fx := fc Given
( ) T j⋅2⋅π⋅fx = 1
( ) fcaccurate := Find fx
PMaccurate = 69.92 deg fcaccurate = 132.289 MHz
Cc
+
2⋅β)
Calculate compensation capacitor
Cc
:=
2⋅2
1 β
⋅
kB⋅Tr ⋅γ⋅(1
Ntot
+
2⋅β)
Cc = 488.831 fF
Static error spec:
avo :=
1 ε s⋅ β
avo = 724
β⋅avo = 200
For simplicity, assume that each stage contributes same gain, and that each device M1...M4 is designed for same intrinsic gain. Intrinsic gain in each device is must then be larger than
Normalize all caps, so that optimization engine does not need to deal with extremely small quantities (this seems to be an issue in MathCAD)
Cnorm := 1fF
ID2 :=
gm2 gmID2
gmID1 =
5.089
1 V
gmID2 =
1 10.813
V
ID1 = 371.585 µA ID2 = 530.233 µA
ID1 + ID2 = 901.818 µA
Current densities and device widths (using look-up table)
( ) ( ) IDW1 := pidw L1 , gmID1
IDW2 := nidw L2 , gmID2
IDW1
=
6.017
A m
IDW2
=
5.054
A m
W1 :=
ID1 IDW1
W2 :=
ID2 IDW2
W1 = 47.188 µm W2 = 72.126 µm
Refinement
We could now simulate this design in Spice and resolve discrepancies (due to approximations) through a few iterations and "educated tweaking". Alternatively, it is possible to improve the design accuracy by performing one more corrective iteration using more accurate equations:
ID1 :=
gm1 gmID1
ID2 :=
gm2 gmID2
gmID1
=
5.874
1 V
gmID2
=
12.75
1 V
ID1 = 283.936 µA ID2 = 364.529 µA
ID1 + ID2 = 648.465 µA
Current densities and device widths (using look-up table)
Noise requirement
Approximate noise equation (assumes gm2>>gm1, and gm(load) = gm(active).
Ntot :=
0.5⋅Vodmax2 DR
10 10
Ntot = 355.234 µV
Ntot
=
2⋅2
1 β
⋅
kB⋅Tr ⋅γ⋅(1
Cj1 := (1 + 0.5)⋅0.8Cgg1 Cj2 := (1 + 1)⋅0.8Cgg2 C1 := Cj1 + Cgg2
C2 := CL + Cj2 + (1 − β)⋅Cf
Cj1 = 148.8 fF Cj2 = 222.72 fF C1 = 288 fF C2 = 767.471 fF
Total stage 1 load Total stage 2 load
fT1 = 2.427 GHz fT2 = 6.555 GHz
gm/ID to meet fT values above (using look-up table)
( ) ( ) gmID1 := pgmid L1 , fT1 gmID2 := ngmid L2 , fT2
ID1 :=
gm1 gmID1
⋅γ⋅(1
+
2⋅β)⋅
1 Cnorm
gm1
←
1.15
1 β
⋅2⋅π⋅fc⋅Cc⋅Cnorm
Cj1 ← (1 + 0.5)⋅0.8Cgg1
Cj2 ← (1 + 1)⋅0.8Cgg2
CLtot ← CL + Cj2 + (1 − β)⋅Cf
k
←
tan⎛⎜⎝π⋅
PM + 3deg 180deg
⎞ ⎠
( ) gm2
( ) ( ) IDW1 := pidw L1 , gmID1
IDW2 := nidw L2 , gmID2
IDW1
=
7.876
A m
W1 :=
ID1 IDW1
W2 :=
ID2 IDW2
W1 = 47.18 µm
IDW2
=
7.416
A m
W2 = 71.497 µm
Find best design choice using optimization function
Cgg1 := 0.31⋅Cs DESIGN CHOICE 1: Cgg usually comparable to Cs
Return factor
β :=
Cf
Cf + Cs + Cgg1
β = 0.276
Hale Waihona Puke Cgg2 := 0.348⋅CL DESIGN CHOICE 2: Cgg2 usually comparable to CL
←
⎡ k⋅2⋅π⋅fc⋅⎢
CLtot⋅
⎣
Cgg2 Cc
+
Cj1
⎤ + Cgg2 + Cj1 + CLtot⎥⋅Cnorm
⎦
fT1
←
1 ⋅ gm1 2⋅π Cgg1⋅Cnorm
fT2
←
1 ⋅ gm2 2⋅π Cgg2⋅Cnorm
( ) ( ) gmID1 ← if ⎛⎜⎝pgmid L1 , fT1
>
fT1 :=
1 ⋅ gm1 2⋅π Cgg1
fT2 :=
1 ⋅ gm2 2⋅π Cgg2
fT1 = 2.141 GHz fT2 = 5.314 GHz
gm/ID to meet fT values above (using look-up table)
( ) ( ) gmID1 := pgmid L1 , fT1 gmID2 := ngmid L2 , fT2
2-Stage OTA Design Example (Small-Signal)
Cf
Cs
+
Vsd
Vid
-
Cs
Cf
Given parameters and specs
Cs := 400fF fc := 150MHz
Cf := 200fF PM := 73deg
CL := 400fF εs := 0.5%
Given Cgg1 > 0
Cgg2 > 0
( ) Copt := Minimize f, Cgg1 , Cgg2
Copt
=
⎛⎜⎝
123.885 139.245
⎞ ⎠
f⎛⎝Copt0, Copt1⎞⎠ = 907.545 µA
Junction capacitance estimates at 1st/2nd stage output. Cj is approximately equal to Cgg. Assume Stage 1 loads (NMOS) are half as wide as diff pair devices (PMOS); assume 2nd stage loads (PMOS) have same width as CS devices (NMOS)
Estimate transconductances
gm1 :=
1 β