Two-stage_design_example_清华大学模拟集成电路分析与设计
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Cc
+
2⋅β)
Calculate compensation capacitor
Cc
:=
2⋅2
1 β
⋅
kB⋅Tr ⋅γ⋅(1
Ntot
+
2⋅β)
Cc = 488.831 fF
Static error spec:
avo :=
1 ε s⋅ β
avo = 724
β⋅avo = 200
For simplicity, assume that each stage contributes same gain, and that each device M1...M4 is designed for same intrinsic gain. Intrinsic gain in each device is must then be larger than
Cj1 := (1 + 0.5)⋅0.8Cgg1 Cj2 := (1 + 1)⋅0.8Cgg2 C1 := Cj1 + Cgg2
C2 := CL + Cj2 + (1 − β)⋅Cf
Cj1 = 148.8 fF Cj2 = 222.72 fF C1 = 288 fF C2 = 767.471 fF
Total stage 1 load Total stage 2 load
ID1 :=
gm1 gmID1
ID2 :=
gm2 gmID2
gmID1
=
5.874
1 V
gmID2
=
12.75
1 V
ID1 = 283.936 µA ID2 = 364.529 µA
ID1 + ID2 = 648.465 µA
Current densities and device widths (using look-up table)
Junction capacitance estimates at 1st/2nd stage output. Cj is approximately equal to Cgg. Assume Stage 1 loads (NMOS) are half as wide as diff pair devices (PMOS); assume 2nd stage loads (PMOS) have same width as CS devices (NMOS)
←
⎡ k⋅2⋅π⋅fc⋅⎢
CLtot⋅
⎣
Cgg2 Cc
+
Cj1
⎤ + Cgg2 + Cj1 + CLtot⎥⋅Cnorm
⎦
fT1
←
1 ⋅ gm1 2⋅π Cgg1⋅Cnorm
fT2
←
1 ⋅ gm2 2⋅π Cgg2⋅Cnorm
( ) ( ) gmID1 ← if ⎛⎜⎝pgmid L1 , fT1
>
⋅γ⋅(1
+
2⋅β)⋅
1 Cnorm
gm1
←
1.15
1 β
⋅2⋅π⋅fc⋅Cc⋅Cnorm
Cj1 ← (1 + 0.5)⋅0.8Cgg1
Cj2 ← (1 + 1)⋅0.8Cgg2
CLtot ← CL + Cj2 + (1 − β)⋅Cf
k
←
tan⎛⎜⎝π⋅
PM + 3deg 180deg
⎞ ⎠
( ) gm2
Estimate transconductances
gm1 :=
1 β
⋅2⋅π⋅fc⋅Cc
k
:=
tan⎛⎜⎝π⋅
PM 180deg
⎞ ⎠
k = 3.271
gm2 :=
k⋅2⋅π
⎛ ⋅fc⋅⎜
⎝
C2⋅C1 Cc
+
C1
+
⎞
C2
⎠
gm1 = 1.668 mS gm2 = 4.648 mS
Transit frequencies
2 avo = 53.814
L1 := 0.55µm L2 := 0.4µm
DESIGN CHOICE 3: Length of PMOS device in first stage DESIGN CHOICE 4: Length of NMOS device in second stage
Circuit Parameter Calculations
R1 :=
avo gm1
R2 :=
avo gm2
( ) ( ) p1 := − C2 + Cc R2 +
C1
+
1 Cc
⋅R1
+
gm2⋅R2⋅R1⋅Ccp2
:=
− C1⋅C2
gm2⋅Cc + Cc⋅C2 +
Cc⋅C1
p3
:=
− gm2 C1
T(s) := β⋅
gm1⋅R1⋅gm2⋅R2
⎛⎜1 ⎝
−
s p1
Noise requirement
Approximate noise equation (assumes gm2>>gm1, and gm(load) = gm(active).
Ntot :=
0.5⋅Vodmax2 DR
10 10
Ntot = 355.234 µV
Ntot
=
2⋅2
1 β
⋅
kB⋅Tr ⋅γ⋅(1
Reference:C:\Documents and Settings\Murmann\My Documents\lib\Mathcad\defaults.mcd Reference:C:\Documents and Settings\Murmann\My Documents\teaching\ee214_autumn05\project\gmidda
Normalize all caps, so that optimization engine does not need to deal with extremely small quantities (this seems to be an issue in MathCAD)
Cnorm := 1fF
fT1 = 2.427 GHz fT2 = 6.555 GHz
gm/ID to meet fT values above (using look-up table)
( ) ( ) gmID1 := pgmid L1 , fT1 gmID2 := ngmid L2 , fT2
ID1 :=
gm1 gmID1
⎞ ⎠
⋅⎛⎜ ⎝
1
−
s p2
⎞⋅ ⎠
⎛⎜1 ⎝
−
s⎞ p3 ⎠
( ( )) PMaccurate := 180deg + arg T j⋅2⋅π⋅fc
fx := fc Given
( ) T j⋅2⋅π⋅fx = 1
( ) fcaccurate := Find fx
PMaccurate = 69.92 deg fcaccurate = 132.289 MHz
( ) ( ) IDW1 := pidw L1 , gmID1
IDW2 := nidw L2 , gmID2
IDW1
=
7.876
A m
W1 :=
ID1 IDW1
W2 :=
ID2 IDW2
W1 = 47.18 µm
IDW2
=
7.416
A m
W2 = 71.497 µm
Find best design choice using optimization function
scalegm1 :=
fc
fcaccurate
scalegm1 = 1.134
scalePM := PM − PMaccurate scalePM = 3.08 deg
Re-calculate transconductances
gm1 :=
1 β
⋅2⋅π
⋅fc⋅Cc⋅
scalegm1
k
:=
tan⎛⎜⎝π⋅
CL
+ Vod
-
CL
DR := 72 (dB) VDD := 3V
γ := 2 3
Chosen architecture (Miller compensation, neutralization caps and CMFB not shown)
M1a,b
M4a,b
M3a,b
M2a,b
Design Choices
2-Stage OTA Design Example (Small-Signal)
Cf
Cs
+
Vsd
Vid
-
Cs
Cf
Given parameters and specs
Cs := 400fF fc := 150MHz
Cf := 200fF PM := 73deg
CL := 400fF εs := 0.5%
ID2 :=
gm2 gmID2
gmID1 =
5.089
1 V
gmID2 =
1 10.813
V
ID1 = 371.585 µA ID2 = 530.233 µA
ID1 + ID2 = 901.818 µA
Current densities and device widths (using look-up table)
fT1 :=
1 ⋅ gm1 2⋅π Cgg1
fT2 :=
1 ⋅ gm2 2⋅π Cgg2
fT1 = 2.141 GHz fT2 = 5.314 GHz
gm/ID to meet fT values above (using look-up table)
( ) ( ) gmID1 := pgmid L1 , fT1 gmID2 := ngmid L2 , fT2
5⋅ 1 , pgmid V
L1 , fT1
, 0.1⋅ 1 ⎞ V⎠
( ) ( ) gmID2 ← if ⎛⎜⎝ngmid L2 , fT2
>
5⋅ 1 , ngmid V
L2 , fT2
, 0.1⋅ 1 ⎞ V⎠
gm1 + gm2 gmID1 gmID2
(Cost function = sum of transconductor currents)
PM + scalePM ⎞ 180deg ⎠
k = 4.035
gm2 :=
k⋅2⋅
π⋅fc⋅
⎛ ⎜ ⎝
C2⋅C1 Cc
+
C1
+
⎞
C2
⎠
gm1 = 1.891 mS gm2 = 5.733 mS
Transit frequencies
fT1 :=
1 ⋅ gm1 2⋅π Cgg1
fT2 :=
1 ⋅ gm2 2⋅π Cgg2
Cs :=
Cs Cnorm
Initial guess for optimization
Cf :=
Cf Cnorm
CL :=
CL Cnorm
Cgg1 := 1⋅Cs
Cgg2 := 1⋅CL
( ) f Cgg1 , Байду номын сангаасgg2 :=
β←
Cf
Cf + Cs + Cgg1
Cc
←
2⋅2
1 β
⋅
kB⋅Tr Ntot
Cgg1 := 0.31⋅Cs DESIGN CHOICE 1: Cgg usually comparable to Cs
Return factor
β :=
Cf
Cf + Cs + Cgg1
β = 0.276
Cgg2 := 0.348⋅CL DESIGN CHOICE 2: Cgg2 usually comparable to CL
PM short by a few degrees (due to third pole), fc is off by >10% due to neglecting second order terms in dominant pole expression & impact of nondominant poles on fc.
Given Cgg1 > 0
Cgg2 > 0
( ) Copt := Minimize f, Cgg1 , Cgg2
Copt
=
⎛⎜⎝
123.885 139.245
⎞ ⎠
f⎛⎝Copt0, Copt1⎞⎠ = 907.545 µA
Cgg1 = 124 fF Cgg2 = 139.2 fF
Dynamic range considerations:
Vdsmin guess for NMOS and PMOS output device
VDSmin := 500mV
Differential peak amplitude
Vodmax := VDD − 2⋅VDSmin
( ) ( ) IDW1 := pidw L1 , gmID1
IDW2 := nidw L2 , gmID2
IDW1
=
6.017
A m
IDW2
=
5.054
A m
W1 :=
ID1 IDW1
W2 :=
ID2 IDW2
W1 = 47.188 µm W2 = 72.126 µm
Refinement
We could now simulate this design in Spice and resolve discrepancies (due to approximations) through a few iterations and "educated tweaking". Alternatively, it is possible to improve the design accuracy by performing one more corrective iteration using more accurate equations:
+
2⋅β)
Calculate compensation capacitor
Cc
:=
2⋅2
1 β
⋅
kB⋅Tr ⋅γ⋅(1
Ntot
+
2⋅β)
Cc = 488.831 fF
Static error spec:
avo :=
1 ε s⋅ β
avo = 724
β⋅avo = 200
For simplicity, assume that each stage contributes same gain, and that each device M1...M4 is designed for same intrinsic gain. Intrinsic gain in each device is must then be larger than
Cj1 := (1 + 0.5)⋅0.8Cgg1 Cj2 := (1 + 1)⋅0.8Cgg2 C1 := Cj1 + Cgg2
C2 := CL + Cj2 + (1 − β)⋅Cf
Cj1 = 148.8 fF Cj2 = 222.72 fF C1 = 288 fF C2 = 767.471 fF
Total stage 1 load Total stage 2 load
ID1 :=
gm1 gmID1
ID2 :=
gm2 gmID2
gmID1
=
5.874
1 V
gmID2
=
12.75
1 V
ID1 = 283.936 µA ID2 = 364.529 µA
ID1 + ID2 = 648.465 µA
Current densities and device widths (using look-up table)
Junction capacitance estimates at 1st/2nd stage output. Cj is approximately equal to Cgg. Assume Stage 1 loads (NMOS) are half as wide as diff pair devices (PMOS); assume 2nd stage loads (PMOS) have same width as CS devices (NMOS)
←
⎡ k⋅2⋅π⋅fc⋅⎢
CLtot⋅
⎣
Cgg2 Cc
+
Cj1
⎤ + Cgg2 + Cj1 + CLtot⎥⋅Cnorm
⎦
fT1
←
1 ⋅ gm1 2⋅π Cgg1⋅Cnorm
fT2
←
1 ⋅ gm2 2⋅π Cgg2⋅Cnorm
( ) ( ) gmID1 ← if ⎛⎜⎝pgmid L1 , fT1
>
⋅γ⋅(1
+
2⋅β)⋅
1 Cnorm
gm1
←
1.15
1 β
⋅2⋅π⋅fc⋅Cc⋅Cnorm
Cj1 ← (1 + 0.5)⋅0.8Cgg1
Cj2 ← (1 + 1)⋅0.8Cgg2
CLtot ← CL + Cj2 + (1 − β)⋅Cf
k
←
tan⎛⎜⎝π⋅
PM + 3deg 180deg
⎞ ⎠
( ) gm2
Estimate transconductances
gm1 :=
1 β
⋅2⋅π⋅fc⋅Cc
k
:=
tan⎛⎜⎝π⋅
PM 180deg
⎞ ⎠
k = 3.271
gm2 :=
k⋅2⋅π
⎛ ⋅fc⋅⎜
⎝
C2⋅C1 Cc
+
C1
+
⎞
C2
⎠
gm1 = 1.668 mS gm2 = 4.648 mS
Transit frequencies
2 avo = 53.814
L1 := 0.55µm L2 := 0.4µm
DESIGN CHOICE 3: Length of PMOS device in first stage DESIGN CHOICE 4: Length of NMOS device in second stage
Circuit Parameter Calculations
R1 :=
avo gm1
R2 :=
avo gm2
( ) ( ) p1 := − C2 + Cc R2 +
C1
+
1 Cc
⋅R1
+
gm2⋅R2⋅R1⋅Ccp2
:=
− C1⋅C2
gm2⋅Cc + Cc⋅C2 +
Cc⋅C1
p3
:=
− gm2 C1
T(s) := β⋅
gm1⋅R1⋅gm2⋅R2
⎛⎜1 ⎝
−
s p1
Noise requirement
Approximate noise equation (assumes gm2>>gm1, and gm(load) = gm(active).
Ntot :=
0.5⋅Vodmax2 DR
10 10
Ntot = 355.234 µV
Ntot
=
2⋅2
1 β
⋅
kB⋅Tr ⋅γ⋅(1
Reference:C:\Documents and Settings\Murmann\My Documents\lib\Mathcad\defaults.mcd Reference:C:\Documents and Settings\Murmann\My Documents\teaching\ee214_autumn05\project\gmidda
Normalize all caps, so that optimization engine does not need to deal with extremely small quantities (this seems to be an issue in MathCAD)
Cnorm := 1fF
fT1 = 2.427 GHz fT2 = 6.555 GHz
gm/ID to meet fT values above (using look-up table)
( ) ( ) gmID1 := pgmid L1 , fT1 gmID2 := ngmid L2 , fT2
ID1 :=
gm1 gmID1
⎞ ⎠
⋅⎛⎜ ⎝
1
−
s p2
⎞⋅ ⎠
⎛⎜1 ⎝
−
s⎞ p3 ⎠
( ( )) PMaccurate := 180deg + arg T j⋅2⋅π⋅fc
fx := fc Given
( ) T j⋅2⋅π⋅fx = 1
( ) fcaccurate := Find fx
PMaccurate = 69.92 deg fcaccurate = 132.289 MHz
( ) ( ) IDW1 := pidw L1 , gmID1
IDW2 := nidw L2 , gmID2
IDW1
=
7.876
A m
W1 :=
ID1 IDW1
W2 :=
ID2 IDW2
W1 = 47.18 µm
IDW2
=
7.416
A m
W2 = 71.497 µm
Find best design choice using optimization function
scalegm1 :=
fc
fcaccurate
scalegm1 = 1.134
scalePM := PM − PMaccurate scalePM = 3.08 deg
Re-calculate transconductances
gm1 :=
1 β
⋅2⋅π
⋅fc⋅Cc⋅
scalegm1
k
:=
tan⎛⎜⎝π⋅
CL
+ Vod
-
CL
DR := 72 (dB) VDD := 3V
γ := 2 3
Chosen architecture (Miller compensation, neutralization caps and CMFB not shown)
M1a,b
M4a,b
M3a,b
M2a,b
Design Choices
2-Stage OTA Design Example (Small-Signal)
Cf
Cs
+
Vsd
Vid
-
Cs
Cf
Given parameters and specs
Cs := 400fF fc := 150MHz
Cf := 200fF PM := 73deg
CL := 400fF εs := 0.5%
ID2 :=
gm2 gmID2
gmID1 =
5.089
1 V
gmID2 =
1 10.813
V
ID1 = 371.585 µA ID2 = 530.233 µA
ID1 + ID2 = 901.818 µA
Current densities and device widths (using look-up table)
fT1 :=
1 ⋅ gm1 2⋅π Cgg1
fT2 :=
1 ⋅ gm2 2⋅π Cgg2
fT1 = 2.141 GHz fT2 = 5.314 GHz
gm/ID to meet fT values above (using look-up table)
( ) ( ) gmID1 := pgmid L1 , fT1 gmID2 := ngmid L2 , fT2
5⋅ 1 , pgmid V
L1 , fT1
, 0.1⋅ 1 ⎞ V⎠
( ) ( ) gmID2 ← if ⎛⎜⎝ngmid L2 , fT2
>
5⋅ 1 , ngmid V
L2 , fT2
, 0.1⋅ 1 ⎞ V⎠
gm1 + gm2 gmID1 gmID2
(Cost function = sum of transconductor currents)
PM + scalePM ⎞ 180deg ⎠
k = 4.035
gm2 :=
k⋅2⋅
π⋅fc⋅
⎛ ⎜ ⎝
C2⋅C1 Cc
+
C1
+
⎞
C2
⎠
gm1 = 1.891 mS gm2 = 5.733 mS
Transit frequencies
fT1 :=
1 ⋅ gm1 2⋅π Cgg1
fT2 :=
1 ⋅ gm2 2⋅π Cgg2
Cs :=
Cs Cnorm
Initial guess for optimization
Cf :=
Cf Cnorm
CL :=
CL Cnorm
Cgg1 := 1⋅Cs
Cgg2 := 1⋅CL
( ) f Cgg1 , Байду номын сангаасgg2 :=
β←
Cf
Cf + Cs + Cgg1
Cc
←
2⋅2
1 β
⋅
kB⋅Tr Ntot
Cgg1 := 0.31⋅Cs DESIGN CHOICE 1: Cgg usually comparable to Cs
Return factor
β :=
Cf
Cf + Cs + Cgg1
β = 0.276
Cgg2 := 0.348⋅CL DESIGN CHOICE 2: Cgg2 usually comparable to CL
PM short by a few degrees (due to third pole), fc is off by >10% due to neglecting second order terms in dominant pole expression & impact of nondominant poles on fc.
Given Cgg1 > 0
Cgg2 > 0
( ) Copt := Minimize f, Cgg1 , Cgg2
Copt
=
⎛⎜⎝
123.885 139.245
⎞ ⎠
f⎛⎝Copt0, Copt1⎞⎠ = 907.545 µA
Cgg1 = 124 fF Cgg2 = 139.2 fF
Dynamic range considerations:
Vdsmin guess for NMOS and PMOS output device
VDSmin := 500mV
Differential peak amplitude
Vodmax := VDD − 2⋅VDSmin
( ) ( ) IDW1 := pidw L1 , gmID1
IDW2 := nidw L2 , gmID2
IDW1
=
6.017
A m
IDW2
=
5.054
A m
W1 :=
ID1 IDW1
W2 :=
ID2 IDW2
W1 = 47.188 µm W2 = 72.126 µm
Refinement
We could now simulate this design in Spice and resolve discrepancies (due to approximations) through a few iterations and "educated tweaking". Alternatively, it is possible to improve the design accuracy by performing one more corrective iteration using more accurate equations: