DC脚本及解释

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DC脚本说明

下面对usb_dma模块的DC脚本进行说明。

set search_path "./rtl" 设置搜索路径，即寻找库的路径。

source ./script/lib_link.path source是把script 下的lib_link.path文件链接到此处，设置链接路径，文件里面是综合用到的的库的路径。

source ./script/dont_use.tcl dont_use.tcl文件是综合时不希望用到的元件的信息，如RS触发器和JK触发器等，与做APR的人员商量得到，目的是使用合适的器件，提高流片成功率。

read_verilog 读入代码。

读入代码的时候要先读入子模块的代码，最后读入顶层。

Link 报告链接信息，若有些库或者代码没找到会报错。

check_design 检查design中的悬空管脚、短接等情况。

主要关注其中的没有输入驱动（no_drivers）、loop和tied to的情况。

set_wire_load_model 选择连线负载模型，由工艺库中的连线模型得到。

命令区别于set_wire_load_mode，mode一共有三种，分别是top、enclosed、segmented三种。

set compile_segmap_propagate_constants false 把输入端接固定电平的触发器当做固定电平而不看作触发器处理。

set uload 设置标准负载，具体为哪一个，由后面的决定。

一般选择与非门的输出引脚。

set_load [expr 10*$uload] [all_outputs] 给所有的输出端设置负载，负载值为标准负载的10倍。

set_driving_cell 设置输入驱动，一般选择反相器。

set_fix_multiple_port_nets -feedthroughs -outputs -constants -buffer –constants 给所有纯组合逻辑的路径（输入到输出都是组合逻辑）的输出端加buffer，以增强驱动能力。

dc综合自带宏定义

dc综合自带宏定义DC综合自带宏定义DC综合自带宏定义是指在DC综合工具中默认提供的一系列宏定义，用于实现功能复杂的设计。

宏定义是一种预编译指令，可以在编译过程中替换为特定的代码或表达式。

DC综合自带宏定义为我们提供了一些常用的功能实现，方便我们在设计中使用。

一、常用的DC综合自带宏定义1. `define`define是DC综合中定义宏的关键字，通过`define我们可以定义一些常量或者函数，用于简化代码的编写和维护。

例如，我们可以使用`define定义一个常量：`define WIDTH 8定义了一个名为WIDTH的宏，它的值为8。

在后续的代码中，我们可以直接使用WIDTH来代替8，使得代码更加简洁易读。

2. `ifdef和`endif`ifdef是DC综合中的条件编译指令，用于判断某个宏是否被定义。

例如，我们可以使用`ifdef来判断一个宏是否被定义：`ifdef DEBUG// 调试模式下的代码`else// 正常模式下的代码`endif如果宏DEBUG被定义，则执行调试模式下的代码；否则执行正常模式下的代码。

通过使用`ifdef和`endif，我们可以根据需要选择性地编译某些代码，提高代码的灵活性和可维护性。

3. `include`include是DC综合中的包含文件指令，用于将其他文件中的代码包含到当前文件中。

例如，我们可以使用`include包含一个名为test.v的文件：`include "test.v"通过使用`include，我们可以将一些通用的代码放在单独的文件中，然后在需要的地方进行包含，避免代码的重复编写，提高代码的复用性和可读性。

二、DC综合自带宏定义的应用DC综合自带宏定义在实际设计中有着广泛的应用。

下面以一个简单的例子来说明宏定义的使用。

假设我们需要设计一个8位加法器，可以将两个8位的输入相加得到一个8位的输出。

我们可以使用DC综合自带宏定义来实现这个功能。

DC简单使用

综合概述综合主要包括三个阶段：转换(translation)、优化(optimization)与映射(mapping)。

转换阶段综合工具将高层语言描述的电路用门级的逻辑来实现，对于Synopsys的综合工具DC来说，就是使用gtech.db1库中的门级单元来组成HDL语言描述的电路，从而构成初始的未优化的电路。

优化与映射是综合工具对已有的初始电路进行分析，去掉电路中的冗余单元，并对不满足限制条件的路径进行优化，然后将优化之后的电路映射到由制造商提供的工艺库上。

必须的限制条件1)电路中需要有时钟的定义.2)保留时钟网络,不对时钟网络做综合.3)综合的时候需要指定线负载模型,用于估计连线延迟.4)限制模块中组合路径的输入输出延迟.5)限制输出的带负载能力(Loading budget)以及输入的驱动单元(drivingcell)6)模块同步输出的输出延迟(output delay)的限制,以及同步输入的输入延迟(input delay)的限制.7)多周期路径(multicycle path)以及非法路径(false path)的限制8)工作环境的给定综合的准备设计文件自下而上式的编译目录结构综合划分（Partitioning for Synthesis）采取的策略：z方便设计重用（Partition for design reuse）z保证相关的组合逻辑一起（Keep related combinational logic together）z确保块输出为寄存器（Registering block outputs）z按设计目标划分（Partition by design goal）z按编译技术划分（Partition by compile technique）z保证共享的资源在一起（Keep sharable resources together）z Keep user-defined resources with the logic they drive.z隔离特殊的功能，例如pads，时钟，边界扫描和异步逻辑（Isolate special functions，such as pads，clocks，boundary scans，and asynchronous logic）综合划分技术库技术库包含了半导体厂商提供的每个单元的特征和功能的信息。

DC Design Compiler 综合脚本命令及参考模板

DC Design Compiler 综合脚本命令及参考模板Design Compiler 综合脚本常用命令和模板参照自己的设计，以及自己的工艺信息，适当修改下面的Constraints 和 Run Script 等的脚本，添加一些相关的约束语句，就可以运行了详细的命令请参照DC的官方User Guide等相关资料。

Invoking Design CompilerUnix% design_vision # Interactive GUI, WLM mode Unix%design_vision –topographical # Interactive GUI, Topographical mode Unix% dc_shell-t # Interactive shell, WLM mode Unix% dc_shell-t –topographical # Interactive shell, Topographical mode Unix% dc_shell-t –f RUN.tcl | tee –i my.log # Batch mode.synopsys_dc.setupset search_path “$search_path libs cons unmapped rtl”set synthetic_library dw_foundation.sldbset target_library 65nm.dbset link_library “* $target_library $synthetic_library IP.db”set symbol_library 65nm.sdbdefine_design_lib WORK –path ./workset_svf <my_filename.svf>set_vsdc <my_filename.vsdc>history keep 200set sh_enable_page_mode falseset cache_write .set cache_read $cache_writesuppress_message {LINT-28 LINT-32 LINT-33 UID-401} setalib_library_analysis_path [get_unix_variable HOME] alias h history alias rc “report_constraint -all_violators”TCL Commands and Constructsset PER 2.0 # Define a variable and its value echo $PER # Variable substitution , 2.0set MARG 0.95expr $PER * $MARG # expr: *, /, +, -, >, <, =, <=, >=set pci_ports [get_ports A] # Imbedded command set pci_ports[get_ports “Y??M Z*”] # Wildcardsecho “Effctv P = \ # Soft quotes , 1.9[expr $PERIOD * $MARGIN]”echo {Effctv P = \ # Hard quotes[expr $PERIOD * $MARGIN]} # , Effctv P = [expr $PER * $MARG] # Comment lineset COMMENT in_line; # In-line comment set MY_DESIGNS {B1.v ...B26.v} # foreach loop foreach DESIGN $MY_DESIGNS {read_verilog $DESIGN}for {set i 1} {$i < 27} {incr i} { # for loopread_verilog BLOCK_$i.v}Helpful UNIX-like DC-shell commandspwdcdlshistory!!!7!reportsh <UNIX_command>printenvget_unix_variable ARCHConstraintsreset_designset_max_area 0create_clock -period 2 –name Main_Clk [get_ports Clk1]create_clock –period 2.5 –waveform {2 3.5} [get_ports Clk2]create_clock –period 3.5 –name V_Clk; # VIRTUAL clockset_clock_uncertainty –setup 0.14 [get_clocks *]set_clock_uncertainty –setup 0.21 –from [get_clocks Main_Clk] –to [get_clocks Clk2] set_clock_latency –max 0.6 [get_clocks Main_Clk] set_clock_latency –source –max 0.3 [get_clocks Main_Clk]set_clock_transition 0.08 [get_clocks Main_Clk] set_input_delay -max 0.6-clock Main_Clk [all_inputs] set_input_delay –max 0.3 –clock Clk2 –clock_fall –add_delay [get_ports “B E”]set_input_delay -max 0.5 -clock –network_latency_included V_Clk [get_ports “A C F”]set_output_delay -max 0.8 -clock –source_latency_included Main_Clk [all_outputs]set_output_delay -max 1.1 -clock V_Clk [get_ports “OUT2 OUT7]set_max_capacitance 1.2 [all_inputs]set_load 0.080 [all_outputs]set_load [expr [load_of slow_proc/NAND2_3/A] * 4] [get_ports OUT3] set_load 0.12 [all_inputs]set_input_transition 0.12 [remove_from_collection[all_inputs][get_ports B]]set_driving_cell –lib_cell FD1 –pin Q [get_ports B]set_operating_conditions –max WCCOMset auto_wire_load_selection falseset_wire_load_model –name 1.6MGatesset_wire_load_mode enclosedset_wire_load_model –name 200KGates [get_designs “SUB1 SUB2”] set_wire_load_model –name 3.2MGates [get_ports IN_A]set_port_fanout_number 8 [get_ports IN_A] set_false_path -from[get_clocks Asynch_CLKA] -to [get_clocks Asynch_CLKB]set_multicycle_path –setup 4 –from –from A_reg -throughU_Mult/Out –to B_regset_multicycle_path –hold 3 –from –from A_reg -throughU_Mult/Out –to B_regset_isolate_ports –type inverter [all_outputs]set_ideal_network [get_ports reset* select*] set_ideal_network[get_pins FF_SET_reg/Q] set_ideal_network –no_propagate [get_nets CTRL] set_ideal_latency 1.4 [get_ports reset* select*]set_ideal_transition 0.5 [get_pins FF_SET_reg/Q] set_scan_configuration -style <multiplexed_flip_flop | clocked_scan | lssd | aux_clock_lssd> Checking and Removing Constraints and Directivesreport_clock; report_clock -skewreport_designreport_port –verbosereport_wire_loadreport_path_groupsreport_timing_requirements (–ignored) report_auto_ungroupreport_isolate_ports write_script –output <constraints.tcl>check_timingreset_path –from FF1_regremove_clockremove_clock_transition remove_clock_uncertainty remove_input_delay remove_output_delay remove_driving_cell remove_wire_load_modelSyntax CheckingUnix% dcprocheck constr_file.conPhysical Constraints – Topographical Modeset_aspect_ratioset_utilizationset_placement_areaset_rectilinear_outline set_port_sideset_port_locationset_cell_locationcreate_placement_keepoutMisc. Reports# Generate A library report fileread_db library_file.dblist_libsredirect –file reports/lib.rpt {report_lib <libname>}report_hierarchy [-noleaf]# Arithmetic implementation and# resource-sharing info report_resources# List area for all cells in the design report_cell [get_cells –hier *]Run Scriptread_verilog {A.v B.v TOP.v} orread_vhdl {A.vhd B.vhd TOP.vhd} orread_ddc MY_TOP.ddc oracs_read_hdl MY_TOP oranalyze –format verilog {A.v B.v TOP.v}elaborate MY_TOP –parameters “A_WIDTH=8, B_WIDTH=16”current_design MY_TOPlinkif {[check_design] ==0} {echo “Check Design Error”exit # Exits DC if a check-design error is encountered } # Continue if NO problems encounteredwrite –f ddc –hier –out unmappedd/TOP.ddcredirect –tee –file reports/precompile.rpt {source –echo -verbose TOP.con} redirect –append –tee –file reports/precompile.rpt{check_timing} source <Physical_Constraints_TCL_file> or # Source tcl constraints, if available, orextract_physical_constraints <DEF_file> # Extract and apply from an existing# DEF floorplan filegroup_path -name CLK1 -critical_range <10% of CLK1 Period> –weight 5group_path -name CLK2 -critical_range <10% of CLK2 Period> –weight 2group_path –name INPUTS –from [all_inputs]group_path –name OUTPUTS –to [all_outputs]group_path –name COMBO –from [all_inputs] –to [all_outputs]set_fix_multiple_port_nets –all –buffer_constants********************************************************* * ** Insert Expert, Ultra or ACS compile flow here * * **********************************************************check_designreport_constraint –all_violatorsreport_timing –delay –to –from –through –input_pins –max_paths \–nworst –nets –cap –sig –groupreport_areareport_qorset verilogout_no_tri truechange_names –rule verilog –hierwrite –f verilog –hier –out mapped/TOP.vwrite –f ddc –hier –out mapped/TOP.ddcwrite_sdc TOP.sdcwrite_scan_def –out TOP_scan.defwrite_physical_constraints –output TOP_PhysConstr.tcl exitObject Retrieval and Manipulation (Collection Commands)get_ports, get_pins, get_designsget_cells, get_nets, get_clocksget_nets –of_objects [get_pins FF1_reg/Q] get_libs <lib_name>get_lib_cells <lib_name/cell_names> get_lib_pins<lib_name/cell_name/pin_names> all_inputs, all_outputs, all_clocks,all_registers all_connectedall_fanin, all_fanoutall_ideal_netsset pci_ports [get_ports pci_*]echo $pci_ports # , _sel184query_objects $pci_ports # , {pci_1 pci_2 ...} get_object_name $pci_ports # , pci_1 pci_2 ...sizeof_collection $pci_ports # , 37set pci_ports [add_to_collection $pci_ports \[get_ports CTRL*]]set all_inputs_except_clk [remove_from_collection \[all_inputs] [get_ports CLK]]compare_collectionsindex_collectionsort_collectionforeach_in_collection my_cells [get_cells -hier * \-filter “is_hierarchical == true”] {echo “Instance [get_object_name $cell] is hierarchical”}# Filtering operators: ==, !=, >, <, >=, <=, =~, !~filter_collection [get_cells *] “ref_name =~ AN*”get_cells * -filter “dont_touch == true”get_clocks * -filter “period < 10”# List all cell attributes and redirect output to a fileredirect –file cell_attr \{list_attributes –application –class cell}# Grep the file for cell attributes starting with dont_UNIX% grep dont_ cell_attr | more# List the value of the attribute dont_touchget_attribute <cell_name> dont_touchUltra Compile Flow - Topographical or WLM ModeUltra + DesignWare and DFTC licenses available# In “topo” mode (dc_shell-t –topo) specify Milkyway reference and design libraries create_mw_lib –tech <technology_file> -mw_reference_library <mw_reference_libraries> \<mw_design_library_name>open_mw_lib <mw_design_library_name>set_tlu_plus_files -max_tluplus <max_tluplus_file> -tech2itf_map <mapping_file> set compile_auto_ungroup_delay_num_cells 99999999 set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup <top_level_and/or_pipelined_blocks> false# OPTIONAL: Disable unconditional auto-ungrouping# of DesignWare hierarchy (not usually recommended) setcompile_ultra_ungroup_dw false# If design contains pipelined sub-designs and the pipeline registers# are grouped together at the input or output, relax timingset_multicycle_path –setup <#_stages> -from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg*# In “ topo” mode, if the floorplan is available, apply or extract the physical constraintssource <physical_constraints_file> ORextract_physical_constraints <DEF_file># OPTIONAL: Exclude specific cells/design from adaptive retiming (-retime) set_dont_retime <cells_or_designs> true# First compilecompile_ultra –scan –retime –timing|-area# The design hierarchy may have changed due to auto-ungrouping/-uniquifying reset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg* # OPTIONAL: Maintain registered pipeline outputs if requiredset_dont_touch [get_cells U_Pipeline/R12_reg*] true# Optimize registers if pipeline violates timing; Skip if nopipeline issues: set_optimize_registers true –designMy_Pipeline_Subdesignoptimize_registers –only_attributed_designs# Continue if design is NOT meeting all constraints:# Apply more focus on violating critical paths, as necessarygroup_path –name <group_name> -from <path_start> -to <path_end> \ –critical range <10% of max delay goal> -weight 5# Select appropriate second compile# In “topo” mode in DC v2006.06, or any mode in DC v2007.03 or latercompile_ultra –scan –incremental# In “WLM” mode in DC v2006.06set_ultra_optimization truecompile –boundary –scan –map_effort high –incremental (-area_effort medium|low|none)# In “topo” mode prior to DC v2007.03: Write out updated physical constraintswrite_physical_constraints –output PhysConstr.tclDFT Flow – Expert or UltraDFTC license available# Prior to the first compile set the# scan cell styleset_scan_configuration –style ..# Perform the first test-ready compilecompile –boundary –map high –scan # ORcompile_ultra –timing -scan# Continue before the next compile:# Read in the scan specification filesource scan_spec.tcl# Check for DFT rule violationsdft_drc# Preview the scan chainspreview_dft# Insert and optimize scaninsert_dft****************************************************** * ** Execute additional Ultra/Expert optimization * * techniques, as needed * * *******************************************************# After the final compile check the DFT QoR# and write out the scan DEF filedft_drc –coverage_estimatewrite_scan_def -out <my_design.def>Some Scan Specification Commandsset_scan_state test_readyset_dft_configuration ...set_dft_signal ...set_scan_path ...set_scan_configuration ...create_test_protocolExpert Compile FlowNo Ultra license available; DFTC license available compile –boundary –scan –map_effort high# Continue if NOT meeting constraints# Note: -scan requires DFTC licensecompile –boundary –scan –map_effort high –incremental \(-area_effort medium|low|none)# Continue if NOT meeting constraints:# Increase max-delay priority if OK to postpone DRC fixingset_cost_priority –delay# Note: The design hierarchy may have changed due to auto-# uniquifying# Apply more focus on violating critical paths, as necessarygroup_path –name <group_name> -from <path_start> \-to <path_end> –critical range <10% of max delay goal> -weight 5 # Repartition if design is poorly partitioned group –design<NEW_DESIGN> -cell_name <U_NEW_CELL> \{U2 U7 ...}ungroup –start_level 2 U_NEW_CELLcompile –boundary –scan –map_effort high –incremental \(-area_effort medium|low|none)# Or, can ungroup all hierarchy in lieu of group/ungroup# commands with –ungroup_allcompile –boundary –scan –map_effort high –incremental \(-area_effort medium|low|none) –ungroup_all“Pseudo Ultra” Compile FlowUltra license available; No DesignWare license available set compile_auto_ungroup_delay_num_cells 99999999 setcompile_auto_ungroup_area_num_cells 99999999 setcompile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup <top_level_and/or_pipelined_blocks> false# OPTIONAL: Disable unconditional auto-ungrouping# of DesignWare hierarchy (not usually recommended) set compile_ultra_ungroup_dw false# If design contains pipelined sub-designs and the pipeline registers# are grouped together at the input or output, relax timing set_multicycle_path –setup <#_stages> \-from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg*# Enable Ultra optimizations available for compileset_ultra_optimization –no_auto_dwlib trueset hlo_disable_datapath_optimization trueset compile_slack_driven_buffering truecompile –boundary –scan –map_effort high –auto_ungroup delay|area \ (-area_effort medium|low|none)# Note: The design hierarchy may have changed due to auto- # ungrouping and auto-uniquifyingreset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg* # OPTIONAL: Maintain registered pipeline outputs if required set_dont_touch [get_cells U_Pipeline/R12_reg*] true # Optimize registers if pipeline violates timing; Skip if no pipeline issues:set_optimize_registers true –design My_Pipeline_Subdesign optimize_registers –only_attributed_designs# Continue if design is NOT meeting all constraints: compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)# Continue if NOT meeting all constraints:set_cost_priority –delay# Ungroup DesignWare components amid combinational logic ungroup <DesignWare_components># Apply more focus on violating critical paths, as necessary group_path –name <group_name> -from <path_start> -to <path_end> \ –critical range <10% of max delay goal> -weight 5 compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)。

DC Design Compiler 综合脚本命令及参考模板

Design Compiler 综合脚本常用命令和模板参照自己的设计，以及自己的工艺信息，适当修改下面的Constraints和Run Script 等的脚本，添加一些相关的约束语句，就可以运行了详细的命令请参照DC的官方User Guide等相关资料。

Invoking Design CompilerUnix% design_vision # Interactive GUI, WLM modeUnix% design_vision –topographical # Interactive GUI, Topographical modeUnix% dc_shell-t # Interactive shell, WLM modeUnix% dc_shell-t –topographical # Interactive shell, Topographical modeUnix% dc_shell-t –f RUN.tcl | tee –i my.log # Batch mode.synopsys_dc.setupset search_pa th “$search_path libs cons unmapped rtl”set synthetic_library dw_foundation.sldbset target_library 65nm.dbset link_library “* $target_library $synthetic_library IP.db”set symbol_library 65nm.sdbdefine_design_lib WORK –path ./workset_svf <my_filename.svf>set_vsdc <my_filename.vsdc>history keep 200set sh_enable_page_mode falseset cache_write .set cache_read $cache_writesuppress_message {LINT-28 LINT-32 LINT-33 UID-401}set alib_library_analysis_path [get_unix_variable HOME]alias h historyalias rc “report_constraint -all_violators”TCL Commands and Constructsset PER 2.0 # Define a variable and its valueecho $PER # Variable substitution → 2.0set MARG 0.95expr $PER * $MARG # expr: *, /, +, -, >, <, =, <=, >=set pci_ports [get_ports A] # Imbedded commandset pci_ports [get_ports “Y??M Z*”]# Wildcardsecho “Effctv P = \ # Soft quotes → 1.9[expr $PERIOD * $MARGIN]”echo {Effctv P = \ # Hard quotes[expr $PERIOD * $MARGIN]} # → Effctv P = [expr $PER * $MARG] # Comment lineset COMMENT in_line; # In-line commentset MY_DESIGNS {B1.v ... B26.v} # foreach loopforeach DESIGN $MY_DESIGNS {read_verilog $DESIGN}for {set i 1} {$i < 27} {incr i} { # for loopread_verilog BLOCK_$i.v}Helpful UNIX-like DC-shell commandspwdcdlshistory!!!7!reportsh <UNIX_command>printenvget_unix_variable ARCHConstraintsreset_designset_max_area 0create_clock -period 2 –name Main_Clk [get_ports Clk1]create_clock –period 2.5 –waveform {2 3.5} [get_ports Clk2]create_clock –period 3.5 –name V_Clk; # VIRTUAL clockset_clock_uncertainty –setup 0.14 [get_clocks *]set_clock_uncertainty –setup 0.21 –from [get_clocks Main_Clk] –to [get_clocks Clk2]set_clock_latency –max 0.6 [get_clocks Main_Clk]set_clock_latency –source –max 0.3 [get_clocks Main_Clk]set_clock_transition 0.08 [get_clocks Main_Clk]set_input_delay -max 0.6 -clock Main_Clk [all_inputs]set_input_delay –max 0.3 –clock Clk2 –clock_fall –add_delay [get_ports “B E”]set_input_delay -max 0.5 -clock –network_latency_included V_Clk [get_ports “A C F”]set_output_delay -max 0.8 -clock –source_latency_included Main_Clk [all_outputs]set_output_delay -max 1.1 -clock V_Clk [get_ports “OUT2 OUT7]set_max_capacitance 1.2 [all_inputs]set_load 0.080 [all_outputs]set_load [expr [load_of slow_proc/NAND2_3/A] * 4] [get_ports OUT3]set_load 0.12 [all_inputs]set_input_transition 0.12 [remove_from_collection [all_inputs][get_ports B]]set_driving_cell –lib_cell FD1 –pin Q [get_ports B]set_operating_conditions –max WCCOMset auto_wire_load_selection falseset_wire_load_model –name 1.6MGatesset_wire_load_mode enclosedset_wire_load_model –name 200KGates [get_designs “SUB1 SUB2”]set_wire_load_model –name 3.2MGates [get_ports IN_A]set_port_fanout_number 8 [get_ports IN_A]set_false_path -from [get_clocks Asynch_CLKA] -to [get_clocks Asynch_CLKB]set_multicycle_path –setup 4 –from –from A_reg -through U_Mult/Out –to B_regset_multicycle_path –hold 3 –from –from A_reg -through U_Mult/Out –to B_regset_isolate_ports –type inverter [all_outputs]set_ideal_network [get_ports reset* select*]set_ideal_network [get_pins FF_SET_reg/Q]set_ideal_network –no_propagate [get_nets CTRL]set_ideal_latency 1.4 [get_ports reset* select*]set_ideal_transition 0.5 [get_pins FF_SET_reg/Q]set_scan_configuration -style <multiplexed_flip_flop | clocked_scan | lssd | aux_clock_lssd>Checking and Removing Constraints and Directivesreport_clock; report_clock -skewreport_designreport_port –verbosereport_wire_loadreport_path_groupsreport_timing_requirements (–ignored)report_auto_ungroupreport_isolate_portswrite_script –output <constraints.tcl>check_timingreset_path –from FF1_regremove_clockremove_clock_transitionremove_clock_uncertaintyremove_input_delayremove_output_delayremove_driving_cellremove_wire_load_modelSyntax CheckingUnix% dcprocheck constr_file.conPhysical Constraints – Topographical Modeset_aspect_ratioset_utilizationset_placement_areaset_rectilinear_outlineset_port_sideset_port_locationset_cell_locationcreate_placement_keepoutMisc. Reports# Generate A library report fileread_db library_file.dblist_libsredirect –file reports/lib.rpt {report_lib <libname>} report_hierarchy [-noleaf]# Arithmetic implementation and# resource-sharing inforeport_resources# List area for all cells in the designreport_cell [get_cells –hier *]Run Scriptread_verilog {A.v B.v TOP.v} orread_vhdl {A.vhd B.vhd TOP.vhd} orread_ddc MY_TOP.ddc oracs_read_hdl MY_TOP oranalyze –format verilog {A.v B.v TOP.v}elaborate MY_TOP –parameters “A_WIDTH=8, B_WIDTH=16”current_design MY_TOPlinkif {[check_design] ==0} {echo “Check Design Error”exit # Exits DC if a check-design error is encountered} # Continue if NO problems encounteredwrite –f ddc –hier –out unmappedd/TOP.ddcredirect –tee –file reports/precompile.rpt {source –echo -verbose TOP.con}redirect –append –tee –file reports/precompile.rpt {check_timing}source <Physical_Constraints_TCL_file> or # Source tcl constraints, if available, or extract_physical_constraints <DEF_file> # Extract and apply from an existing # DEF floorplan filegroup_path -name CLK1 -critical_range <10% of CLK1 Period> –weight 5group_path -name CLK2 -critical_range <10% of CLK2 Period> –weight 2group_path –name INPUTS –from [all_inputs]group_path –name OUTPUTS –to [all_outputs]group_path –name COMBO –from [all_inputs] –to [all_outputs]set_fix_multiple_port_nets –all –buffer_constants********************************************************** ** Insert Expert, Ultra or ACS compile flow here ** **********************************************************check_designreport_constraint –all_violatorsreport_timing –delay –to –from –through –input_pins –max_paths \–nworst –nets –cap –sig –groupreport_areareport_qorset verilogout_no_tri truechange_names –rule verilog –hierwrite –f verilog –hier –out mapped/TOP.vwrite –f ddc –hier –out mapped/TOP.ddcwrite_sdc TOP.sdcwrite_scan_def –out TOP_scan.defwrite_physical_constraints –output TOP_PhysConstr.tcl exitObject Retrieval and Manipulation (Collection Commands) get_ports, get_pins, get_designsget_cells, get_nets, get_clocksget_nets –of_objects [get_pins FF1_reg/Q]get_libs <lib_name>get_lib_cells <lib_name/cell_names>get_lib_pins <lib_name/cell_name/pin_names>all_inputs, all_outputs, all_clocks, all_registersall_connectedall_fanin, all_fanoutall_ideal_netsset pci_ports [get_ports pci_*]echo $pci_ports # → _sel184 query_objects $pci_ports # → {pci_1 pci_2 ...} get_object_name $pci_ports # → pci_1 pci_2 ... sizeof_collection $pci_ports # → 37set pci_ports [add_to_collection $pci_ports \[get_ports CTRL*]]set all_inputs_except_clk [remove_from_collection \ [all_inputs] [get_ports CLK]]compare_collectionsindex_collectionsort_collectionforeach_in_collection my_cells [get_cells -hier * \ -filter “is_hierarchical == true”] {echo “Instance [get_object_name $cell] is hierarchical”}# Filtering operators: ==, !=, >, <, >=, <=, =~, !~filter_collection [get_cells *] “ref_name =~ AN*”get_cells * -filter “dont_touch == true”get_clocks * -filter “period < 10”# List all cell attributes and redirect output to a fileredirect –file cell_attr \{list_attributes –application –class cell}# Grep the file for cell attributes starting with dont_UNIX% grep dont_ cell_attr | more# List the value of the attribute dont_touchget_attribute <cell_name> dont_touchUltra Compile Flow - Topographical or WLM ModeUltra + DesignWare and DFTC licenses available# In “topo” mode (dc_shell-t –topo) specify Milkyway reference and design libraries create_mw_lib –tech <technology_file> -mw_reference_library <mw_reference_libraries> \<mw_design_library_name>open_mw_lib <mw_design_library_name>set_tlu_plus_files -max_tluplus <max_tluplus_file> -tech2itf_map <mapping_file>set compile_auto_ungroup_delay_num_cells 99999999set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup <top_level_and/or_pipelined_blocks> false# OPTIONAL: Disable unconditional auto-ungrouping# of DesignWare hierarchy (not usually recommended)set compile_ultra_ungroup_dw false# If design contains pipelined sub-designs and the pipeline registers# are grouped together at the input or output, relax timingset_multicycle_path –setup <#_stages> -from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg* # In “ topo” mode, if the floorplan is available, apply or extract the physical constraints source <physical_constraints_file> ORextract_physical_constraints <DEF_file># OPTIONAL: Exclude specific cells/design from adaptive retiming (-retime)set_dont_retime <cells_or_designs> true# First compilecompile_ultra –scan –retime –timing|-area# The design hierarchy may have changed due to auto-ungrouping/-uniquifyingreset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg*# OPTIONAL: Maintain registered pipeline outputs if requiredset_dont_touch [get_cells U_Pipeline/R12_reg*] true# Optimize registers if pipeline violates timing; Skip if no pipeline issues:set_optimize_registers true –design My_Pipeline_Subdesignoptimize_registers –only_attributed_designs# Continue if design is NOT meeting all constraints:# Apply more focus on violating critical paths, as necessarygroup_path –name <group_name> -from <path_start> -to <path_end> \–critical range <10% of max delay goal> -weight 5# Select appropriate second compile# In “topo” mode in DC v2006.06, or any mode in DC v2007.03 or latercompile_ultra –scan –incremental# In “WLM” mode in DC v2006.06set_ultra_optimization truecompile –boundary –scan –map_effort high –incremental (-area_effort medium|low|none) # In “topo” mode prior to DC v2007.03: Write out updated physical constraintswrite_physical_constraints –output PhysConstr.tclDFT Flow – Expert or UltraDFTC license available# Prior to the first compile set the# scan cell styleset_scan_configuration –style ..# Perform the first test-ready compilecompile –boundary –map high –scan # ORcompile_ultra –timing -scan# Continue before the next compile:# Read in the scan specification filesource scan_spec.tcl# Check for DFT rule violationsdft_drc# Preview the scan chainspreview_dft# Insert and optimize scaninsert_dft******************************************************* * * Execute additional Ultra/Expert optimization ** techniques, as needed ** * ******************************************************# After the final compile check the DFT QoR# and write out the scan DEF filedft_drc –coverage_estimatewrite_scan_def -out <my_design.def>Some Scan Specification Commandsset_scan_state test_readyset_dft_configuration ...set_dft_signal ...set_scan_path ...set_scan_configuration ...create_test_protocolExpert Compile FlowNo Ultra license available; DFTC license availablecompile –boundary –scan –map_effort high# Continue if NOT meeting constraints# Note: -scan requires DFTC licensecompile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)# Continue if NOT meeting constraints:# Increase max-delay priority if OK to postpone DRC fixingset_cost_priority –delay# Note: The design hierarchy may have changed due to auto- # uniquifying# Apply more focus on violating critical paths, as necessary group_path –name <group_name> -from <path_start> \-to <path_end> –critical range <10% of max delay goal> -weight 5 # Repartition if design is poorly partitionedgroup –design <NEW_DESIGN> -cell_name <U_NEW_CELL> \{U2 U7 ...}ungroup –start_level 2 U_NEW_CELLcompile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)# Or, can ungroup all hierarchy in lieu of group/ungroup# commands with –ungroup_allcompile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none) –ungroup_all“Pseudo Ultra” Compile FlowUltra license available; No DesignWare license availableset compile_auto_ungroup_delay_num_cells 99999999set compile_auto_ungroup_area_num_cells 99999999set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup <top_level_and/or_pipelined_blocks> false# OPTIONAL: Disable unconditional auto-ungrouping# of DesignWare hierarchy (not usually recommended)set compile_ultra_ungroup_dw false# If design contains pipelined sub-designs and the pipeline registers# are grouped together at the input or output, relax timingset_multicycle_path –setup <#_stages> \-from U_Pipeline/R3_reg* –to U_Pipeline/R7_reg*# Enable Ultra optimizations available for compileset_ultra_optimization –no_auto_dwlib trueset hlo_disable_datapath_optimization trueset compile_slack_driven_buffering truecompile –boundary –scan –map_effort high –auto_ungroup delay|area \ (-area_effort medium|low|none)# Note: The design hierarchy may have changed due to auto-# ungrouping and auto-uniquifyingreset_path -from U_Pipeline/R3_reg* -to U_Pipeline/R7_reg*# OPTIONAL: Maintain registered pipeline outputs if requiredset_dont_touch [get_cells U_Pipeline/R12_reg*] true# Optimize registers if pipeline violates timing; Skip if no pipeline issues:set_optimize_registers true –design My_Pipeline_Subdesignoptimize_registers –only_attributed_designs# Continue if design is NOT meeting all constraints:compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)# Continue if NOT meeting all constraints:set_cost_priority –delay# Ungroup DesignWare components amid combinational logicungroup <DesignWare_components># Apply more focus on violating critical paths, as necessarygroup_path –name <group_name> -from <path_start> -to <path_end> \–critical range <10% of max delay goal> -weight 5compile –boundary –scan –map_effort high –incremental \ (-area_effort medium|low|none)。

详解DC、CDC、HDC、句柄、设备上下文

请问MFC中的DC、CDC、HDC、句柄、设备上下文究竟是什么意思？希望能解答详细一点点谢谢了楼主你没有了解MFC的运行机制就去看他写他所以你先要了解他的机制已经各个CPP .H都是什么下面我就给你说下在MFC程序中,我们并不经常直接调用Windows API,而是从MFC类创建对象并调用属于这些对象的成员函数.也就是说MFC封装了Windows API 你说你喜欢C++而MFC换一种说法就是一个用C++写的一个函数库然后你来调用只不过这个类不是你写的MFC提供数百个类，最重要的、也是编写任何VC++应用程序都必不可少的两个类CWinApp和CFrameWnd,这两个类是编写复杂庞大应用程序的基石。

1>封装特性：构成MFC框架的是MFC类库而MFC类库又是C++的一个类库。

这些类封装WIN32应用程序编程接口，OLE(Object Link Embed 对象链接嵌入)特性，ODBC和DAO数据访问的功能。

2>继承特性：MFC抽象出了众多类的共同特性，并设计出一些基类作为实现其他类的基础，这些类中最重要的类是CObject类和CCmdTarget类，程序员可以从适当的MFC类中派生出自己的类，实现特定的功能达到编程的目的。

3>虚拟和消息映射：MFC是以C++为基础，当然支持虚函数，但作为一个编程框架必须要解决的是效率问题：如果MFC仅仅通过虚函数来支持动态约束必然会产生大量的虚函数表这样编程框架过于臃肿而且消耗更多的内存。

但是MFC 建立了消息映射机制这样降低了内存的使用却大大提高了效率消息映射是一个将消息和成员函数相互关联的表,当应用程序的框架窗口接收到一个消息时,MFC将搜索该窗口的消息映射,如果存在一个处理消息的处理程序,那么就调用该处理程序.它通过宏来实现消息到成员函数的映射，而且这些函数不必是虚拟的成员函数，这样不需要为消息映射函数生成一个很大的虚拟函数表(V表)，节省内存。

dc使用教程

d c使用教程-CAL-FENGHAI.-(YICAI)-Company One1DC使用说明文件说明：在进行下面的演示时需要用到两个文件，一个是，它是描述一个电路的verilog代码，我们的目标就是用DC综合这个代码得到满足约束条件的电路网表；另一个是，它是综合的脚本文件。

这两个文件都在/home/student1000目录下，大家把它们拷贝到自己的目录下，以备使用。

DC既可使用图形界面，也可不使用图形界面而直接运行脚本来综合电路。

一、DC图形界面的使用。

1.DC图形界面的启动打开一个终端窗口，写入命令 dv –db_mode，敲入回车。

则DC图形界面启动，如下图所示红框处是DC的命令输入框，以下在图形界面上的操作都可以在命令输入框中输入相应的命令来完成。

选择Help-----Man Pages可以查看DC的联机帮助。

相应指令：man。

例：man man表示查看man命令的帮助。

man create_clock表示查看creat_clock命令的帮助。

2.设置库文件选择File----Setup需要设置以下库文件，如下图。

相应指令：set search_path [list /tools/lib/smic25/feview_s/version1/STD/Synopsys \ /tools/lib/smic25/feview_s/version1/STD/Symbol/synopsys]set target_library { }set link_library { }set symbol_library { }点OK，设置完成。

3.读入verilog文件选择File---Read在打开文件对话框中选中要打开的文件，在这里我们选中文件。

在Log框中出现successfully字样表明读入文件成功。

相应命令：read_file点击红色箭头所指的按钮可以查看该电路的symbol图。

4.设置约束条件4.1设置时钟约束在symbol图上选中clk端口选择Attributes-----Specify Clock出来设置时钟约束的对话框，按下图设置，给时钟取名为clock，周期20ns，上升沿0ns，下降沿10ns。

DC常用命令及脚本

利用DC进行综合设计(2012-03-25 17:45:10)转载▼标签：dc综合杂谈DC的综合术语用于设计的ASIC的EDA工具往往是一套很复杂的软件，包括大量的工具和文档。

同时，每个公司都有自己的一套术...一、预备知识1.1、DC的综合术语用于设计的ASIC的EDA工具往往是一套很复杂的软件，包括大量的工具和文档。

同时，每个公司都有自己的一套术语。

只有理解了这些术语的含义才能很好的掌握这些工艺。

1 设计和设计对象设计是实现一定逻辑功能的电路的描述。

设计对象就是在设计中被DC命令、属性和约束操作或控制的对象。

常用的设计中包括元件、网络、端口、引脚和时钟。

另外，一个设计可能包括某个相同子设计或库元件的多个例化。

这时候被例化的设计或库元件称作参考。

在一个设计中查找某个对象的命令：find，这是在DC命令中很常用的命令。

如：列出当前设计的所有端口（ports）:Dc_shell>findport OR find(port,”*”)列出所有包含”DW”字母的元件：dc_shell>find (cell,”*DW*”)列出cba_core库中的AN2门的所有接脚：dc_shell>find(pin,cba_core/AN2Read –format vhdl ./src/rtl/timer_tugw.vhdRead –format vhdl ./src/rtl/test_top.vhdCheck_error –vIf(dc_shell_status= =1){exit 1}Current_design test_topLinkCheck_error –vIf(dc_shell_status= =1){exit 1}Include pass0/constraint/test_top.conCheck_error –vIf(dc_shell_status= =1){exit 1}Set_max_area 0.0000Set_flatten falseEcho”***doing full compile for the partition ‘test_top’***”Sh date;Compile –map_effort mediumCheck_error –vIf(dc_shell_status= =1){exit 1}Sh date;Check_designCompile_top_acs_partion=tureCompile_top_all_paths=trueEcho”***doing boundary compile for the partition ‘test_top’***”Sh date;Compile –topUniquifyCheck_error –vIf(dc_shell_status= =1){exit 1}Sh date;Current_design test_topWrite –format db –hierarchy –output pass0/db/test_top.dbWrite –format verilog –hierarchy –output pass0/db/test_top.vWrite –format vhdl –hierarchy –output pass0/db/test_top.vhdReport_timing> pass0/report/test_top.timReport_area> pass0/report/test_top.areaReport_constraints> pass0/report/test_top.cstrReport_qor> pass0/report/test_top.qorReport_constraints–all_violators–verbose>pass0/report/test_top.vioquit脚本文件可以使用任何一个文本编辑工具产生或修改，也可以在dc_shell中执行write_scirpt 命令产生。

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#script for Design Compiler# Language : TCL# Usage :# 1) make sure the lib in the current directory# 2) if you...#script for Design Compiler# Language : TCL# Usage :# 1) make sure the lib in the current directory# 2) if you have the file .synopsys_dc.setup,# set synopsys_dc_setup_file 1,# if not, set synopsys_dc_setup_file 0# 3) change Step 3 : Variables to what you want# Especially : top module name, clock name,# reset name, all files name, and period# 4) typing dc_shell-t -f run_72.tcl | tee -i run.log##===================================================== ===set synopsys_dc_setup_file 0#-----------------------------------------------------# Step 1 :# Setting Up path and library：# If you have edited the file .synopsys_dc.setup, then you can skip over this step#-----------------------------------------------------if { $synopsys_dc_setup_file == 0} {set search_path [list /home/chanshi/dc/library/smic /home/chanshi/dc/rfid/source /home/chanshi/dc/script]set target_library {typical.db}#set target_library {CSM35OS142_typ.db};# if you want use typical library,change to typical.db#set link_library [list {*} ram_interp_typical_syn.db ram_458_typical_syn.db typical.db] set link_library [list {*} $target_library]}#set symbol_library {csm18ic.sdb csm18io.sdb}#set synthetic_library {dw_foundation.sldb};# Design Wareset command_log_file "command.log"#-----------------------------------------------------# Step 2 :# Compile Swithes#-----------------------------------------------------#set verilogout_no_tri true ;# if inout used, tri net will be used#通过将三态（tri）逻辑声明成线网（wire）来确保网表中不会出现三态逻辑，因为一些布线工具很难读取包含tri、tran源语、assign语句的网表，对于“inout”类型的port,DC产生tri wire 语句和tran 源语，对于tri，还会产生assign语句set test_default_scan_style multiplexed_flip_flop#设置扫描链的类型，还可以通过set_scan_configuration -style来设置set link_force_case case_insensitive#设置link命令是否区分大小写，默认是check_reference,就是根据产生reference的模块格式来判断是否大小写敏感，如果是vhdl格式就是不敏感，如果是verilog就敏感define_name_rules VLSI_NET -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256define_name_rules VLSI_CELL -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type cell -max_length 256define_name_rules VLSI_PORT -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type port -max_length 256define_name_rules TAN_RULE -allowed "a-zA-Z0-9_" -first_restricted "0-9_\[]" -max_length 256 -map {{{"*cell*", "mycell"}, {"*-return", "myreturn"}}};set hdlin_check_no_latch "true"#设置如果推断出锁存器，是否报warning，默认是false，即不报。

set hdlin_merge_nested_conditional_statements "true"#顾名思义，是否把嵌套的if融合，默认值是false，就是对于嵌套的条件语句（if或case 语句）中的每一个if和case都推断出一个选择器，这种做法有利于把某些迟到的条件判断信号（late arriving signals）安排到离输出最近的选择器上（进而有利于减小延迟），如果设成true，就会把这些选择器融合成一个大的选择器，这样所有的选择信号到输出的距离都是相同的#-----------------------------------------------------# Step 3 :# Define Variables#-----------------------------------------------------set active_design "whole_modules";# Top module namesource files.tcl;# All RTL source_files (verilog)set clock_name "clk";# Name of clockset reset_name "reset";# Name of resetset clk_period 70.0#设置时钟周期，注意带小数点，这样计算出的值都带小数点，不然小于1的数都显示为0 # Desired Clock Period = 1000/Frequenceset clk_uncertainty_setup [expr $clk_period/200];#设置时钟不确定性，这里只设置了相对于建立时间的不确定性，就是时钟上升沿有可能提前clk_uncertainty_setup（时钟偏差和时钟抖动之和）到来，dc要提前clk_uncertainty_setup 检查建立时间是否满足# Uncertainty of clockset clk_latency [expr $clk_period/10];#设置时钟延迟，是时钟信号从其实际时钟原点到设计中时钟定义点的传输时间# Network Latency of clock#考虑reg1+combo1--------combo2_input+reg2+combo2_output-----------combo3+reg3的模型来解释input_delay和output_delay，中间的combo2_input+reg2+combo2_output 是要综合的模块set input_delay [expr $clk_period/4];#设置输入延迟，设置一个外部输入（组合逻辑combo1）用了多少时间（即从时钟上升沿到输入数据到来经历的延迟），dc计算还有多少时间留给内部组合逻辑combo2_input，例如时钟周期为10ns，input_delay是4ns，则还有（6-tsu）留给内部组合逻辑combo2_input # Input Delay of all input ports except clockset output_delay [expr $clk_period/4];#设置输出延迟，设置一个外部输出（组合逻辑combo3）用了多少时间（即外部组合逻辑的延迟），dc计算有多少时间留给内部组合逻辑combo2_output，例如时钟周期为10ns，output_delay为4ns，则还有（6-Tclk2Q）留给内部组合逻辑combo2_output# Output Delay of all output portsset area_desired 0;#设置面积的期望值，用于set_max_areaset wire_load_model "smic18_wl20";#为了精确地计算设置线载模型（DC支持三种模式：以此来决定如何选择用于跨层次边界的网线的线载模型），用于计算时序路径的延迟，用于set_wire_load_model# Model of the intra netset output_load "typical/NAND2BX1/AN" ;#为了精确地计算输出电路的时间，需要设置端口负载（输出或输入的外部电容负载），就是为所有输出端口指定一个负载，综合时dc就会认为这里有一个这样的负载（并不是说综合时在这里强制添加一个电容），dc综合时就会选择满足这个负载的器件，例如假设已经知道某输出端口要驱动的是一个反相器，那么把输出负载设置成这个反相器的输入负载即可，当然可以设置成很大，这样dc就会用驱动能力很大的器件，来满足所有单元被驱动。