数字电路与系统答案(丁志杰)

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数字电路与系统分析第一章习题答案

数字电路与系统习题参考答案南京邮电学院电子工程系2003/12习题答案1.1将下列各式写成按权展开式：（352.6）10=3×102+5×101+2×100+6×10-1（101.101）2=1×22+1×20+1×2-1+1×2-3（54.6）8=5×81+54×80+6×8-1（13A.4F）16=1×162+3×161+10×160+4×16-1+15×16-21.2按十进制0~17的次序，列表填写出相应的二进制、八进制、十六进制数。

解：略1.3二进制数00000000~11111111和0000000000~1111111111分别可以代表多少个数？解：分别代表28=256和210=1024个数。

（0110.1010）余3循环BCD码=（1.1110）2——余3循环BCD码中的1和0没有权值意义，因此先转换成十进制数（1.9）10，得出原精度为10-1，转换的二进制的小数位k≥3.3，因此至少取4位。

大连理工大学智慧树知到“电力系统自动化技术”《数字电路与系统》网课测试题答案卷3

大连理工大学智慧树知到“电力系统自动化技术”《数字电路与系统》网课测试题答案（图片大小可自由调整）第1卷一.综合考核(共10题)1.下列关于多变量异或运算说法中，正确的是()。

A.奇数个变量为0，则结果为1B.奇数个变量为1，则结果为1C.偶数个变量为1，则结果为1D.偶数个变量为1，则结果为02.基本RS触发器可以通过统一的控制信号控制其转换时刻。

()A.正确B.错误3.TTL与非门和TTL非门相比较，下列说法正确的是()。

A.结构不同B.结构相同C.输入端个数不同D.输入端个数相同4.转换精度是表征DAC性能的唯一的参数。

()A.正确B.错误5.改变集成计数器的模的方法有哪些?()A.异步清0法B.同步清0法C.异步置数法D.同步置数法6.由与非门构成的基本RS触发器中，当两个输入端都为1时，触发器()。

A.具有保持功能B.置1C.置0D.是不确定状态7.两个模N计数器级联，可实现()的计数器。

A.1B.N×NC.ND.2N8.7485是一个()。

A.译码器B.编码器C.触发器D.数值比较器9.时序逻辑电路要想完全描述功能，必须要有下列哪些方程?()A.特性方程B.激励方程C.状态方程D.输出方程10.A+AB=()。

A.AB.BC.ABD.A+B第1卷参考答案一.综合考核1.参考答案：BD2.参考答案：B3.参考答案：BC4.参考答案：B5.参考答案：ABCD6.参考答案：A7.参考答案：B8.参考答案：D9.参考答案：BCD10.参考答案：A。

数字电路与系统分析第九章习题答案

9.3 习题答案9.1 在ROM中，什么是“字数”，什么是“位数”？如何标注存储器的容量？解：地址译码器的输出线称作字线，字数表示字线的个数；存储矩阵的输出线称作位线(数据线)。

位数表示位线的个数。

字线和位线的每个交叉占处有—个存储单元。

因此存储容量用“字数×位数”表示。

9.2 固定ROM、PROM、EPROM、E2PROM之间有何异同？解：固定ROM、PROM、EPROM、E2PROM都是只读存储器，它们的工作原理和结构相同，都是由地址译码器、存储矩阵和输出电路构成，当地址译码器选中某一个字后，该字的若干位同时由输出电路输出，存储矩阵由M个字、每个字N位的存储单元构成。

它们的不同之处在于存储单元的写入和擦除方式不同。

固定ROM出厂时结构数据已经固定，用户不能更改，适于存储大批量生产的程序和数据，常被集成到微控制器中作为程序存储器；PROM可由用户写入数据，但只能一次性写入，之后不能更改。

适于存储中、小批量生产的程序和数据；EPROM数据可通过紫外线擦除，重新写入。

可擦除数百次，写入一个字节需50ms。

适用于开发研制阶段存储数据和程序，并可经常修改；E2PROM数据可通过电擦除，因此在工作时间可随时擦写。

可擦除数10~1000万次，写入一个字节需20ms。

适合于信息量不大，经常要改写，掉电后仍保存的场合。

9.3 试用ROM阵列图实现下列一组多输出逻辑函数F1(A,B,C)=⎺AB+A⎺B+BCF2(A,B,C)=∑m(3,4,5,7)F3(A,B,C)=⎺A⎺B⎺C+⎺A⎺BC+⎺ABC+AB⎺C+ABC解：将F1 ,F2 ,F3都用最小项表达式表示：F1(A,B,C)=⎺AB+A⎺B+BC=∑m(2,3,4,5,7)F2(A,B,C)=∑m(3,4,5,7)F3(A,B,C)=⎺A⎺B⎺C+⎺A⎺BC+⎺ABC+AB⎺C+ABC=∑m(0,1,3,6,7)ROM的阵列图如下图：9.4 用适当规模PROM 设计2位全加器，输入被加数及加数分别为a 2a 1和b 2b 1，低位来的进位是CI ，输出本位和∑2∑1以及向高位的进位C O2。

数字电路与系统设计课后习题答案

.1.1将下列各式写成按权展开式：（352.6）10=3×102+5×101+2×100+6×10-1（101.101）2=1×22+1×20+1×2-1+1×2-3（54.6）8=5×81+54×80+6×8-1（13A.4F）16=1×162+3×161+10×160+4×16-1+15×16-21.2按十进制0~17的次序，列表填写出相应的二进制、八进制、十六进制数。

解：略1.3二进制数00000000~11111111和0000000000~1111111111分别可以代表多少个数？解：分别代表28=256和210=1024个数。

1.4将下列个数分别转换成十进制数：（1111101000）2，（1750）8，（3E8）16解：（1111101000）2=（1000）10（1750）8=（1000）10（3E8）16=（1000）101.5将下列各数分别转换为二进制数：（210）8，（136）10，（88）16解：结果都为：（10001000）21.6将下列个数分别转换成八进制数：（111111）2，（63）10，（3F）16解：结果都为（77）81.7将下列个数分别转换成十六进制数：（11111111）2，（377）8，（255）10解：结果都为（FF）161.8转换下列各数，要求转换后保持原精度：解：（1.125）10=（1.0010000000）10——小数点后至少取10位（0010 1011 0010）2421BCD=（11111100）2（0110.1010）余3循环BCD码=（1.1110）21.9用下列代码表示（123）10，（1011.01）2：解：（1）8421BCD码：（123）10=（0001 0010 0011）8421BCD（1011.01）2=（11.25）10=（0001 0001.0010 0101）8421BCD（2）余3 BCD码（123）10=（0100 0101 0110）余3BCD（1011.01）2=（11.25）10=（0100 0100.0101 1000）余3BCD1.10已知A=（1011010）2，B=（101111）2，C=（1010100）2，D=（110）2（1）按二进制运算规律求A+B，A-B，C×D，C÷D，（2）将A、B、C、D转换成十进制数后，求A+B，A-B，C×D，C÷D，并将结果与（1）进行比较。

大连理工大学智慧树知到“电力系统自动化技术”《数字电路与系统》网课测试题答案卷5

大连理工大学智慧树知到“电力系统自动化技术”《数字电路与系统》网课测试题答案（图片大小可自由调整）第1卷一.综合考核(共10题)1.基本RS触发器可以通过统一的控制信号控制其转换时刻。

()A.正确B.错误2.两个一位二进制数的相加可以通过半加器来实现。

()A.错误B.正确3.单稳态触发器的暂稳态时间Tω取决于哪些因素?()A.输入信号B.输出信号C.定时元件RD.定时元件C4.组合逻辑电路的“0”型冒险会使输出出现()的脉冲。

A.低电平B.高电平C.窄D.宽5.ADC的转换精度常用下列哪些项来表示?()A.分辨率B.转换误差C.线性误差D.温度系数6.下列哪项不属于集成触发器按照触发方式的分类?()A.电平触发器B.脉冲触发器C.时钟触发器D.边沿触发器7.改变集成计数器的模的方法有哪些?()A.异步清0法B.同步清0法C.异步置数法D.同步置数法8.组合逻辑电路分析的任务是：对给定的逻辑电路图，找出电路的逻辑功能。

()A.错误B.正确9.两个二进制数之间的算术运算的实现在数字计算机中都是化成若干步()进行运算的。

A.加法B.减法C.乘法D.除法10.数字电路中常用“1”和“0”表示两种不同的状态。

()A.错误B.正确第1卷参考答案一.综合考核1.参考答案：B2.参考答案：B3.参考答案：CD4.参考答案：AC5.参考答案：AB6.参考答案：C7.参考答案：ABCD8.参考答案：B9.参考答案：A10.参考答案：B。

数字电路与系统分析第六章习题答案

解：1）分析电路结构：该电路是由七个与非门及一个JKFF组成，且CP下降沿触发，属于米勒电路，输入信号X1，X2，输出信号Z。

2）求触发器激励函数：J=X1X2，K =X 1X2触发器次态方程：Q n+1=X1X 2Q n +X 1X2Q n=X1X 2Q n+(X1+X2)Q n电路输出方程：Z = X 1X2Q n+X 1X 2Q n +X1X 2Q n+X1X2Q n3)状态转移表：表6.3.1输入X1X2S(t)Q nN(t)Q n+1输出Z0 0 0 0 0 10 11 0 1 0 1 1 1 101111111111114)X1X2Q n为低位来的进位，Q n+1表示向高位的进位。

且电路每来一个CP，实现一次加法运算，Z为本位和，Q 在本时钟周期表示向高位的进位，在下一个时钟周期表示从低位来的进位。

例如X1=110110，X2=110100，则运算如下表所示：LSB MSB表6.3.2节拍脉冲CP CP1 CP2 CP3 CP4 CP5 CP6 CP7被加数X10 1 1 0 1 1 0加数X20 0 1 0 1 1 0低位进位Q n0 0 0 1 0 1 16.2 试作出101序列检测器的状态图，该同步电路由一根输入线X，一根输出线Z，对应与输入序列的101的最后一个“1”，输出Z=1。

其余情况下输出为“0”。

（1）101序列可以重叠，例如：X：010101101 Z：000101001（2）101序列不可以重叠，如：X：010******* Z：0001000010解：1）S0：起始状态，或收到101序列后重新检测。

S1：收到序列“1”。

S2：连续收到序列“10”。

0/01/0X/Z0/011…100…S2S1S1/00/01/12）0/01/0X/Z0/011…100…S2S1S1/00/01/1解：（1）列隐含表：A B CDCB×A B CDCB×ADBC××(a)(b)进行关联比较得到所有的等价类为：AD，BC。

数字电路与系统试卷及答案

一、填空填（共14分）1．最简与或表达式的标准是。

2．和普通多谐振荡器相比，石英警惕振荡器的突出优点是。

3．当基极电流大于临界饱和基极电流时，三极管工作在状态，这时，集电极与发射极间相当于开关；当基极与发射机间的电压小于0时，三极管工作在状态，这时，集电极与发射极间相当于开关。

4．时序逻辑电路的特点是其输出不仅取决于当时的信号，而且还与电路的状态有关。

5．二进制全译码器很适合用来实现多输出逻辑函数，是因为它的输出为。

6．A/D 转换分为、、、 4步完成。

二、选择题（共15分）在以下各题中，选择正确的答案填入括号中。

1．在下列TTL 门电路中，Y =A 的是（）YA 1YA 0Y（a ）（b ）（c ）2．数据选择器很适合用以实现单输出逻辑函数，因为它的输出是（） (a)全体最小项的和（b ）全体最小项的积（c ）最小项的差 3．接通电源电压就能输出矩形脉冲的电路是（）（a ）单稳态触发器（b ）施密特触发器（c ）多谐振荡器（d ）触发器4．在下列电路中，时序电路为（）（a ）编码器（b ）译码器（c ）计数器（d ）加法器5．和异步计数器相比，同步计数器的优点是（）（a ）工作速度高（b ）触发器数少（c ）电路很简单（d ）不需要统一的CP三、写出图(a)所示电路的输出表达式，并根据图(b)给出的输入A 、B 的波形画出输出Y 的波形。

（8分）AB Y（a ）（b ）四、化简下列逻辑函数与最简与或表达式（方法不限）（16分）1．Y=A+B AD CD B •++ 2．Y=BC D C A B A C A +++五、用输出低电平有效的3线—8线译码器和门电路实现逻辑函数，并写出具体步骤。

（15分）Y=AB+BC+AC六、用同步二进制加法计数器CT74LS161和门电路构成十二进制计数器，并写出设计步骤。

CT74LS161的功能表如下。

数字集成电路设计与系统分析答案

懂得1、Please illustrate the meaning of its voltage transfer characteristic to a logic gate, and describe the static behaviors showed in the voltage transfer characteristic curves.The electrical function of a gate is best expressed by its voltage transfer characteristic (VTC),which plots the output voltage as a function of the input voltage Vout=f(Vin).The high and low nominal voltage Voh and Vol;The gate or switching threshold voltage Vm,that is define as Vm=f(Vm)(The gate threshold voltage presents the midpoint of the switching characteristics,which is obtained when the output of a gate is short circuited to the input);The high and low input voltage Vih and Vil are defined by the point where the gain (=dVout/dVin)of the VTC equals -12、Please draw the voltage transfer characteristic curve of the inverter and label the static operation points in the VTC.3、Please describe the definition of noise margin and its physical significance(物理意义), then draw the figure of definition of noise margins.The noise margins represent the levels of noise that can be sustained(所允许的) when gates are cascaded. A measure of the sensitivity of a gate to noise is given by the noise margins NML(noise margin low) and NMH(noise margin high), which quantize the size of the legal “0” and “1”, respectively, and set a fixed maximum threshold on the noise value4、Please describe the meaning of the regenerative property and the conditions of a gate with regenerative property.A gate with regenerative property ensures that a disturbed signal converges back to a nominal voltage level after passing through a number of logical stages. The VTC should have a transient region (or undefined region) with a gain greater than 1 in absolute value, bordered by the two legal zones, where the gain should be less than 1 in absolute value5、What are the definitions of the fan-out and fan-in properties?The number that can be driven is termed the fan-out of circuit, that denotes the number of load gates N that are connected to the output of the driving gate. The fan-in of a gate is defined as the number of independent input nodes to the gate.6、How to describe the performance of a digital IC? Please illustrate the parameters used to characterize the transient performance of a logic family, and draw the associated figure of the definition of these parP ropagation delay time and rise/fall time can be used to characterize the transient performance of a logic family .Propagation delay time of a gate expresses the delay experienced by a signal when passing through a gate,which represent how quickly the gate responds to the changes at its inputs.Rise/fall time express how fast a signal transits between the different levels. Propagation delay time is defined as the period between the 50%transition points of the input and output signals.Rise/fall time is defined as the period between the 10% and 90% points of the total voltage transition at the output waveforms.1、Illustrate the basic structure and simple operation principle of MOS transistor.Four terminals:source, drain, gate, body; Vertical Structure: gate electrode, insulator, semiconductor substrate; Horizontal Structure: source region, channel region, drain region2、Illustrate the basic function of each terminal of MOS device, and describe the general terminal connections of NMOS and PMOS transistor, respectively.The source and the drain are the electrodes conducting the current. The gate electrode is thecontrolling terminal. The function of the body is secondaryIn NMOS devices, the source is defined as the n+ region which has a lower potential(电势) than the other n+ region, the drain. The source is the terminal with the higher potential in PMOS devices, The body is generally connected to a DC supply that is identical for all devices of the same type (GND for NMOS, VDD for PMOS).3、What does the transition (or input) characteristic of MOS transistor mean? And what conclusions we can find from the characteristic curve?It describes the relationship between the gate-source voltage and the drain-source current with the certain drain-source voltage .When the gate-source voltage is less than the threshold voltage, the conducting current is zero, that is, the NMOS transistor is in cutoff operation. When is larger than, the NMOS transistor is on.4、What does the current-voltage (or output) characteristic of MOS transistor mean? And what conclusions we can find from the I-V characteristic curve?.It describes the relationship between the drain-source voltage and the drain-source current with a certain gate-source voltageVgs > Vt , 0<VDS <VGS -VT : Linear modeThe inversion layer forms a continuous current path between the source and the drain.A drain current proportional to Vds will flow from the drain to the source through the conducting channel. The channel region acts as a voltage-controlled linear resister.5、Describe the operation modes of NMOS and PMOS transistors respectively, and define the corresponding ideal current equations.1、Explain the channel-length modulation, sub-threshold conduction, short-channel effect and narrow-channel effect. And illustrate their corresponding chief impacts on the device.This simple current equation prescribes a linear drain-bias dependence for the current in MOS transistors, determined by the empirical model parameter λ, called the channel-length modulation coefficientOne typical condition, which is due to the two-dimensional nature of channel current flow, is the sub-threshold conduction in small-geometry MOS transistors.As a working definition, a MOS transistor is called a short-channel device if its channel length is on the same order of magnitude as the depletion region thicknesses of the source and drain junctions.The short-channel effects that arise in this case are attributed to two physical phenomena: the limitations imposed on electron drift characteristics in the channel; the modification of the threshold voltage due to the shortening channel lengthMOS transistor that have channel widths on the same order of magnitude as the maxium depletion region thickness are defined as narrow channel devices.For MOSFET with small channel widths,the actual threshold voltage increases as a result of this extra depletion charge of the fringe depletion region.This fact is called narrow channel effect.2、Describe the three main components of the load capacitanceCL, when a logic gate is driving other fan-out gates. And sketch the capacitance model of NMOS transistor.Gate capacitances (of other inputs connected to out)Diffusion(or junction) capacitances (of drain/source regions)Routing capacitances (output to other inputs)1,Describe the basic structure and operation of a static CMOS inverter. Then draw theassociated transistor schematicThis structure consists of an enhancement-type NMOS transistor and an enhancement-type PMOS transistor, operating in complementary mode. So this configuration is called Complementary MOS (CMOS). The gate terminals of the PMOS and NMOS transistors are connected to form the inverter input. The drain terminals of the PMOS and NMOS transistors are connected to form the inverter output. The source and the substrate of the NMOS transistor are connected to the ground, while the source and body of PMOS transistor are connected to VDD The circuit topology is complementary push-pull in the sense that: For high input the NMOS transistor drives (pulls down) the output node while the PMOS transistor acts as the load, and for low input the PMOS transistor drives (pulls up) the output node while the NMOS transistor acts as the load.When the input is at VDD: The NMOS is on (conducting) while the PMOS is off (cut-off). A direct path exists between Vout and the ground node, resulting in a steady-state value of 0V at the output. When the input is at ground:The NMOS is off while the PMOS is on. A direct path exists between VDD and Vout, yielding a high output voltage (equal to VDD).Static CMOS logic:structure:The static CMOS style is really an extension of the static CMOS inverter to multiple inputs. A logic function in static CMOS must be implemented in both NMOS and PMOS transistors. It is the combination of the pull-up network(PUN) and the pull-down network(PDN). Each input always connects to PUN and PDN simultaneously. The function of the PUN is to provide a connection between the output and VDD anytime the output of the logic gate is meant to be 1 (based on the inputs). The function of the PDN is to connect the output to VSS when the output of the logic gate is meant to be 0.Opreation: The pull-down net should be “on” when the pull-up net is “off” and vice versa. For any given input combination, the output is connected either to VDD or to ground via a low-resistance path. A DC current path between the VDD and ground is not established for any of the input combinations. With the complementary nature of NMOS and PMOS, the pull-up or the pull-down is “on” alternately to implement the logic operation.Discuss the main problems for high fan-in static CMOS gates and the associated techniques for fast complex gates.tpHL = 0.69 Reqn(C1+2C2+3C3+4CL); Propagation delay deteriorates(恶化) rapidly as a function of fan-in quadratically in the worst case, Gates with a fan-in greater than 4 become excessively slow and must be avoided.tPLH increases linearly due to the linearly increasing value of the diffusion capacitance;tPHL increase quadratically due to the simultaneous increase the resistance and internal capacitance in serial part.Transistor sizing: as long as fan-out capacitance dominatesProgressive transistor sizing: This approach reduces the dominant resistance, while keeping the increase in capacitance within boundsTransfer gate:Configuration:The source and drain nodes serve as inputs and outputs, while the gate node serves as the control input, the body node is connected to the power/ground Operation: For NMOS transfer gate,it turns on while the gate control terminal goes high, and the input signal will be delivered to the output node; it turns off while the gate control terminal goes low, and the output node will be impedance.CMOS transmission gate:Configuration: The CMOS transmission gate consists of one NMOS and one PMOS transistor, with the source and drain connected in parallel; The gate voltages appliedto these two transistors are also set to be complementary signals. The substrate terminal of the NMOS transistor is connected to ground and the substrate terminal of the PMOS transistor is connected to Vdd.Operation: If the control signal C is logic-high (equal to Vdd), then both transistors are turned on and provide a low-resistance current path between the input and output nodes. If the control signal C is logic-low, then both transistors will be off, and the path between the input and output nodes will be in the high-impedance state. The weakness of one device is overcome by the strength of the other device, whether the output is transmitting a high or low value. This is a clear advantage of the CMOS transfer gate over the single transistor counterpart.DCVLS:Operation: Assume now that, for a given set of inputs, PDN1 conducts while PDN2 does not, and that Out and out are initially high and low, respectively. Turning on PDN1: Causes Out to be pulled down (below VDD−|VTP |); Out is in a high impedance state, as M2 and PDN2 are both turned off. At the point M2 turns on and starts charging out非to VDD — eventually turning off M1; This in turn enables Out to discharge all the way to GND.XOR/XNOR: When the signals A and B have the same values, there is one conducting path either AB or A非B非; Then the output F is pulled down;At the same time, the other pull-down paths connected to the F非are both turned off. When F is pulled down below VDD−|VTP |, M2 t urns on and starts charging F非to VDD —eventually turning off M1 and pulling down F to Gnd. When the signals A and B have the different values, there is one conducting path either AB非or A非B; Then the output F非is pulled down; At the same time, the other pull-down paths connected to the F are both turned off. When F非is pulled down below VDD−|VTP |, M1 turns on and starts charging F to VDD —eventually turning off M2 and pulling down F非to Gnd.Precharge-Evaluate dynamic CMOS:Operation: Precharge (when the clock signal Φ= 0)：The PMOS precharge transistor MP is conducting while the complementary NMOS transistor MN is off. The output load capacitance is precharged to VDD by MP, then VOH=VDD；The input voltages have no influence yet upon the output level since the complementary NMOS transistor MN is off. Evaluate (when the clock signal Φ=1)：The precharge transistor MP turns off while the NMOS evaluate transistor MN turns on. The output node voltage may now remain at the logic-high level or drop to a logic low, depending on the input voltage levels: If the input signals create a conducting path between the output node and the ground, PDN is on, and the output capacitance will discharge toward VOL=0;Otherwise, when PDN is off, the output voltage remains at VOH= VDD.Domino dynamic CMOS logic:When Φ=0, during precharge: The output of the n-type dynamic gate is charged up to VDD, and the output of the inverter is set to 0. When Φ=1, during evaluation: The dynamic gate conditionally discharges, and there are two possibilities: The output node of the dynamic CMOS stage is either discharged to a low level through the NMOS circuitry (1 to 0 transition), or it remains high. Consequently, the inverter output voltage can also make at most one transition during the evaluation phase, from 0 to 1.TSPC dynamic CMOS logic:Configuration:If one constrains a NORA stage to have only n-precharge gates, and not static gates, then a p-channel transistor can be eliminated from the clocked latch; The dynamic circuit technique to be presented in that it uses only one-phase clock signal, so no clock skew problem exists. The NORA design style can be simplified so that a single clock is sufficient. For the doubled n-C2MOS latch, when φ= 1, the latch is in the transparent evaluate mode and corresponds to 2 cascaded inverters (non-inverting); For the doubled n-C2MOS latch, when φ= 0, both inverters are disabled (hold mode) -- only the pull-up network is still active.Pipelined NORA dynamic CMOS system:Configuration: Consists of an np-CMOS logic sequence and a clocked CMOS output buffer; A pipelined system can be constructed by simply cascading alternating φ-section and φ -section, meaning that evaluation occurs during active φ and φ respectively;Operation:φ=0, during hold mode :N block performs the precharge operation and pulls node Out1 up to VDD through the p-type device Mp1, while p block performs the discharge operation and pulls the node Out2 down to zero through the n-type device Mn2; The clocked CMOS latch will not be in operation and the previous output voltage will be stored on the output load capacitor CL. φ=1, during evaluate mode:All cascaded NMOS and PMOS blocks evaluate output levels one after the other, and then the signal Out2 will be inversed to the output node by the clocked CMOS latch in operation;Operation Mode: Evaluate―Hold: All logic stages perform the precharge-discharge operation when the clock is high, and all stages evaluate output levels when the clock is low. Therefore, wewill call this circuit a section, meaning that evaluation occurs during active .Clocked CMOS dynamic circuit:Basic Structure:A pair of PMOS and NMOS transistors controlled by the complementary clock signals are cascaded in the pullup and pulldown paths of the static CMOS gate, respectively, then a CMOS logic gate can be synchronized with a clock. Operation: φ=1, during evaluation mode：The transistors Mp1 and Mp2 are both turned on, then this gate can evaluate normally as a CMOS inverter to generate the logic output In非; φ=0 , during hold mode: Both transistors Mp1 and Mp2 are off, decoupling the output from the input. The CMOS circuit cannot conduct and evaluate, then the output Q retains its previous value stored on the output capacitor CL.Sequential logic:Virtually all useful systems require storage of state information, leading to another class of circuits called sequential logic circuits. In these circuits, the output not only depends upon the current values of the inputs, but also upon preceding output values. In other words, a sequential circuit remembers some of the past history of the system; A sequential circuit consists of a combinational circuit and a memory block in the feedback loop.Combination logic:In all logic circuits described so far, the output is directly related to the input. Typically, there are no feedback loops between the output and the input in these circuits (also classified as non-regenerative circuits), so the outputs are always a logical combination of the inputs. As a class, these circuits are known as combinational logic circuits. Combinational logic circuits, described earlier, have the property that the output of a logic block is only a function of the current input values, assuming that enough time has elapsed for the logic gates to settle. Static storage:preserve state as long as the power is on;are built using positive feedback or regeneration with an intentional connection between the output and the input;useful when updates are infrequent (clock gating)Dynamic storage:store state on parasitic capacitors;only hold state for short periods of time (milliseconds);require periodic refresh to annihilate charge leakage;usually simpler, so higher speed and lower power;useful in datapath circuits that require high performance levels and are periodically clockedLatch: level sensitive circuit that passes inputs to Q when the clock is high (or low);input sampledon the falling edge of the clock is held stable when clock is low (or high)Register or Flip-flops (edge-triggered): edge sensitive circuits that only sample the inputs on a clock transitionpositive edge-triggered: 0- 1negative edge-triggered: 1 -0built using latches (e.g., master-slave flip-flops)。

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第一章习题1-1 例1.2.12中转换前后两个数的绝对值哪个大？为什么？答：转换前大。

因为转换后舍去了后边的小数位。

1-2 将下列二进制数分别转换为八进制数、十六进制数和十进制数。

11001101.101，10010011.1111解：(11001101.101)2 =(11 001 101.101)2= ( 315.5)8=(1100 1101.1010)2 =( CD.A)16=(128+64+8+4+1+0.5+0.125)10=(205.625)10(10010011.1111)2 =(1001 0011.1111)2= (93.F)16=(10 010 011.111 100)2 =( 223.74)8=(128+16+2+1+0.5+0.25+0.125+0.0625)10=(147.9375)101-3 将下列十进制数转换为二进制、八进制和十六进制数。

121.56，73.85解：1. 0Å1Å3Å7Å15Å30Å60Å121 0.56Æ0.12Æ0.24Æ0.48Æ0.96Æ0.921 1 1 1 0 0 1 1 0 0 0 1所以：（121.56）10=(1111001.10001)2=(171.42)8=(79.88)162. 0Å1Å2Å4Å9Å18Å36Å73 0.85Æ0.7Æ0.4Æ0.8Æ0.6Æ0.2Æ0.41 0 0 1 0 0 1 1 1 0 1 1 0（73.85）10=(1001001.11011)2=(111.66)8=(49.D8)161-4 将下列十六进制数转换为二进制、八进制和十进制数。

89.0F，E5.CD解：(89.0F)16=(10001001.00001111)2=(211.036)8=(8*16+9+15/256)10=(137. 0.05859375)10 1-5 试求例1.2.17的转换误差，比较例1.2.12的转换误差，哪个大？为什么？答：例1.2.12的误差大。

例1.2.17实际上转换了15位二进制小数，而例1.2.12只转换了5位。

1-6 用十六位二进数表示符号数。

试分别写出原码、反码和补码可表示的数值范围。

解：原码 –(215-1) ~ +(215-1)；反码 –(215-1) ~ +(215-1)；补码 –215 ~ +(215-1)1-7 设n=8，求下列二进制数的反码：101101，-101101，10100，-10100解：先补齐8位，再求反；正数的反码是原码，负数的反码需求反。

(101101)反=00101101(-101101)反=11010010(10100)反=00010100(-101101)反=111010111-8 设n=8，求下列二进制数的补码：101101，-101101，10100，-10100，101.001，-101.001解：先补齐8位，再求补；正数的补码是原码，负数的补码需求补。

(101101)补=00101101(-101101)补=11010011(10100)补=00010100(-101101)补=11101100(101.001)补=00000101.001(-101101)补=11111010.1111-9 为什么将N求反加1即为N的补码？答：（N）补=2n-N=(2n-1-N)+12n-1为n位全1。

(2n-1-N)为N的反码。

再加1即得补码。

得证。

1-10 试证明利用补码进行加减运算的正确性。

证明：设有两个n位正数N1、N2，则-N1、-N2的补码分别为2n-N1和2n-N2。

在n位加法器中进行加减运算时共有如下四种情况：①N1+N2 就是两个正数相加，结果为正数；②N1-N2=N1+（2n-N2）= 2n-（N2- N1），结果取决于N2-N1的符号：如果N2>N1,则结果为负数，2n-（N2- N1）就是-（N2- N1）的补码；如果N2< N1,则结果为2n+（N1-N2），由于N1-N2>0，而2n为第n-1位的进位，位于第n位（n位运算器的最位位为第n-1位）上，在n位运算器之外，所以结果为N1-N2，是正数；③N2-N1，结果与N1-N2类似；④-N1-N2=（2n-N1）+（2n-N2）=2n+[2n -（N1+N2）]，其中第1个2n为第n-1位的进位，位于在第n位上，在n位运算器之外，舍去不管；而[2n-(N1+N2)]就是负数-(N1+N2)的补码。

由此就证明了用补码进行加减运算的正确性。

1-11 设A=65，B=56，n=8。

试用补码求下列运算，并验证其结果是否正确：A+B，A-B，-A+B，-A-B解：(A)补=01000001 (-A)补=10111111 (B)补=00111000 (-B)补=11001000A+B A-B -A+B -A-B1011111101000001 01000001 10111111+ 00111000 + 11001000 + 00111000 + 1100100001111001 100001001 11110111 110000111 所以：A+B=01111001，A-B=00001001，-A+B=11110111，-A-B=10000111 A+B=121 A-B=9 -A+B=-9 -A-B=-121结果正确。

1-12设A=65，B=75，n=8。

试用补码求下列运算，并验证其结果是否正确：A+B，A-B，-A+B，-A-B如果结果有错，为什么？解：(A)补=01000001 (-A)补=10111111 (B)补=01001011 (-B)补=10110101A+B A-B -A+B -A-B1011111101000001 01000001 10111111+ 01001011 + 10110101 + 01001011 + 1011010110001100 11110110 100001010 101110100 所以：A+B=10001100，A-B=11110110，-A+B=00001010，-A-B=01110100 A+B=-116 A-B=-10 -A+B=+10 -A-B=+116 结果错正确正确错原因：65+75=140，超出了8位运算器所能表示的范围。

1-13 如何判断补码运算有无溢出？答：当第n-1位（符号位）和第n-2位（最高数字位）不同时无进位（两正数相加）或不同时有进位（两负数相加）时，有溢出错误发生。

可用异或门进行检测。

1-14 试分别写出下列十进制数的8421、5421、2421和余三码。

325，108，61.325解：（325）10=(0011 0010 0101)8421=(0011 0010 1000)5421=(0011 0010 1011)2421=(0110 0101 1000)余3(108)10=(0001 0000 1000)8421=(0001 0000 1011)5421=(0011 0000 1110)2421=(0100 0011 1011)余3(61.325)10=(0110 0001.0011 0010 0101)8421=(1001 0001.0011 0010 1000)5421=(1100 0001.0011 0010 1011)2421=(1001 0100.0110 0101 1000)余31-15 完成下列BCD码运算：（001110010001）8421BCD+（010*********）8421BCD=？解：（0011 1001 0001）8421BCD+（0101 1000 0010）8421BCD=（1001 0111 0011）8421BCD 其中第二位 1001+1000=1 0001，结果大于10。

此时要加6，所以结果为1 0111。

1-16 写出对应下列二进制数的格雷码1010，1101解：利用由B到G的关系式（异或）：B 1010 11011011G 11111-17 写出对应下列格雷码的二进制数1010，1101解：利用G由到B的关系式（异或）：G 1010 1101B 1100 10011-18 写出“Hello everyone”的ASCII编码，分别用二进制和十六进制。

解：由ASCII表得：48 65 6C 6C 6F 20 65 76 65 72 79 6F 6E 651-19 设要用奇偶校验码传送ASCII字符串“BIT”，试分别写出其奇校验码和偶校验码。

在这种情况下传输效率降低了多少？解：B：P100 0010 奇：1100 0010 偶：0100 0010I： P1001001 奇：0100 1001 偶：1100 1001T：P1010101 奇：1101 0101 偶：0101 0101传输效率降低了1/8=12.5%.1-20 设发送端发送的奇偶校验码为101100110，而在接收端收到的码元序列为①111100110，②101010110。

问本例中采用的是奇校验还是偶校验？接收结果①、②中哪个是对的？哪个是错的？为什么？答：因为发端数据是1 0110 0110，有5个1，所以是奇校验；两个接收数据都是错的：前者可由奇偶特性知道；后者错了两位，奇偶码不能将其检出。

1-21 用二维奇偶纠错码去纠错，有无可能纠正所有的错误？若不能，什么情况下不能？试列出不能纠错的情况并说明原因。

答：不能。

如图所示情况就不能纠正。

因为出错的行列均有偶数个错。

2-1举出现实生活中的一些相互对立的、处于矛盾状态的事物。

试着给这些对立的事物赋予逻辑“0”和逻辑“1”。

2-2为什么称布尔代数为“开关代数”？2-3基本逻辑运算有哪些？写出它们的真值表。

答：与、或、非。

2-4什么是逻辑函数？它与普通代数中的函数在概念上有什么异同？答：由只能取值为“1”、“0”的自变量构成的，各自变量之间由各种逻辑关系组成的逻辑表达式，被称为逻辑函数。

逻辑函数与普通函数的区别为：逻辑自变量的取值范围和逻辑因变量的值阈均只能是“1”、“0”两值。

2-5如何判定两个逻辑函数的相等？2-6逻辑函数与逻辑电路的关系是什么？答：逻辑电路是能完成某一逻辑运算的电子线路，而逻辑函数可以描述该电路的逻辑功能。

2-7什么是逻辑代数公理？逻辑代数公理与逻辑代数基本定律或定理的关系是什么？2-8用真值表证明表2.3.2中的“0-1律”，“自等律”，“互补律”，“重叠律”和“还原律”。