EDA期末考试题02(最新整理)

三、VHDL 程序填空：（10 分）以下程序是一个BCD 码表示0～99 计数器的VHDL 描述，试补充完整。

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt100b isport( clk, rst, en : in std_logic;cq : out std_logic_vector(7 downto 0); -- 计数输出cout: out std_logic); -- 进位输出end entity cnt100b;architecture bhv of cnt100b isbeginprocess (clk, rst, en)variable cqi : std_logic_vector(7 downto 0);beginif rst = '1' thencqi := (others => ‘0’); -- 计数器清零复位elseif clk’event and clk = ‘1’then -- 上升沿判断if en = '1' thenif cqi(3 downto 0) < "1001" then -- 比较低4位cqi := cqi + 1; -- 计数加1elseif cqi(7 downto 4) < "1001" then -- 比较高4位cqi := cqi + 16;elsecqi := (others => '0');end if;cqi (3 downto 0) := “0000”; -- 低4位清零end if;end if;end if;end if;if cqi = “10011001”then -- 判断进位输出cout <= '1';elsecout <= '0';end if;cq <= cqi;end process;end architecture bhv; 1.在程序中存在两处错误，试指出，并说明理由：在Quartus II 中编译时，其中一个提示的错误为：第9 行，状态机数据类型声明错误，关键字应为TYPE第32 行，case 语句缺少when others 处理异常状态情况2.修改相应行的程序（如果是缺少语句请指出大致的行数）：错误1 行号：9 程序改为：SIGNAL 改为TYPE错误2 行号：32 程序改为：之前添加一句when others => c_st <= st0;Error (Line 9): VHDL syntax error at MOORE1.vhd(9) near text "IS"; expecting ":", or ","四、VHDL 程序改错：（10 分）仔细阅读下列程序，回答问题LIBRARY IEEE; -- 1 USE IEEE.STD_LOGIC_1164.ALL; -- 2 ENTITY MOORE1 IS -- 3 PORT ( DATAIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- 4 CLK, RST: IN STD_LOGIC; -- 5Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); -- 6 END MOORE1; -- 7 ARCHITECTURE BEHAV OF MOORE1 IS -- 8 SIGNAL ST_TYPE IS (ST0, ST1, ST2, ST3, ST4); -- 9 SIGNAL C_ST : ST_TYPE; -- 10 BEGIN -- 11 PROCESS (CLK, RST) -- 12 BEGIN -- 13 IF RST = '1' THEN C_ST <= ST0; Q <= "0000"; -- 14ELSIF CLK'EVENT AND CLK = '1' THEN -- 15 CASE C_ST IS -- 16 WHEN ST0 => IF DATAIN = "10" THEN C_ST <= ST1; -- 17ELSE C_ST <= ST0; -- 18END IF; Q <= "1001"; -- 19 WHEN ST1 => IF DATAIN = "11" THEN C_ST <= ST2; -- 20ELSE C_ST <= ST1; -- 21END IF; Q <= "0101"; -- 22 WHEN ST2 => IF DATAIN = "01" THEN C_ST <= ST3; -- 23ELSE C_ST <= ST0; -- 24END IF; Q <= "1100"; -- 25 WHEN ST3 => IF DATAIN = "00" THEN C_ST <= ST4; -- 26ELSE C_ST <= ST2; -- 27END IF; Q <= "0010"; -- 28 WHEN ST4 => IF DATAIN = "11" THEN C_ST <= ST0; -- 29ELSE C_ST <= ST3; -- 30END IF; Q <= "1001"; -- 31 END CASE; -- 32 END IF; -- 33 END PROCESS; -- 34 END BEHAV; -- 35五、阅读下列 VHDL 程序，画出相应ＲＴＬ图：（10 分）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY TRIS ISPORT ( CONTROL : IN STD_LOGIC;INN : IN STD_LOGIC;Q : INOUT STD_LOGIC;Y : OUT STD_LOGIC );END TRIS;ARCHITECTURE ONE OF TRIS ISBEGINPROCESS (CONTROL, INN, Q)BEGINIF (CONTROL = '0') THENY <= Q;Q <= 'Z';ELSEQ <= INN;Y <= 'Z';END IF;END PROCESS;END ONE;六、写 VHDL 程序：（20 分）1.试描述一个带进位输入、输出的8 位全加器端口：A、B 为加数，CIN 为进位输入，S 为加和，COUT 为进位输出LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ADDER8 ISPORT (A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);CIN : IN STD_LOGIC;COUT : OUT STD_LOGIC;S : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );END ADDER8;ARCHITECTURE ONE OF ADDER8 ISSIGNAL TS : STD_LOGIC_VECTOR (8 DOWNTO 0);BEGINTS <= (‘0’ & A) + (‘0’ & B) + CIN;S <= TS(7 DOWNTO 0);COUT <= TS(8);END ONE;2.看下面原理图，写出相应VHDL 描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MYCIR ISPORT (A, CLK : IN STD_LOGIC; C,B : OUT STD_LOGIC );END MYCIR;ARCHITECTURE BEHAV OF MYCIR ISSIGNAL TA : STD_LOGIC;BEGINPROCESS (A, CLK)BEGINIF CLK’EVENT AND CLK = ‘1’ THENTA <= A;B<= TA;C<= A AND TA;END IF;END PROCESS;END BEHAV;七、综合题（20 分）下图是一个A/D 采集系统的部分，要求设计其中的FPGA 采集控制模块，该模块由三个部分构成：控制器（Control）、地址计数器（addrcnt）、内嵌双口RAM（adram）。

控制器（control）是一个状态机，完成AD574的控制，和adram 的写入操作。

adram 是一个LPM_RAM_DP 单元，在wren 为’1’时允许写入数据。

试分别回答问题FPGA采集控制下面列出了 AD574 的控制方式和控制时序图：AD574 逻辑控制真值表（X 表示任意）CE CS RC K12_8 A0 工作状态0 X X X X 禁止X 1 X X X 禁止1 0 0 X 0 启动12 位转换1 0 0 X 1 启动8 位转换1 0 1 1 X 12 位并行输出有效1 0 1 0 0 高8 位并行输出有效1 0 1 0 1 低4 位加上尾随4 个0 有效2.试画出control 的状态机的状态图3.地址计数器每当ClkInc 时钟上升沿到达，输出地址加1，请对该模块进行VHDL 描述。

Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity cnt64 isPort ( ClkInc, Cntclr : in std_logic; -- 时钟信号和清零信号输入Wraddr : out std_logic_vector (5 downto 0) );End cnt64;问题：AD574 工作时序Architecture one of cnt64 isBeginProcess (clkinc, cntclr)Variable counter : std_logic_vector (5 downto 0);BeginIf cntclr = ‘1’ then counter := (others => ‘0’);Elsif clkinc = ‘1’ and clkinc’event then counter := counter + 1;1. 要求AD574 工作在8 位转换模式，K12_8、A0 在control 中如何设置？K12_8 低电平A0 高电平End if;Wraddr <= counter;End process;End one;信号预处理放大采样/保持ADData 8STATUS8rddata adram（lpm_ram_dp）8AD574wrenCS 1rddatardaddr6AnalogIn CEA0RCK12_8Control6 wraddrClkInc地址计数器Cntclr CLK4.根据状态图，试对control 进行VHDL 描述Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity control isPort ( CLK, STATUS : in std_logic; -- 时钟信号和AD转换状态信号输入ADDATA : in std_logic_vector (7 downto 0); -- 转换数据输入CS, CE, A0, RC, K12_8 : out std_logic; -- AD574控制信号ClkInc : out std_logic; -- 地址计数器时钟信号rddata : out std_logic_vector (7 downto 0) ); -- 转换数据输出End control;Architecture behave of control isType sm_state is (s0, s1, s2, s3, s4);Signal c_st, n_st : sm_state;Signal lock : std_logic;Signal regdata : std_logic_vector(7 downto 0);BeginK12_8 <= ‘0’;A0 <= ‘1’;Process (clk)If clk’event and clk =‘1’ then c_st <= n_st; end if;End process;Process (c_st, status)BeginCase c_st isWhen s0 => n_st <= s1; rc <= ‘1’; ce <= ‘0’; cs <= ‘1’; lock <= ‘0’;When s1 => n_st <= s2; rc <= ‘0’; ce <= ‘1’; cs <= ‘0; lock <= ‘0’;When s2 => if status = ‘0’ then n_st <= s3; else n_st <=s2;Rc <= ‘1’; ce <=‘1’ cs <= ‘0’; lock <= ‘0’;When s3 => n_st <= s4; rc <= ‘1’; ce <= ‘1’; cs <= ‘0’; lock <= ‘1’;When s4 => n_st <= s0; rc <= ‘1’; ce <= ‘1’; cs <= ‘0’; lock <= ‘0’;When others => n_st <= s0;End case;End process;Process (lock)BeginIf lock’event and lock = ‘1’ thenRegdata <= addata;Clkinc <= ‘1’;ElseClkinc <= ‘0’;End if;End process;Rddata <= regdata;End behave;5.已知adram 的端口描述如下ENTITY adram ISPORT( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 写入数据wraddress: IN STD_LOGIC_VECTOR (5 DOWNTO 0); -- 写入地址rdaddress: IN STD_LOGIC_VECTOR (5 DOWNTO 0); -- 读地址wren : IN STD_LOGIC := '1'; -- 写使能q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) -- 读出数据);END adram;试用例化语句，对整个FPGA 采集控制模块进行VHDL 描述Library ieee;Use ieee.std_logic_1164.all;Use ieee.std_logic_unsigned.all;Entity ADC574 isPort ( CLK, STATUS : in std_logic; -- 时钟信号和AD转换状态信号输入ADDATA : in std_logic_vector (7 downto 0); -- 转换数据输入Cntclr : in std_logic; -- 计数器清零信号Rdaddr : in std_logic_vector (5 downto 0); -- adram读数地址CS,CE, A0, RC, K12_8 : out std_logic; -- AD574控制信号rddata : out std_logic_vector (7 downto 0) ); -- adram读数据输出End ADC574;Architecture one of adc574 iscomponent cnt64Port ( ClkInc, Cntclr : in std_logic; -- 时钟信号和清零信号输入Wraddr : out std_logic_vector (5 downto 0) );End component;component controlPort ( CLK, STATUS : in std_logic; -- 时钟信号和AD转换状态信号输入ADDATA : in std_logic_vector (7 downto 0); -- 转换数据输入CS, CE, A0, RC, K12_8 : out std_logic; -- AD574控制信号ClkInc : out std_logic; -- 地址计数器时钟信号rddata : out std_logic_vector (7 downto 0) ); -- 转换数据输出End component;component adramPORT (data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- 写入数据wraddress: IN STD_LOGIC_VECTOR (5 DOWNTO 0); -- 写入地址rdaddress: IN STD_LOGIC_VECTOR (5 DOWNTO 0); -- 读地址wren : IN STD_LOGIC := '1'; -- 写使能q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) -- 读出数据);END component;Signal r_data : std_logic_vector (7 downto 0);Signal clkinc : std_logic;Signal wraddr : std_logic_vector (5 downto 0);BeginU1 : cnt64 port map (clkinc => clkinc, cntclr => cntclr, wraddr => wraddr);U2 : control portmap (clk => clk, status => status, addata => addata, cs => cs, ce => ce, a0 => a0, rc => rc, k12_8 => k12_8, clkinc => clkinc, rddata => r_data);U3 : adram port map (data => r_data, wraddress => wraddr, rdaddress => rdaddr, wren => ‘1’, q => rddata);End one;“”“”At the end, Xiao Bian gives you a passage. Minand once said, "people who learn to learn are very happy people.". In every wonderful life, learning is an eternal theme. As a professional clerical and teaching position, I understand the importance of continuous learning, "life is diligent, nothing can be gained", only continuous learning can achieve better self. Only by constantly learning and mastering the latest relevant knowledge, can employees from all walks of life keep up with the pace of enterprise development and innovate to meet the needs of the market. This document is also edited by my studio professionals, there may be errors in the document, if there are errors, please correct, thank you!。