数字设计课件第七章时序逻辑设计原理

inputs, but also on the past sequence of time, possibly arbitrarily far back in time.
Inputs
Combinational
Storage
Logic
Elements
Next
State
State
Outputs
2
Chapter 7
12
Chapter 7
2、S-R latch
• built with NAND
gates
S_L S Q Q R_L R Q Q_L
S_L 、R_L: active low signals
S_L R_L Q Q_L
0
0
1
1 forbidden
0
1
1
0 set
1
0
0
1 reset
1
1
Last lastQ Q _L hold
H
level
L
coordinate by signal rising edge or falling edge
• clocked synchronous state machine
all memory of the sequential circuit changes only on a clock edge or signal level.
ddpp
Chapter 7 sequential logic design
principles
•state, state variable •latches, flip-flops •analysis •synthesis
sequential circuit
• the outputs depend not only on its current
the stored bit is present on the output Q.
9
Chapter 7
进入亚 稳态
10
Chapter 7
(2) minimum pulse width
S
propagation delay is exist when a transition on S or R input produce a transition on an output signal.
8
Chapter 7
1、S—R Latches
S-R latch built with NOR Function table
gates
SR Q
Q_L
1
0 0 Last Q lastQ_L hold
01 0
1
reset
10 1
0
set
2
11 0
0 forbidden
Q=QN’=Q_L’
S and R : active high signal
state variable: the symbol representation of
state. n state
2n possible
variables
states
• finite-state machine
the states of a sequential circuit is always finite.
SQ RQ
current state
QS
0
0
0
0
0
1
characteristic equation for
0
1
S-R latch:
Q*=S+R’Q （S·R=0）
1
0
1
0
1
1
S=R=1, restricted combination 1 1
next state
R Q*
0
0
1
0
0
1
1
d
0
1
1
0
0
1
1
d
4
Chapter 7
7.1 Bistable Element
1
feedback
2
Q is the state variable
• Output variable：Q，Q_L，且Q_L=Q’ • Two stable state:
Q=0、Q_L=1
Q=1、Q_L=0
5
Chapter 7
analysis with transfer characteri
stable
INV1
metasta ble
INV2
VOUT=T(VIN)
6
Chapter 7
stable VI1=VO2
7
Chapter 7
7.2 Latches and Flip_Flops
• basic building block • be classified as S-R、D、T、J-K types • definition: ① latch：watches the circuit’s inputs
Some important concepts
• state and state variable
state : collection of state variable, contain all the information about the past necessary to account for the circuit’s future behavior.
13
Chapter 7
3、S-R latch with enable
SQ C RQ
forbidden
metastable still exist
14
Chapter 7
4、D latch
the time of active level of S or R must be keeping longer than minimum pulse width, or else the
latch may be go into metastable.
11
Chapter 7
(3) symbol and characteristic equation
3
Chapter 7
Some important concepts
• clock
a clock signal is a signal used to coordinate the actions of two or more sequential units.
coordinate
by signal
continuously and can changes the outputs at any time.
② flip-flops：samples the circuit’s inputs and
changes the output only when a clocking signal is changing.