MOSFET高速驱动设计
TC4421 TC4422 9A 高速 MOSFET 驱动器 说明书
—
电源电流
IS
—
—
输入工作电压
VDD
4.5
注 1： 设计可确保开关时间。 2： 封装功耗取决于 PCB 板上铜焊垫的面积。 3： 测试数据仅为特征值，未经生产测试。
>1.5
60 60 30 33
0.2 55 —
— 0.025
— 1.7 — —
—
75 75 60 60
1.5 150 18
V 直流测试 V 直流测试 Ω IOUT = 10 mA 且 VDD = 18V Ω IOUT = 10 mA 且 VDD = 18V A VDD = 18V A 10V ≤ VDD ≤ 18V 且 TA = +25°C
－
注 1： 设计可确保开关时间。
—
V
0.8 V
+10 µA 0V ≤ VIN ≤ VDD
— 0.025
3.6 2.7
V 直流测试 V 直流测试 Ω IOUT = 10 mA 且 VDD = 18V Ω IOUT = 10 mA 且 VDD = 18V
MOSFET的驱动保护电路设计
摘要：率场效应晶体管由于具有诸多优点而得到广泛的应用;但它承受短时过载的能力较弱，使其应用受到一定的限制。
分析了二极管器件驱动与保护电路的设计要求;计算了MOSFET驱动器的功耗及MOSFET驱动器与MOSFET的匹配;设计了基于IR2130驱动模块的MOSFET驱动保护电路。
该电路具有结构简单，实用性强，响应速度快等特点。
在驱动无刷直流电机的应用中证明，该电路驱动能力及保护功能效果良好。
功率场效应晶体管(Power MOSFET)是一种多数载流子导电的单极型电压控制器件，具有开关速度快、高频性能好、输入阻抗高、噪声小、驱动功率小、动态范围大、无二次击穿现象和安全工作区域(SOA)宽等优点，因此，在高性能的开关电源、斩波电源及电机控制的各种交流变频电源中获得越来越多的应用。
但相比于绝缘栅双极型晶体管IGBT或大功率双极型晶体管GTR等，MOSFET管具有较弱的承受短时过载能力，因而其实际使用受到一定的限制。
如何设计出可靠和合理的驱动与保护电路，对于充分发挥MOSFET 功率管的优点，起着至关重要的作用，也是有效利用MOSFET管的前提和关键。
文中用IR2130驱动模块为核心，设计了功率MOSFET驱动保护电路应用与无刷直流电机控制系统中，同时也阐述了本电路各个部分的设计要求。
该设计使系统功率驱动部分的可靠性大大的提高。
1 功率MOSFET保护电路设计功率场效应管自身拥有众多优点，但是MOSFET管具有较脆弱的承受短时过载能力，特别是在高频的应用场合，所以在应用功率MOSFET对必须为其设计合理的保护电路来提高器件的可靠性。
功率MOSFET保护电路主要有以下几个方面：1)防止栅极 di/dt过高：由于采用驱动芯片，其输出阻抗较低，直接驱动功率管会引起驱动的功率管快速的开通和关断，有可能造成功率管漏源极间的电压震荡，或者有可能造成功率管遭受过高的di/dt 而引起误导通。
为避免上述现象的发生，通常在MOS驱动器的输出与MOS管的栅极之间串联一个电阻，电阻的大小一般选取几十欧姆。
IR2110驱动电路设计
3 IR2110驱动电路设计
IR2110是一种高压高速功率MOSFET 驱动器，有独立的高端和低端输出驱动通道，其内部 功能原理框图如图1所示。
它包括输入/输出逻辑电路、电平移位电路、输出驱动电路欠压保护和自举电路等部分。
各引出端功能分别是：1端(LO)是低通道输出；2端(COM)是公共端；);3端(VCC)是低端固定电源电压；5端(US)是高端浮置电源偏移电压；6端(UB)是高端浮置电源电压；7端(HO)是高端输出；9端(VDD)是逻辑电路电源电压；10端(HIN)是高通道逻辑输入；11端(SD)是输入有效与否的选择端，可用来过流过压保护；12端(LIN)是低通道输入；13端(VSS)是逻辑电路的地端。
如图所示：在BUCK 变换器中只需驱动单个MOEFET ，因此仅应用了IR2110的高端驱动，此时将12端(LIN)低通道输入接地、1端(LO)低通道输出悬空。
5端(US)和6端(UB)间连接一个自举电容C1，自举电容通常为1F μ和0.1F μ并联使用。
正常工作时，电源对自举电容C1的充电是在续流二级管D1的导通期间进行。
此时，MOEFET 截止，其源极电位接近地电位，,+12v 电源通过D2给C1充电，使C1上的电压接近+12v ，当MOEFET 导通而D1截止时，C1自举，D2截止，C1上存储电荷为IR2110的高端驱动输出提供电源。
实际应用中，逻辑电源VDD 接+5V ，低端固定电源电压VCC 接+12V ；对驱动电路测试时需将VS 端接地。
自举电容C1的值不能太小，否则其上的自举电压达不到12V ，驱动脉冲的幅值不够！自举电容通常为1F μ和0.1F μ并联使用或（105）1F μ。
MOSFET管经典驱动电路设计大全
在设计便携式设备和无线产品时，提高产品性能、延长电池工作时间是设计人员需要面对的两个问题。
DC-DC转换器具有效率高、输出电流大、静态电流小等优点，非常适用于为便携式设备供电。
目前DC-DC转换器设计技术发展主要趋势有：（1）高频化技术：随着开关频率的提高，开关变换器的体积也随之减小，功率密度也得到大幅提升，动态响应得到改善。
小功率DC-DC转换器的开关频率将上升到兆赫级。
（2）低输出电压技术：随着半导体制造技术的不断发展，微处理器和便携式电子设备的工作电压越来越低，这就要求未来的DC-DC变换器能够提供低输出电压以适应微处理器和便携式电子设备的要求。
这些技术的发展对电源芯片电路的设计提出了更高的要求。
首先，随着开关频率的不断提高，对于开关元件的性能提出了很高的要求，同时必须具有相应的开关元件驱动电路以保证开关元件在高达兆赫级的开关频率下正常工作。
其次，对于电池供电的便携式电子设备来说，电路的工作电压低（以锂电池为例，工作电压2.5～3.6V），因此，电源芯片的工作电压较低。
MOS管具有很低的导通电阻，消耗能量较低，在目前流行的高效DC－DC 芯片中多采用MOS管作为功率开关。
但是由于MOS管的寄生电容大，一般情况下NMOS开关管的栅极电容高达几十皮法。
这对于设计高工作频率DC－DC 转换器开关管驱动电路的设计提出了更高的要求。
在低电压ULSI设计中有多种CMOS、BiCMOS采用自举升压结构的逻辑电路和作为大容性负载的驱动电路。
这些电路能够在低于1V电压供电条件下正常工作，并且能够在负载电容1～2pF的条件下工作频率能够达到几十兆甚至上百兆赫兹。
本文正是采用了自举升压电路，设计了一种具有大负载电容驱动能力的，适合于低电压、高开关频率升压型DC－DC转换器的驱动电路。
电路基于Samsung AHP615 BiCMOS工艺设计并经过Hspice仿真验证，在供电电压1.5V ，负载电容为60pF时，工作频率能够达到5MHz以上。
FAN3XXX系列高速低端MOSFET驱动器概述
下 ＋ 时，Ｑ２ 截止，ＩＣ２ 输出的高电压使
Ｆ Ａ Ｎ ３ Ｘ Ｘ Ｘ 系列 Ｍ Ｏ Ｓ Ｆ Ｅ Ｔ 驱动器 Ｑ３ 导通。Ｌ１ 储存的能量向负载释放，经
与 Ｐ Ｗ Ｍ 控制器及功率 Ｍ Ｏ Ｓ Ｆ Ｅ Ｔ 可以组 Ｑ３ 形成回路，其工作状态如图 ９ 所示。
这种同步整流的
结构具有较高的
转换效率。
图 ８ 仅画出
值电压可达 ９ Ａ
根据选定的开关器，确定其 Ｑ ，则利用 Ｇ
表 ３ 可确定需要多大电流的驱动器。
驱动器的电流参数也可用近似的计
算方法来计算，其计算公式如下：
开关导通时（输出源电流），Ｉ ＤＶＲ，ＳＲＣ
≥ １．５（Ｑ ／ｔ ） （１） Ｇ ｓｗ－ｏｎ
开关关断时（输入沉电流），Ｉ ＤＶＲ，ＳＮＫ
之和，每通道的功耗为：
Ｐ ＝Ｖ × Ｑ × ｆ （３）
ＤＲＩＶＥ ＤＤ
Ｇ
ｓｗ
式中，ＶＤＤ 为驱动器的工作电压，ＱＧ
为 Ｍ Ｏ Ｓ Ｆ Ｅ Ｔ 的总栅极电荷，ｆ 为开关 ＳＷ
频率。
按上式计算出的功耗应小于该驱动
器最大允许的功耗。
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今日电子 · 2007 年 11 月
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大功率SiCMOSFET驱动电路设计
第40卷第3期 2020年5月核电子学与探测技术Nuclear Electronics Detection TechnologyVol.40 No. 3May.2020大功率Si C M O S F E T驱动电路设计吴凯铭i2,高大庆1#，高杰\李明睿\申万增1(1.中国科学院近代物理研究所，兰州730000;2.中国科学院大学，北京100049)摘要•.为了使强流重离子加速器装置（H IAF)碳化硅功率开关器件SiC M O SFET工作在理想状态，设计了基于SIC1182K驱动芯片的SiC M O SFET驱动电路。
对该驱动电路的输出电压、响应时间、脉宽 连续可调性、稳定性和可靠性进行实验测试，测试结果表明：该驱动电路能够长时间、稳定可靠工作，满 足SiC M O SF E T的工作需求。
关键词：加速器电源；SIC1182K;SiC M O SFET;驱动电路中图分类号：T L56 文献标志码：A文章编号：0258 —0934(2020)3 —0412 —05强流重离子加速器装置（H IA F)[1’2]是“十 二五”国家重大科学工程项目。
硅功率器件是现阶段兰州加速器电源常用的开关器件，与传 统硅器件相比，第三代半导体开关器件SiC M O SFE T有着更加卓越的高温高压工作性能。
并且SiC M O S F E T上升下降时间短、通态损耗 小等特点[3]，决定了 SiC M O SF E T在达成更高 开关频率的同时，还兼备更小的功率损耗。
在 相同功率等级下，与硅器件开关电源相比，SiC M O SF E T开关电源能够凭借更高的开关频率，减小电路中电容电感体积，降低滤波成本，提高 功率密度。
器件材料的差异导致驱动电路不可 通用，驱动电路就成为SiC M O SFE T理想工作 所需解决的技术难点。
收稿日期：2020_03—02基金项目：国家自然科学基金项目（11805248)资助。
作者简介：吴凯铭（1995 —），男，福建南靖人，在读硕士生，攻读方向为加速器工程设计研究。
MOS驱动电路设计
高速MOS驱动电路设计和应用指南简介MOSFET是Metal Oxide Semiconductor Field Effect Transistor的首字母缩写，它在电子工业高频、高效率开关应用中是一种重要的元件。
或许人们会感到不可思议，但是FET是在1930年，大约比双极晶体管早20年被发明出来。
第一个信号电平FET晶体管制成于二十世纪60年代末期，而功率MOSFET是在二十世纪80年代开始被运用的。
如今,成千上万的MOSFET晶体管集成在现代电子元件,从微型的到“离散”功率晶体管。
本课题的研究重点是在各种开关模型功率转换应用中栅极驱动对功率MOSFET 的要求。
场效应晶体管技术双极晶体管和场效应晶体管有着相同的工作原理。
从根本上说,，两种类型晶体管均是电荷控制元件，即它们的输出电流和控制极半导体内的电荷量成比例。
当这些器件被用作开关时，两者必须和低阻抗源极的拉电流和灌电流分开，用以为控制极电荷提供快速的注入和释放。
从这点看，MOS-FET在不断的开关，当速度可以和双极晶体管相比拟时，它被驱动的将十分的‘激烈’。
理论上讲，双极晶体管和MOSFET的开关速度是基本相同的，这取决与载流子穿过半导体所需的时间。
在功率器件的典型值为20 ~ 200皮秒，但这个时间和器件的尺寸大小有关。
与双极结型晶体管相比，MOSFET在数字技术应用和功率应用上的普及和发展得益于它的两个优点。
优点之一就是在高频率开关应用中MOSFET使用比较方便。
MOSFET更加容易被驱动，这是因为它的控制极和电流传导区是隔离开的，因此不需要一个持续的电流来控制。
一旦MOSFET导通后，它的驱动电流几乎为0。
另外，在MOSFET中，控制电荷的积累和存留时间也大大的减小了。
这基本解决了设计中导通电压降（和多余的控制电荷成反比）和关断时间之间的矛盾。
因此，MOSFET技术以其更加简单的、高效的驱动电路使它比晶体管设备具有更大的经济效益。
此外，有必要突出强调下，尤其是在电源应用上，MOSFET本身具有阻抗特性。
两种常见的MOSFET驱动电路设计
两种常见的MOSFET驱动电路设计常见的MOSFET驱动电路设计有两种：高侧驱动电路和低侧驱动电路。
高侧驱动电路是将MOSFET的源极连接到地，而负载连接到漏极。
这种电路设计的优点是可以在高侧实现PWM调光控制，因为调光信号是接在负载一侧，而不会影响到驱动信号。
高侧驱动电路的实现需要解决负载和电源之间的电位差问题。
一种常见的设计是使用一个电隔离器件，如光耦合器，它可以将输入信号隔离开，并提供一个离地的电位供电MOSFET。
另一种方法是使用一个NPN晶体管来驱动MOSFET，该晶体管的基极通过一个电阻连接到正电源，而发射极连接到MOSFET的源极，并且信号输入到晶体管的基极。
低侧驱动电路是将MOSFET的漏极连接到地，而负载连接到源极。
这种电路设计的优点是相对简单，不需要解决电位差的问题。
低侧驱动电路中最常见的设计时使用一个NPN晶体管将MOSFET的源极与地连接起来。
信号输入到NPN晶体管的基极，晶体管的发射极与MOSFET的源极相连。
当输入信号为高电平时，晶体管导通，MOSFET的源极与地之间产生一个低电平，从而导通MOSFET。
当输入信号为低电平时，晶体管截止，MOSFET被断开。
在设计这两种驱动电路时，需要考虑一些关键参数和特性，以确保MOSFET能够正常工作。
其中一个关键参数是驱动电压的选取。
驱动电压应该足够高以确保MOSFET能够完全导通，同时应该在MOSFET的最大耐压范围内。
另一个关键参数是驱动电流的选取。
驱动电流应该足够大以确保MOSFET能够迅速地从导通到截止的状态切换。
此外，还需要考虑电源的稳定性和电流能力。
为了防止驱动电路的电压波动对MOSFET的工作产生不利影响，应当使用稳定的电源。
此外，驱动电路还应能够提供足够的电流以确保MOSFET迅速地从导通到截止的状态切换。
综上所述，高侧驱动电路和低侧驱动电路是常见的MOSFET驱动电路设计。
通过正确选择驱动电压和驱动电流，并考虑电源稳定性和电流能力，可以确保MOSFET能够正常工作。
高速MOSFET栅极驱动电路的设计与应用指南
高速MOSFEMOSFET T栅极驱动电路的设计与应用指南摘要本文将展示一个用来设计高速开关应用所需的高性能栅极驱动电路的系统性方案。
它综合了各方面的信息，可一次性解决一些最常见的设计问题。
因此，各个层面的电力电子工程师都值得一读。
文中分析了一些最流行的电路方案及其性能，包括寄生元件、瞬间和极端工作条件的影响。
首先，文章对MOSFET技术和开关操作进行了大致讨论，从简单问题逐渐转向复杂问题，并详细讲述了低端和高端栅极驱动电路以及交流耦合和变压器隔离式方案的设计程序。
另外，文章还专门用一个章节的内容来讨论同步整流器应用中MOSFET的栅极驱动要求。
最后，本文还提供了多个分步骤的设计案例。
简介MOSFET，全称为金属氧化物半导体场效应晶体管，是电子产品领域各种高频高效开关应用的关键元器件。
FET技术发明于1930年，比双极晶体管还要早大约20年，这一点令人感到意外。
最早的信号级FET晶体管出现在20世纪50年代末，而功率MOSFET则是在70年代中期问世的。
如今，数百万的MOSFET 晶体管被集成到了各种电子元器件中，从微控制器到“离散式”功率晶体管。
本话题的重点在于各种开关模式电源转换应用中功率MOSFET的栅极驱动要求。
Design And Application GuideFor High Speed MOSFET Gate Drive CircuitsBy Laszlo BaloghABSTRACTThe main purpose of this paper is to demonstrate a systematic approach to design high performance gate drive circuits for high speed switching applications. It is an informative collection of topics offering a “one-stop-shopping” to solve the most common design challenges. Thus it should be of interest to power electronics engineers at all levels of experience.The most popular circuit solutions and their performance are analyzed, including the effect of parasitic components, transient and extreme operating conditions. The discussion builds from simple to more complex problems starting with an overview of MOSFET technology and switching operation. Design procedure for ground referenced and high side gate drive circuits, AC coupled and transformer isolated solutions are described in great details. A special chapter deals with the gate drive requirements of the MOSFETs in synchronous rectifier applications.Several, step-by-step numerical design examples complement the paper.INTRODUCTIONMOSFET – is an acronym for Metal Oxide Semiconductor Field Effect Transistor and it is the key component in high frequency, high efficiency switching applications across the electronics industry. It might be surprising, but FET technology was invented in 1930, some 20 years before the bipolar transistor. The first signal level FET transistors were built in the late 1950’s while power MOSFETs have been available from the mid 70’s. Today, millions of MOSFET transistors are integrated in modern electronic components, from microprocessors, through “discrete” power transistors.The focus of this topic is the gate drive requirements of the power MOSFET in various switch mode power conversion applications. MOSFET TECHNOLOGYThe bipolar and the MOSFET transistors exploit the same operating principle. Fundamentally, both type of transistors are charge controlled devices which means that their output current is proportional to the charge established in the semiconductor by the control electrode. When these devices are used as switches, both must be driven from a low impedance source capable of sourcing and sinking sufficient current to provide for fast insertion and extraction of the controlling charge. From this point of view, the MOSFETs have to be driven just as “hard” during turn-on and turn-off as a bipolar transistor to achieve comparable switching speeds. Theoretically, the switching speeds of the bipolar and MOSFET devices are close to identical, determined by the time required for the charge carriers to travel across the semiconductor region. Typical values in power devices are approximately 20 to 200 picoseconds depending on the size of the device. The popularity and proliferation of MOSFET technology for digital and power applications is driven by two of their major advantages over the bipolar junction transistors. One of these benefits is the ease of use of the MOSFET devices in high frequency switching applications. The MOSFET transistors are simpler to drive because their control electrode is isolated from the current conducting silicon, therefore a continuous ON current is not required. Once the MOSFET transistors are turned-on, their drive current is practically zero. Also, the controlling charge and accordingly the storage time in the MOSFET transistors is greatly reduced. This basically1eliminates the design trade-off between on state voltage drop – which is inversely proportional to excess control charge – and turn-off time. As a result, MOSFET technology promises to use much simpler and more efficient drive circuits with significant economic benefits compared to bipolar devices.Furthermore, it is important to highlight especially for power applications, that MOSFETs have a resistive nature. The voltage drop across the drain source terminals of a MOSFET is a linear function of the current flowing in the semiconductor. This linear relationship is characterized by the R DS(on) of the MOSFET and known as the on-resistance. On-resistance is constant for a given gate-to-source voltage and temperature of the device. As opposed to the -2.2mV/°C temperature coefficient of a p-n junction, the MOSFETs exhibit a positive temperature coefficient of approximately 0.7%/°C to 1%/°C. This positive temperature coefficient of the MOSFET makes it an ideal candidate for parallel operation in higher power applications where using a single device would not be practical or possible. Due to the positive TC of the channel resistance, parallel connected MOSFETs tend to share the current evenly among themselves. This current sharing works automatically in MOSFETs since the positive TC acts as a slow negative feedback system. The device carrying a higher current will heat up more – don’t forget that the drain to source voltages are equal – and the higher temperature will increase its R DS(on) value. The increasing resistance will cause the current to decrease, therefore the temperature to drop. Eventually, an equilibrium is reached where the parallel connected devices carry similar current levels. Initial tolerance in R DS(on) values and different junction to ambient thermal resistances can cause significant – up to 30% – error in current distribution.Device typesAlmost all manufacturers have got their unique twist on how to manufacture the best power MOSFETs, but all of these devices on the market can be categorized into three basic device types. These are illustrated in Figure 1.Figure 1. Power MOSFET device types Double-diffused MOS transistors were introduced in the 1970’s for power applications and evolved continuously during the years. Using polycrystalline silicon gate structures and self-aligning processes, higher density integration and rapid reduction in capacitances became possible. The next significant advancement was offered by the V-groove or trench technology to further increase cell density in power MOSFET devices. The better performance and denser integration don’t come free however, as trench MOS devices are more difficult to manufacture.The third device type to be mentioned here is the lateral power MOSFETs. This device type is constrained in voltage and current rating due to its inefficient utilization of the chip geometry. Nevertheless, they can provide significant benefits in low voltage applications, like in microprocessor power supplies or as synchronous rectifiers in isolated converters.2The lateral power MOSFETs have significantly lower capacitances, therefore they can switch much faster and they require much less gate drive power.MOSFET ModelsThere are numerous models available to illustrate how the MOSFET works, nevertheless finding the right representation might be difficult. Mostof the MOSFET manufacturers provide Spice and/or Saber models for their devices, but these models say very little about the application traps designers have to face in practice. They provide even fewer clues how to solve the most common design challenges.A really useful MOSFET model which would describe all important properties of the device from an application point of view would be very complicated. On the other hand, very simple and meaningful models can be derived of the MOSFET transistor if we limit the applicabilityof the model to certain problem areas.The first model in Figure 2 is based on the actual structure of the MOSFET device and can be used mainly for DC analysis. The MOSFET symbol in Figure 2a represents the channel resistance and the JFET corresponds to the resistance of the epitaxial layer. The length, thus the resistance of the epi layer is a function of the voltage rating of the device as high voltage MOSFETs require thicker epitaxial layer.Figure 2b can be used very effectively to model the dv/dt induced breakdown characteristic of a MOSFET. It shows both main breakdown mechanisms, namely the dv/dt induced turn-on of the parasitic bipolar transistor - present in all power MOSFETs - and the dv/dt induced turn-onof the channel as a function of the gate terminating impedance. Modern power MOSFETs are practically immune to dv/dt triggering of the parasitic npn transistor due to manufacturing improvements to reduce the resistance between the base and emitter regions.It must be mentioned also that the parasitic bipolar transistor plays another important role. Its base – collector junction is the famous body diode of the MOSFET.Figure 2. Power MOSFET models34Figure 2c is the switching model of the MOSFET. The most important parasitic components influencing switching performance are shown in this model. Their respective roles will be discussed in the next chapter which is dedicated to the switching procedure of the device.MOSFET Critical ParametersWhen switch mode operation of the MOSFET is considered, the goal is to switch between the lowest and highest resistance states of the device in the shortest possible time. Since the practical switching times of the MOSFETs (~10ns to 60ns) is at least two to three orders of magnitude longer than the theoretical switching time (~50ps to 200ps), it seems important to understand the discrepancy. Referring back to the MOSFET models in Figure 2, note that all models include three capacitors connected between the three terminals of the device. Ultimately, the switching performance of the MOSFET transistor is determined by how quickly the voltages can be changed across these capacitors.Therefore, in high speed switching applications, the most important parameters are the parasitic capacitances of the device. Two of these capacitors, the C GS and C GD capacitors correspond to the actual geometry of the device while the C DS capacitor is the capacitance of the base collector diode of the parasitic bipolar transistor (body diode).The C GS capacitor is formed by the overlap of the source and channel region by the gate electrode. Its value is defined by the actual geometry of the regions and stays constant (linear) under different operating conditions.The C GD capacitor is the result of two effects. Part of it is the overlap of the JFET region and the gate electrode in addition to the capacitance of the depletion region which is non-linear. The equivalent C GD capacitance is a function of the drain source voltage of the device approximated by the following formula:DS1GD,0GD V K 1C C ⋅+≈The C DS capacitor is also non-linear since it is the junction capacitance of the body diode. Its voltage dependence can be described as:DS 2DS,0DS V K C C ⋅≈Unfortunately, non of the above mentioned capacitance values are defined directly in the transistor data sheets. Their values are given indirectly by the C ISS , C RSS , and C OSS capacitor values and must be calculated as: RSSOSS DS RSS ISS GS RSSGD C C C C C C C C −=−== Further complication is caused by the C GD capacitor in switching applications because it is placed in the feedback path between the input and output of the device. Accordingly, its effective value in switching applications can be much larger depending on the drain source voltage of the MOSFET. This phenomenon is called the “Miller” effect and it can be expressed as:()GD L fs eqv GD,C R g 1C ⋅⋅+=Since the C GD and C DS capacitors are voltage dependent, the data sheet numbers are valid only at the test conditions listed. The relevant average capacitances for a certain application have to be calculated based on the required charge to establish the actual voltage change across the capacitors. For most power MOSFETs the following approximations can be useful: offDS,spec DS,spec OSS,ave OSS,off DS,spec DS,spec RSS,ave GD,V V C 2C V V C 2C ⋅⋅=⋅⋅=The next important parameter to mention is the gate mesh resistance, R G,I . This parasitic resistance describes the resistance associated by the gate signal distribution within the device. Its importance is very significant in high speed switching applications because it is in between the driver and the input capacitor of the device, directly impeding the switching times and the5dv/dt immunity of the MOSFET. This effect is recognized in the industry, where real high speed devices like RF MOSFET transistors use metal gate electrodes instead of the higher resistance polysilicon gate mesh for gate signal distribution. The R G,I resistance is not specified in the data sheets, but in certain applications it can be a very important characteristic of the device. In the back of this paper, Appendix A4 shows a typical measurement setup to determine the internal gate resistor value with an impedance bridge.Obviously, the gate threshold voltage is also a critical characteristic. It is important to note that the data sheet V TH value is defined at 25°C and at a very low current, typically at 250μA. Therefore, it is not equal to the Miller plateau region of the commonly known gate switching waveform. Another rarely mentioned fact about V TH is its approximately –7mV/°C temperature coefficient. It has particular significance in gate drive circuits designed for logic level MOSFET where V TH is already low under the usual test conditions. Since MOSFETs usually operate at elevated temperatures, proper gate drive design must account for the lower V TH when turn-off time, and dv/dt immunity is calculated as shown in Appendix A and F.The transconductance of the MOSFET is its small signal gain in the linear region of its operation. It is important to point out that every time the MOSFET is turned-on or turned-off, it must go through its linear operating mode where the current is determined by the gate-to-source voltage. The transconductance, g fs , is the small signal relationship between drain current and gate-to-source voltage:GSD fs dV dI g =Accordingly, the maximum current of the MOSFET in the linear region is given by: ()fs th GS D g V V I ⋅−=Rearranging this equation for V GS yields the approximate value of the Miller plateau as a function of the drain current.fs D th Miller GS,g IV V +=Other important parameters like the source inductance (L S ) and drain inductance (L D ) exhibit significant restrictions in switching performance. Typical L S and L D values are listed in the data sheets, and they are mainly dependant on the package type of the transistor. Their effects can be investigated together with the external parasitic components usually associated with layout and with accompanying external circuit elements like leakage inductance, a current sense resistor, etc.For completeness, the external series gate resistor and the MOSFET driver’s output impedance must be mentioned as determining factors in high performance gate drive designs as they have a profound effect on switching speeds and consequently on switching losses.SWITCHING APPLICATIONSNow, that all the players are identified, let’s investigate the actual switching behavior of the MOSFET transistors. To gain a better understanding of the fundamental procedure, the parasitic inductances of the circuit will be neglected. Later their respective effects on the basic operation will be analyzed individually. Furthermore, the following descriptions relate to clamped inductive switching because most MOSFET transistors and high speed gate drive circuits used in switch mode power supplies work in that operating mode.Figure 3. Simplified clamped inductive switchingmodelThe simplest model of clamped inductive switching is shown in Figure 3, where the DC current source represents the inductor. Its current can be considered constant during the short switching interval. The diode provides a path for the current during the off time of the MOSFET and clamps the drain terminal of the device to the output voltage symbolized by the battery.Turn-On procedureThe turn-on event of the MOSFET transistor can be divided into four intervals as depicted in Figure 4.Figure 4. MOSFET turn-on time intervalsIn the first step the input capacitance of the device is charged from 0V to V TH. During this interval most of the gate current is charging the C GS capacitor. A small current is flowing through the C GD capacitor too. As the voltage increases at the gate terminal and the C GD capacitor’s voltage has to be slightly reduced. This period is called the turn-on delay, because both the drain current and the drain voltage of the device remain unchanged.Once the gate is charged to the threshold level, the MOSFET is ready to carry current. In the second interval the gate is rising from V TH to the Miller plateau level, V GS,Miller. This is the linear operation of the device when current is proportional to the gate voltage. On the gate side, current is flowing into the C GS and C GD capacitors just like in the first time interval and the V GS voltage is increasing. On the output side of the device, the drain current is increasing, while the drain-to-source voltage stays at the previous level (V DS,OFF). This can be understood looking at the schematic in Figure 3. Until all the current is transferred into the MOSFET and the diode is turned-off completely to be able to block reverse voltage across its pn junction, the drain voltage must stay at the output voltage level. Entering into the third period of the turn-on procedure the gate is already charged to the sufficient voltage (V GS,Miller) to carry the entire load current and the rectifier diode is turned off. That now allows the drain voltage to fall. While the drain voltage falls across the device, the gate-to-source voltage stays steady. This is the Miller plateau region in the gate voltage waveform. All the gate current available from the driver is diverted to discharge the C GD capacitor to facilitate the rapid voltage change across the drain-to-source terminals. The drain current of the device stays constant since it is now limited by the external circuitry, i.e. the DC current source.The last step of the turn-on is to fully enhance the conducting channel of the MOSFET by applying a higher gate drive voltage. The final amplitude of V GS determines the ultimate on-resistance of the device during its on-time. Therefore, in this fourth interval, V GS is increased from V GS,Miller to its final value, V DRV. This is accomplished by charging the C GS and C GD capacitors, thus gate current is now split between the two components. While these capacitors are being charged, the drain current is still constant, and the drain-to-source voltage is slightly decreasing as the on-resistance of the device is being reduced.6Turn-Off procedureThe description of the turn-off procedure for the MOSFET transistor is basically back tracking the turn-on steps from the previous section. Start with V GS being equal to V DRV and the current in the device is the full load current represented by I DC in Figure 3. The drain-to-source voltage is being defined by I DC and the R DS(on) of the MOSFET. The four turn-off steps are shown in Figure 5. for completeness.Figure 5. MOSFET turn-off time intervals The first time interval is the turn-off delay which is required to discharge the C ISS capacitance from its initial value to the Miller plateau level. During this time the gate current is supplied by the C ISS capacitor itself and it is flowing through the C GS and C GD capacitors of the MOSFET. The drain voltage of the device is slightly increasing as the overdrive voltage is diminishing. The current in the drain is unchanged.In the second period, the drain-to-source voltage of the MOSFET rises from I D⋅R DS(on) to the final V DS(off) level, where it is clamped to the output voltage by the rectifier diode according to the simplified schematic of Figure 3. During this time period – which corresponds to the Miller plateau in the gate voltage waveform - the gate current is strictly the charging current of the C GDcapacitor because the gate-to-source voltage is constant. This current is provided by the bypass capacitor of the power stage and it is subtracted from the drain current. The total drain current still equals the load current, i.e. the inductor current represented by the DC current source in Figure 3.The beginning of the third time interval is signified by the turn-on of the diode, thus providing an alternative route to the load current.The gate voltage resumes falling from V GS,Miller to V TH. The majority of the gate current is coming out of the C GS capacitor, because the C GDcapacitor is virtually fully charged from the previous time interval. The MOSFET is in linear operation and the declining gate-to-source voltage causes the drain current to decrease and reach near zero by the end of this interval.Meanwhile the drain voltage is steady at V DS(off)due to the forward biased rectifier diode.The last step of the turn-off procedure is to fully discharge the input capacitors of the device. V GSis further reduced until it reaches 0V. The bigger portion of the gate current, similarly to the third turn-off time interval, supplied by the C GScapacitor. The drain current and the drain voltage in the device are unchanged.Summarizing the results, it can be concluded that the MOSFET transistor can be switched between its highest and lowest impedance states (either turn-on or turn-off) in four time intervals. The lengths of all four time intervals are a function of the parasitic capacitance values, the required voltage change across them and the available gate drive current. This emphasizes the importance of the proper component selection and optimum gate drive design for high speed, high frequency switching applications.7Characteristic numbers for turn-on, turn-off delays, rise and fall times of the MOSFET switching waveforms are listed in the transistor data sheets. Unfortunately, these numbers correspond to the specific test conditions and to resistive load, making the comparison of different manufacturers’ products difficult. Also, switching performance in practical applications with clamped inductive load is significantly different from the numbers given in the data sheets.Power lossesThe switching action in the MOSFET transistorin power applications will result in some unavoidable losses, which can be divided into two categories.The simpler of the two loss mechanisms is the gate drive loss of the device. As described before, turning-on or off the MOSFET involves chargingor discharging the C ISS capacitor. When the voltage across a capacitor is changing, a certain amount of charge has to be transferred. The amount of charge required to change the gate voltage between 0V and the actual gate drive voltage V DRV, is characterized by the typical gate charge vs. gate-to-source voltage curve in the MOSFET datasheet. An example is shown in Figure 6.Figure 6. Typical gate charge vs. gate-to-sourcevoltage This graph gives a relatively accurate worst case estimate of the gate charge as a function of the gate drive voltage. The parameter used to generate the individual curves is the drain-to-source off state voltage of the device. V DS(off) influences the Miller charge – the area below the flat portion of the curves – thus also, the total gate charge required in a switching cycle. Once the total gate charge is obtained from Figure 6, the gate charge losses can be calculated as:DRVGDRVGATEfQVP⋅⋅=where V DRV is the amplitude of the gate drive waveform and f DRV is the gate drive frequency – which is in most cases equal to the switching frequency. It is interesting to notice that the Q G⋅f DRV term in the previous equation gives the average bias current required to drive the gate. The power lost to drive the gate of the MOSFET transistor is dissipated in the gate drive circuitry. Referring back to Figures 4 and 5, the dissipating components can be identified as the combination of the series ohmic impedances in the gate drive path. In every switching cycle the required gate charge has to pass through the driver output impedances, the external gate resistor, and the internal gate mesh resistance. As it turns out, the power dissipation is independent of how quickly the charge is delivered through the resistors. Using the resistor designators from Figures 4 and 5, the driver power dissipation can be expressed as:OFFDRV,ONDRV,DRVIG,GATELODRVGDRVLOOFFDRV,IG,GATEHIDRVGDRVHIONDRV,PPPRRRfQVR21PRRRfQVR21P+=++⋅⋅⋅⋅=++⋅⋅⋅⋅=In the above equations, the gate drive circuit is represented by a resistive output impedance and this assumption is valid for MOS based gate drivers. When bipolar transistors are utilized in the gate drive circuit, the output impedance becomes non-linear and the equations do not yield the correct answers. It is safe to assume that with low value gate resistors (<5Ω) most gate drive losses are dissipated in the driver. If R GATE is sufficiently large to limit I G below the output89current capability of the bipolar driver, the majority of the gate drive power loss is then dissipated in R GATE .In addition to the gate drive power loss, the transistors accrue switching losses in the traditional sense due to high current and high voltage being present in the device simultaneously for a short period. In order to ensure the least amount of switching losses, the duration of this time interval must be minimized. Looking at the turn-on and turn-off procedures of the MOSFET, this condition is limited to intervals 2 and 3 of the switching transitions in both turn-on and turn-off operation. These time intervals correspond to the linear operation of the device when the gate voltage is between V TH and V GS,Miller , causing changes in the current of the device and to the Miller plateau region when the drain voltage goes through its switching transition.This is a very important realization to properly design high speed gate drive circuits. It highlights the fact that the most important characteristic of the gate driver is its source-sink current capability around the Miller plateau voltage level. Peak current capability, which is measured at full V DRV across the driver’s output impedance, has very little relevance to the actual switching performance of the MOSFET. What really determines the switching times of the device is the gate drive current capability when the gate-to-source voltage, i.e. the output of the driver is at ~5V (~2.5V for logic level MOSFETs).A crude estimate of the MOSFET switching losses can be calculated using simplified linear approximations of the gate drive current, drain current and drain voltage waveforms during periods 2 and 3 of the switching transitions. First the gate drive currents must be determined for the second and third time intervals respectively:()G.I GATE HI MillerGS,DRV G3G.IGATE HI TH Miller GS,DRVG2R R R V V I R R R V V 0.5V I ++−=+++⋅−=Assuming that I G2 charges the input capacitor of the device from V TH to V GS,Miller and I G3 is the discharge current of the C RSS capacitor while the drain voltage changes from V DS(off) to 0V, the approximate switching times are given as:G3offDS,RSS G2THMillerGS,ISS I V C t3I V V C t2⋅=−⋅=During t2 the drain voltage is V DS(off) and the current is ramping from 0A to the load current, I L while in t3 time interval the drain voltage is falling from V DS(off) to near 0V. Again, using linear approximations of the waveforms, the power loss components for the respective time intervals can be estimated:Loff DS,Loff DS,I 2V T t3P32I V T t2P2⋅⋅=⋅⋅=where T is the switching period. The total switching loss is the sum of the two loss components, which yields the following simplifed expression:Even though the switching transitions are well understood, calculating the exact switching losses is almost impossible. The reason is the effect of the parasitic inductive components which will significantly alter the current and voltage waveforms, as well as the switching times during the switching procedures. Taking into account the effect of the different source and drain inductances of a real circuit would result in second order differential equations to describe the actual waveforms of the circuit. Since the variables, including gate threshold voltage, MOSFET capacitor values, driver output impedances, etc. have a very wide tolerance, the above described linear approximation seems to be a reasonable enough compromise to estimate switching losses in the MOSFET.Effects of parasitic componentsThe most profound effect on switching performance is exhibited by the source inductance. There are two sources for parasitic source inductance in a typical circuit, the sourceTt3t22I V P L DS(off)SW +⋅⋅=。
MOSFET的驱动技术详解
MOSFET的驱动技术详解simtriex/simplis仿真电路用软件MOSFET作为功率开关管，已经是是开关电源领域的绝对主力器件。
虽然MOSFET作为电压型驱动器件，其驱动表面上看来是非常简单，但是详细分析起来并不简单。
下面我会花一点时间，一点点来解析MOSFET的驱动技术，以及在不同的应用，应该采用什么样的驱动电路。
首先，来做一个实验，把一个MOSFET的G悬空，然后在DS上加电压，那么会出现什么情况呢？很多工程师都知道，MOS会导通甚至击穿。
这是为什么呢？我根本没有加驱动电压，MOS怎么会导通？用下面的图1，来做个仿真；去探测G极的电压，发现电压波形如图2所示。
图1 图2这种情况有什么危害呢？实际情况下，MOS肯定有驱动电路的么，要么导通，要么关掉。
问题就出在开机，或者关机的时候，最主要是开机的时候，此时你的驱动电路还没上电。
但是输入上电了，由于驱动电路没有工作，G级的电荷无法被释放，就容易导致MOS导通击穿。
那么怎么解决呢？在GS之间并一个电阻。
其仿真的结果如图4。
几乎为0V。
图3 图4什么叫驱动能力，很多PWM芯片，或者专门的驱动芯片都会说驱动能力，比如384X 的驱动能力为1A，其含义是什么呢？假如驱动是个理想脉冲源，那么其驱动能力就是无穷大，想提供多大电流就给多大。
但实际中，驱动是有内阻的，假设其内阻为10欧姆，在10V电压下，最多能提供的峰值电流就是1A，通常也认为其驱动能力为1A。
那什么叫驱动电阻呢，通常驱动器和MOS的G极之间，会串一个电阻，就如下图5的R3。
驱动电阻的作用，如果你的驱动走线很长，驱动电阻可以对走线电感和MOS结电容引起的震荡起阻尼作用。
但是通常，现在的PCB走线都很紧凑，走线电感非常小。
第二个，重要作用就是调解驱动器的驱动能力，调节开关速度。
当然只能降低驱动能力，而不能提高。
图5对上图进行仿真，R3分别取1欧姆，和100欧姆。
下图6是MOS的G极的电压波形上升沿。
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图 13 是 MOSFET 处于线性放大区长达 500uS 的波形。如果某些应用需要 MOSFET 进入放大区，我们必 须确定 MOSFET 处于安全工作区 SOA 的限制以内。
图 13 6． 结论 MOSFET 的驱动设计，我们需要考虑以下几个方面： 1．选择合适的 MOSFET。Qg 小的 MOSFET 可以达到快速的开关速度，同时减小对驱动的要求。Vgsth
震荡回路 2 是由图 4 中蓝色曲线组成。其回路由 MOSFET 源极寄生电感（包括 MOSFET 封装电感以及 PCB 布线等效电感），MOSFET 结电容 Cgs, MOSFET 门极电感 Lg（包括 MOSFET 封装电感以及 PCB 布线等效电感）,MOSFET 内置门极驱动电阻 Rgini，MOSFET 外置门极驱动电阻 Rgext 组成。 当 MOSFET 开通时，MOSFET 电流上升，该回路的电感，电容同样会产生 LC 震荡，震荡频率通常在 100MHz 到 200MHz 左右，同时急剧变化的电流 di/dt. 会在 Ls 上产生一个变化的电压。di/dt=VLs/Ls. 当假设 di/dt=500A/us, Ls=10nH 时，根据公式在漏极电感 Ls 上产生的电压 VLs=di/dt*Ls=500A/us*10nH=5V. 一 旦门极震荡电压在阀值范围内，MOSFET 会不断重复开关，造成极大的开关损耗甚至会影响到 MOSFET 的可靠性。
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图4 综上，对于驱动线路设计中如何降低 di/dt,dv/dt 减小震荡，我们有以下几点考虑：
1． 减小 PCB 布线所带来等效寄生电感。 2． 选择合适的带内置门极驱动电阻的 MOSFET 如 Infineon CoolMOS C6 系列。 3． 选择无引线的封装 MOSFET，降低由封装所产生的寄生电阻和电感。 4． 选择合适的门极驱动电阻从而抑制 MOSFET 的门极驱动震荡。 图 5 中是 Infineon 的 600V 高压 MOSFET ThinPAK 封装。这种封装不仅具有小的封装寄生参数，同时可 以缩短 PCB 布线的长度。此外该封装门极地线与驱动信号地线分属于不同的管脚，可以有效的降低门极驱 动震荡。
1． 设置门极驱动电阻 2． 设置 MOSFET 阀值电压 Vgsth 3． 设置 PCB 布线电感
图7 设置 1，如图 8 将其中一 MOSFET 门极驱动电阻 R3 设置为 12Ohm,另一 MOSFET 门极驱动电阻 R2 保持 10Ohm 不变。
图8 如图 7 右所示，当门极驱动电阻相差 2Ohm 时，流过两个 MOSFET 的电流相差并不十分明显。 设置 2，如图 9 将其中一 MOSFET DUT1 门极阀值电压设置为 3.4V,另一 MOSFET DUT2 门极阀值电压保持 3V 不 变。
图9 如图 9 右所示，当门极驱动电压相差 0.4V 时，流过两个 MOSFET 的电流相差也并不十分明显。 设置 3，如图 10 将其中一 MOSFET DUT1 门极阀值电压设置为 4V,另一 MOSFET DUT2 门极阀值电压设置为 2V。
图 10 如图 10 右所示，当门极驱动电压相差 2V 时，分别通过两个 MOSFET 的电流相差近 40% 当情形为多个 MOSFET 并联时，其中个别 MOSFET 将会出现过流，过温现象。 设置 4，如图 11 将两个 MOSFET 之间的布线电感设置为 10nH。
2． MOSFET 结构以及影响驱动的相关参数
图1 图 1 是 MOSFET 的电容等效图。MOSFET 包含 3 个等效结电容 Cgd, Cgs 和 Cds. 通常在 MOSFET 的规格书中我们可以看到以下参数
其中 Ciss=Cgs+Cgd Coss=Cgd+Cds Crss=Cgd
这些结电容影响着 MOSFET 开通和关闭速度。结电容小的 MOSFET 具有快速的开关速度，可以降低 MOSFET 开通和关闭时所产生的损耗。同时对驱动线路需求更低。 但是值得注意的是这些电容跟普通的电容并不完全相同，普通电容的容值并不会有太大的改变，而 MOSFET 等效电容容值会随着 MOSFET Vds 的变化而变化。图 2 描述了 MOSFET 结电容随电压的变化 状况。
图5 4． MOSFET 并联 由于功率或者效率的原因，单个 MOSFET 在某些应用场合并不能完全满足要求，此时需要两个或多个 MOSFET 进行并联。我们下面来简单分析 MOSFET 并联会面临那些问题。
图6 图 6 是当两个 MOSFET 并联时的等效电路，当 MOSFET 开关时，很容易在图 6 红色区域形成自激震荡， 该震荡回路由 MOSFET 寄生参数和驱动电路中 Rg1ext, Lg1, Rg1 ini, Cgd1, Ld1, 和 Rg2ext, Lg2, Rg2 ini, Cgd2, Ld2 共同组成。 由于震荡，并联 MOSFET 的门极驱动电压并不能保持一致，门极电压高于 Vgsth 的 MOSFET 仍然开通， 门极电压低于 Vgsth 的 MOSFET 关闭，使得各 MOSFET 之间并不能完全均流。同时， 由于受该震荡回 路的影响， 电磁干扰，门极击穿同样是工程师面临问题。 而有效的控制 MOSFET 并联时的自激震荡我们需要注意以下几点：
MOSFET 高速驱动设计
摘要： 本文阐述了 MOSFET 驱动的基本要求以及在各种应用中如何优化驱动电路的设计 关键词： MOSFET 驱动， MOSFET 并联
1． 引言 随着电源高效，高功率密度的要求，电源的频率由原来的工频，到几十千赫兹，再到如今几百千赫兹甚至 兆赫兹。电源频率的要求越来越高。如何选择合适的 MOSFET, 如何有效的驱动高速的 MOSFET，提升电 源效率是广大工程师面临的问题。本文将探讨 MOSFET 的选型以及高速驱动线路的设计的注意事项。
3． 降低 dv/dt,di/dt 造成的震荡 门极震荡是 MOSFET 高速驱动一个常见问题，驱动的震荡直接影响到电源系统的损耗以及可靠性，通常 MOSFET 门极震荡包含两个回路如图 4 图 4 中红色曲线是震荡回路 1，其回路由 MOSFET 漏极寄生电感 Ld（包括 MOSFET 封装电感以及 PCB 布线等效电感）, MOSFET 结电容 Cgd, MOSFET 门极电感 Lg（包括 MOSFET 封装电感以及 PCB 布线 等效电感）, MOSFET 内置门极驱动电阻 Rgini, 以及装配，PCB 布线耦合电容 Cgdext 组成。 当 MOSFET 关闭时，Vds 上升，红色回路的电感，电容会形成 LC 谐振，该谐振频率约在 300MHz 至 500MHz 之间。此时外加的门极驱动电阻 Rgext 对于该回路的阻尼作用并不明显。而能够明显起到阻尼作用的只有 MOSFET 内置门极驱动电阻 Rgini。尤其是对于高压 MOSFET，由于 dv/dt 较低压 MOSFET 更高。
图 11 如图 11 右所示，当门极驱动电压相差 2V 时，通过两个 MOSFET 的电流相差近 100% 如果 MOSFET 选型中没有留有足够的电流裕量，在此状况下极有可能出现失效。
综合以上的模拟测试，我们不难得出，PCB 布线对于 MOSFET 并联影响最大，其次是 MOSFET 门极阀值电压，再次是门极驱动电阻。 因此对于 MOSFET 并联的驱动设计，我们应该将重点放在 PCB 的 布线当中。 首先需要注意的事 PCB 的布线一致性，尽可能使并联中的 MOSFET 布线保持对称，同时减少 MOSFET 地线之间连接的距离，从而减小寄生电感值，连接注意单点接地； 其次选择阀值电压最小值与最大值相差较小的 MOSFET； 再次保证门极驱动电阻的误差在 5%的范围以内。 5． 避免 MOSFET 进入线性放大区 MOSFET 驱动的最小电流：
t3 阶段 t3 阶段 MOSFET Vgs 电压到达米勒平台并保持动态平衡。电流从 MOSFET 漏极流向源极并保持在最大值， Vds 开始下降并最终到达最小值。
t4 阶段 t4 阶段 Vgs 电压上升至最大值，电流从 MOSFET 漏极流向源极并保持在最大值，Vds 同时保持在最小值， MOSFET 进入饱和区，导通电阻降至最小。 以上是 MOSFET 导通的时序介绍，而 MOSFET 关闭的时序与之完全相反。 从 MOSFET 驱动时序来看，MOSFET Qg 对 MOSFET 的开通与关闭速度起决定作用。对于 MOSFET 的 驱动设计应当着手于选择 Qg 较小的 MOSFET，这样不仅可以降低 MOSFET 开关损耗，同时可以降低对 驱动电路峰值电流的需求。
果。 4． 保证足够驱动的功率和峰值电流，避免 MOSFET 长期工作在线性放大区。一旦进入放大区，需要
确认 MOSFET 是否工作在 SOA 范围之内。 上一篇 下一篇
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zmh169 13-11-11 关于 MOSFET 驱动信号为什么会振荡和任何防止振荡解释得很清楚。
图3 2.1 MOSFET 导通时序介绍
t1 阶段 此阶段处于 MOSFET 死区时间。
MOSFET 电压电流并无变化
t2 阶段 t2 阶段 MOSFET Vgs 电压达到阀值并继续上升。此时 MOSFET 开始导通，电流从 MOSFET 漏极流向源 极并在 t2 结束时到达最大值，而 Vds 此时保持不变。