High-performance, parallel, stack-based genetic programming

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专业英语_单词

专业英语_单词

说明:本单词是按照专业英语吕老师课前提问的单词所总结,由于水平有限加之期末时间仓促,错误在所难免,敬请同学们谅解~~~编辑:张婷婷于超2011年12月17日——————1.1原件、组件component性能capability暂时的temporary永久的permanentlyRAM random-access memory 随机存取器ROM read-only memory 只读存取器存取,访问access指令instruction数据data命令command内部的internal外部的external处理机process主存储器primary storageCPU central processing unit 中央处理机辅助存储器secondary storage容量capacity功能functionality外围设备peripheral1.2总线互联bus interconnection通信communication传输transmission设备device并行parallel串行serial元件、组件component分层结构hierarchy性能performance/capability目的地destination容量capacity处理器processor命令command操作operation体系结构architecture 接口interface、外设peripheral扩充总线expansionSCSI small computer system interface改写rewrite外设peripheralPCI peripheral component体系结构architecture微处理器microprocessor性能、能力capability/performance组件、部件component并行parallel串行serial带宽bandwidth接口interface目的地destination实现、设计实现implementation电磁magnetic吞吐量throughput配置configuration应用程序application驱动程序driver兼容的compatible操作系统OS operating system可扩展性scalabilityVOIP voice on IP IP电话,网络电话分层结构hierarchy2.4USB universal serial bus 通用串行总线设备device并行的parallel串行的serial调制解调器modem数码相机digital camera安装软件install the software标准化的standardizedOS operating system 操作系统驱动程序driver电缆cable版本version升级upgrade发行,发布release宽带bandwidth多媒体multimedia应用程序application传输transmission可兼容性compatibility容量capacity分辨率resolution外设peripheral生产率productivity性能performance枚举技术enumeration中断interrupt成批bulk执行perform询问query火线firewire替代品alternative接口interface实现implement数字化的digitized屏蔽干扰shield interference 方便的convenient配置configuration互联interconnect外设peripheral3.1局域网local area network便利的convenient配置configuration重新配置reconfiguration互联interconnect外设peripheral面向对象object-oriented类class结构struct预处理preprocessor表示represent相互作用interaction 数据结构data structure消息message方法method面向过程procedure-oriented函数function调用函数call function扩充extension抽象abstract属性attribute实例instance最终ultimately属于描述describedescriptiondescriptor封装encapsulation3种描述符public private protected派生子类derived subclass分层结构hierarchy多态性polymorphism派生derive响应response公共的public可扩充性extendability虚函数virtual function动态的dynamically静态的statically运行run编译compile完成accomplish早期约束early binding初始化initialize体系结构architecture利用utilize分布式环境distributed environment硬件软件平台hardware and software platform 嵌入式系统embedded system可靠的reliable可移植的portable实时的real time确保secure鲁棒性robust操作operation网络network分布式的distributed升级upgrade补丁patch动态地dynamically可移植的portable自适应的adaptable面向对象object-oriented平台platform多线程的multithreaded可移植性的portable portability动态性能dynamic capability各自的respective灵活的flexible性能capability performance分配allocate存储storage特性property编译compile接口interface执行executeOS operating system 操作系统GUI graphical user interface图形用户接口SCSI small computer system interface小型计算机系统接口IC integrated circuit 集成电路软件software硬件hardware便利的,方便的convenient资源分配器resource allocator汇编程序assembler编译程序compiler批处理程序batch system常驻,驻留resident利用率utilization脱机操作off-line operation缓冲buffering重叠overlap多道程序设计multiprogramming分时time sharing交互interact实时系统real-time system多处理器multiprocessor 专用应用系统dedicated application传感器sensor可靠性reliability网络OS network operating system分布式OS distributed operating system 并行OS parallel operating system 干扰interfere正常的normal修改modify指令instruction执行execute中断interrupt体系结构architecture设备device应用程序application信息information消息message视频video音频audio输入输出input output显示present表示represent脚本script引擎engine位图bit map分配allocation进程process便利的convenient文本编辑器text editor数据库database检索retrieveIC integrated circuit 集成电路集成integrated访问access通信communication视图view完成百分比completion percentage窗口管理程序window managers显示present消息message描述describe采取适当的行动take appropriate action 适当的appropriate复杂的sophisticated构造construct库library可重用的reusable交互interaction对象object互连connection接口,界面interface终端terminal独立性independence工作台workstation应用程序application可移植性transportability各种各样variety5.1网络network因特网Internet硬件hardware软件software通信communication不兼容incompatible网关gateway转换translation互连interconnect主干网backbone参考模型reference model协议protocol协议栈protocol stackFTP 文件传输协议file transfer protocol LAN 局域网local area networkWAN 广域网wide area networkMAN 城域网metropolitan area network TCP/IP 传输控制协议transmission control protocol 互联网协议Internet protocol下载downloadWWW 万维网world wide web图形电子文档graphical electronic document 浏览browse浏览器browser视频会议video conferencing传真fax体系结构框架architectural framework存取,访问access客户机client 服务器serverC/S 客户机服务器client-sever systemB/S 浏览器服务器browser-sever system 网页page链接link超文本hypertext虚拟现实virtual reality服务进程sever process协议protocolHTTP 超文本传输协议hypertext transport protocol URL 统一资源定位器uniform resource locator DNS 域名系统domain name system万维网WWW word wide webISP internet serve provider因特网服务提供商导航navigation大写字母capitalization恰当的,适当的appropriate工具栏toolbar滚动栏scroll bar标题栏title bar菜单栏menu bar地址栏address bar5.2有线的wired无线的wireless区域网regional设置setup主干网backbone拨号dial-up调制解调器modem接口interface临时的temporary当前因特网会话the current session安全性security呼叫等待call-waiting呼叫转接call-forwarding促进facilitate数据传输率data transfer rate装置appliance便携设备portable device访问accessISDN 综合服务数字网integrated services digital network PC 个人电脑personal computer 静态static虚函数virtual function实际上virtuallyIC 集成电路integrated circuitCD 光盘compact discDVD 数字视盘digital video discLCD 液晶显示liquid crystal display HTML 超文本传输语言hypertext markup language CA TV 有线电视community antenna television 专用的dedicatedDSL 数字用户线路digital subscriber line可用的available转换,开关switch安装installation版本version宽带broadband选择alternative电缆cable升级update全双工full-duplex访问access带宽bandwidth显著的dramatically费用fee卫星satellite固定无线fixed wireless移动无线mobile wireless防火墙firewall文件共享file sharing合并incorporate性能capability 7.1数据库database数据库管理系统database management system 关系relation表示represent永久permanently软件software主存primary storage便利的convenient检索retrieve数据抽象data abstraction最终用户ultimate user终端terminal设备device访问access视图view用户程序application外部的external内部的internal应用程序application指定specify专用dedicate实现implement管理员administrator分配allocate分布式distribute语义semantic语法syntax约束constraint描述describe基于对象object-based实体关系模型entity-relationship model各自的respectively主键primary key相关联的associated适当的appropriate层次hierarchy多态性polymorphism封装encapsulationRTOS 实时操作系统real-time operating system XML 可扩展标记语言Extensive Makeup Language URI 统一资源标识符Uniform Resource IdentifierISO/OSI 国际标准化组织International Standardization Organization /开放系统互联模型Open System Interconnection ModelASP 应用服务供应商application service providerPAN 个人网personal area networkCAD 计算机辅助设计Computer - Aided DesignCAM 计算机辅助制造computer-aided manufacturingGIS 地理信息系统Geographic Information SystemCIM 计算机集成制造computer integrated manufacturingAPI 应用程序设计接口Application Program InterfaceDA T 数字式录音带digital audio tapeMPEG 运动图像专家组Moving Picture Experts GroupJPEG 联合图像专家组Joint Photographic Experts GroupMIDI 音乐设备数字界面Musical Instrument Digital InterfaceA VI 多媒体文件格式Audio V ideo Interactive--------只总结到2011年12月15日,12月22日的上课内容请同学们自行总结。

轮机工程三管轮考试单词

轮机工程三管轮考试单词

1.船舶主推进injection 喷油ignited 点火foundation 基础alignment 对中balancing 平衡性能cross girdle横梁columus机架the frames 机架friction 磨损wear 磨损in an ordinary常用的for an ordinary对。

来说a pot shaped piston 筒形活塞发动机trunk piston type 筒形活塞柴油机circular shape 圆度fluctuating 承受engine block 机座bedplate 机座chain drives 链条驱动reverse 换向receiver 设备wrist pin活塞销piston gudgeon pin 活塞销used to connect 用于。

相连attached to 相连demulsifying 抗乳化sloped倾斜dilution 稀释detergency清洁作用counteract 中和dividing wells 横隔板release of 释放theremometer温度表pyrometer高温计cavitation ercosion穴蚀sear water 海水raw water 海水condensed 冷凝的moisture 潮湿的on opposite ends 两端inaturally aspirated 自然吸入air receiver 空气瓶air bottle 空气瓶air reservoir空气瓶pilot air 控制空气ruputure爆炸governor调速器pick up 引起stablize operation稳定工作sensitivity灵敏度compensating needle valve 补偿针阀get rid of 排除telegrah 车钟sulfur含硫sulphur硫critical临界速度deflection拐档差individual单独的,独立的separate diesel engine 独立式柴油机remedial action修补措施purified净化resonance共振damper减震器thrust 推力flexible coupling柔性连接distillation process蒸馏过程crush,,nip过盈interrupt干扰clear 不可见tension张力fouled污垢的tubeshaft taper 尾轴椎体tail shaft尾轴bring about引起,促成,导致toleranence公差permanence工况penetration穿透inertia惯性fouling污堵的persistent持续的investigation调查resoance共振restricted受限制的,堵塞limited受限制的,堵塞partially clogged受限制的,堵塞violent激烈的,剧烈的apparent明显的MEP平均有效压力MCR最大持续功率MIP平均指示功率fracture折断,破碎seizure咬岗temporary临时flexible coupling弹性联轴节flection弯曲,indined倾斜pads推力块collar推力环contemporary当代的wisely明智theoretical理论上gray淡褐色accelerate加速initiate发起simultaneously同时的against对着kept pace with跟上,,的步伐projection突起物,凸台predude排除hollow中空的firmly牢固的plasma等离子precise精确的generating tube产气管downcomer下降occupy占据oriteria标准precipitate沉淀re-purge重新扫气chloride氯化物neutralization number中和值adazzling white亮白色purged驱气scarenge驱气warp弯曲band弯曲pit麻点stack烟囱econmizer经机器troublesome棘手的,麻烦的contribute to成为。

英语作文loong和dragon的区别

英语作文loong和dragon的区别

英语作文loong和dragon的区别全文共3篇示例,供读者参考篇1A Tale of Two Processors: Loong and Dragon Chips ComparedAs a computer science student, I've become fascinated by the world of processors – those tiny yet incredibly powerful computing engines that make our digital devices run. Recently, two homegrown Chinese processor architectures have caught my attention: the Loong and the Dragon chips. While both are designed and manufactured in China, they have distinct characteristics that set them apart. In this essay, I'll delve into the key differences between these processors, exploring their performance, architecture, and potential applications.Performance: The Need for SpeedOne of the most critical factors in evaluating a processor is its performance, measured in terms of clock speed, instructions per cycle (IPC), and overall throughput. The Loong architecture, developed by Loongson Technology Corporation, boasts impressive performance capabilities. The latest Loong64 3A5000processor, for instance, features a clock speed of up to 3.0 GHz and supports up to 256 cores, making it a formidable contender in the high-performance computing (HPC) arena.On the other hand, the Dragon chips, designed by Higon Information Technology Co., Ltd., have been primarily focused on delivering cost-effective performance for general-purpose computing tasks. The Dragon V9 processor, for example, operates at a modest clock speed of 1.8 GHz but offersquad-core processing capabilities, making it suitable for applications that don't require extreme computational power.Architecture: Diverging PathsThe Loong and Dragon processors have taken different architectural approaches, each with its own strengths and weaknesses. The Loong architecture is based on the MIPS64 instruction set architecture (ISA), which has a long history and is known for its simplicity and efficiency. This design philosophy has allowed Loongson to optimize the Loong chips forhigh-performance computing tasks, such as scientific simulations, data analysis, and artificial intelligence (AI) workloads.In contrast, the Dragon processors adopt the GroundMedia ISA, which is derived from the ARM architecture. This decisionwas likely driven by the widespread adoption of ARM-based processors in mobile and embedded devices, as well as the vast ecosystem of software and development tools available for ARM. The GroundMedia ISA aims to strike a balance between performance and power efficiency, making Dragon chipswell-suited for applications in consumer electronics, Internet of Things (IoT) devices, and mobile computing.Ecosystem and Software SupportThe success of any processor architecture heavily depends on the availability of software and development tools. In this regard, the Loong and Dragon chips have taken divergent paths, each with its own challenges and opportunities.The Loong processors benefit from the well-established MIPS ecosystem, which includes a wide range of compilers, libraries, and development tools. Additionally, the open-source nature of the MIPS architecture has fostered a vibrant community of developers and researchers, contributing to the ongoing improvement and optimization of the Loong chips.On the other hand, the Dragon processors face the challenge of building a robust software ecosystem around the GroundMedia ISA. While ARM-based software can be ported to the Dragon architecture, the process can be complex and mayrequire significant effort from developers. However, the growing interest in Chinese-developed processors could spur the creation of dedicated development tools and libraries for the Dragon chips, potentially attracting a new generation of developers and software vendors.Applications and Use CasesGiven their distinct characteristics, the Loong and Dragon processors are better suited for different applications and use cases.The Loong chips, with their high-performance capabilities and support for massive parallelism, are well-positioned for applications in scientific computing, data centers, and artificial intelligence. These processors could power supercomputers, high-performance clusters, and specialized hardware accelerators for tasks like deep learning and large-scale data analysis.In contrast, the Dragon processors are more aligned with general-purpose computing tasks, such as desktop and mobile applications, embedded systems, and Internet of Things (IoT) devices. Their focus on cost-effectiveness and power efficiency makes them attractive choices for consumer electronics, smarthome appliances, and other devices that require moderate processing power while maintaining energy efficiency.Security and TrustworthinessIn an increasingly digital world, security and trustworthiness have become paramount concerns, particularly for critical infrastructure and sensitive applications. Both the Loong and Dragon processors have made efforts to address these concerns, but their approaches differ.The Loong architecture implements hardware-based security features, such as memory protection mechanisms and secure boot capabilities. These measures aim to prevent unauthorized access to sensitive data and ensure the integrity of the system during the boot process. Additionally, the open-source nature of the MIPS architecture allows for thorough security audits and community-driven security improvements.On the other hand, the Dragon processors leverage the security features inherited from the ARM architecture, including TrustZone technology and secure enclaves. These features enable hardware-based isolation and secure execution environments, protecting sensitive data and code from potential threats.ConclusionThe Loong and Dragon processors represent China's growing technological prowess and ambition to develop homegrown computing solutions. While they share a common goal of providing high-performance and energy-efficient processing capabilities, their architectural differences and design philosophies make them suitable for distinct applications and use cases.The Loong chips, with their MIPS-based architecture and focus on high-performance computing, are well-suited for scientific simulations, data analysis, and AI workloads. Their support for massive parallelism and hardware-based security features make them attractive choices for mission-critical applications and sensitive computing tasks.In contrast, the Dragon processors, built upon the GroundMedia ISA, offer a balance between performance and power efficiency, making them suitable for general-purpose computing tasks, consumer electronics, and IoT devices. Their ARM-based heritage provides a familiar development ecosystem, albeit with the challenge of building a robust software stack around the GroundMedia ISA.As these homegrown Chinese processors continue to evolve and gain traction, it will be fascinating to observe their impact on the global technology landscape. The competition between the Loong and Dragon architectures could drive innovation, foster the development of new software and hardware ecosystems, and ultimately benefit end-users by providing more choices and tailored computing solutions.篇2The Differences Between Loong and Dragon ProcessorsAs a student studying computer science, one area that has always fascinated me is the world of processors. These tiny yet incredibly complex components are the beating heart of our computers, responsible for executing instructions and performing calculations at lightning-fast speeds. In recent years, the processor market has witnessed the emergence of two fascinating architectures: the Loong and the Dragon. While both are designed to power our digital devices, they exhibit distinct characteristics that set them apart. In this essay, I will delve into the key differences between these two processor families, exploring their origins, architectures, performance, and potential applications.Origins and Background:The Loong processor finds its roots in China, developed by Loongson Technology Corporation, a company based in Beijing. Loongson's mission has been to create a domestic,high-performance processor architecture that can compete with established players like Intel and AMD. The first Loong processor, the Loongson 1, was introduced in 2001, marking the beginning of China's journey towards self-sufficiency in the processor domain.On the other hand, the Dragon processor emerged from the United States, born out of the collaborative efforts of several technology giants, including Google, Amazon, and Ampere Computing. The Dragon architecture was designed to address the growing demand for energy-efficient and scalable processors, particularly in the realm of cloud computing and data centers.Architectural Differences:One of the most fundamental differences between the Loong and Dragon processors lies in their underlying architectures. The Loong processors are based on the MIPS (Microprocessor without Interlocked Pipeline Stages) instruction set architecture (ISA), which has a long history dating back to the1980s. MIPS is known for its simplicity, efficient pipeline design, and compatibility with a wide range of software and operating systems.In contrast, the Dragon processors are built upon the Arm instruction set architecture (ISA), which has become increasingly popular in the mobile and embedded systems market. Arm's strength lies in its power-efficient design, making it an attractive choice for devices with limited power budgets, such as smartphones, tablets, and Internet of Things (IoT) devices.Performance and Capabilities:When it comes to performance, both the Loong and Dragon processors have their strengths and weaknesses. The Loong processors have traditionally been geared towardhigh-performance computing (HPC) applications, offering impressive computational power and support for advanced features like vector processing and multithreading. However, they have sometimes lagged behind their Intel and AMD counterparts in terms of raw processing power and software ecosystem support.The Dragon processors, on the other hand, have been optimized for cloud computing and data center workloads. They excel in areas such as parallel processing, virtualization, andenergy efficiency. While they may not match the raw performance of high-end server processors from Intel and AMD, the Dragon processors offer a compelling balance of performance and power efficiency, making them well-suited for large-scale deployments in cloud environments.Applications and Use Cases:The differing architectures and capabilities of the Loong and Dragon processors lend themselves to different applications and use cases.Loong processors have found their niche inhigh-performance computing environments, such as scientific simulations, weather forecasting, and computational fluid dynamics. They are also utilized in certain server and workstation applications where performance is the primary consideration. Additionally, the Loong architecture has garnered interest from the Chinese government and military for national security and defense applications, as it provides a domestic alternative to foreign-made processors.On the other hand, Dragon processors are primarily targeted at cloud computing and data center infrastructure. Their energy-efficient design and scalability make them well-suited for powering large-scale cloud services, web servers, and distributedcomputing applications. Companies like Amazon and Google have already begun deploying Dragon-based processors in their data centers, taking advantage of their cost-effectiveness and power savings.Future Outlook and Implications:As technology continues to evolve, both the Loong and Dragon processor architectures are poised to play significant roles in shaping the future of computing.For the Loong processors, the primary challenge lies in gaining wider adoption and software ecosystem support. While China's push for domestic technology has driven the development of the Loong architecture, its adoption outside of specialized domains has been limited. Overcoming this hurdle and fostering a robust software ecosystem will be crucial for the Loong processors to compete on a global scale.The Dragon processors, backed by industry giants like Google and Amazon, have a strong foundation and significant resources invested in their development. As cloud computing and data center demands continue to grow, the need for energy-efficient and scalable processors will likely increase, positioning the Dragon architecture as a compelling solution. However, competition from established players like Intel andAMD, as well as emerging architectures like Arm's Neoverse, will keep the landscape dynamic and competitive.Conclusion:In the ever-evolving world of processors, the Loong and Dragon architectures represent two distinct approaches to addressing the computational demands of our digital age. While the Loong processors excel in high-performance computing and offer a domestic alternative for China, the Dragon processors have carved out a niche in the cloud computing and data center realm, leveraging their energy efficiency and scalability.As a student fascinated by these technologies, I find it exciting to witness the advancements and innovations happening in the processor space. The competition between different architectures and the pursuit of performance, efficiency, and versatility will undoubtedly drive further technological breakthroughs. Regardless of which architecture ultimately prevails, one thing is certain: the relentless pursuit of computing power will continue to shape our digital future in ways we can scarcely imagine.篇3The Loong and Dragon: A Tale of Two Chinese CPUsAs a student of computer science, I've become fascinated by the world of processors and the companies that design them. While most of us are familiar with the big names like Intel and AMD, there are other players in the game, particularly in China. Two such processors are the Loong and the Dragon, both designed and manufactured by Chinese companies. At first glance, they may seem similar, but upon closer inspection, some significant differences emerge.The Loong processor is developed by Loongson Technology Corporation Limited, a company based in Beijing. It is a RISC (Reduced Instruction Set Computer) processor, which means it has a relatively simple instruction set architecture (ISA) compared to more complex designs like x86. The Loong family includes several different models, such as the Loong3A4000 and the Loong3C3000, each with varying levels of performance and power efficiency.One of the key advantages of the Loong processor is its compatibility with the MIPS instruction set, which has been around since the 1980s. This compatibility allows the Loong to run a wide range of existing software that has been compiled for MIPS architectures. Additionally, the Loong processors are designed with a focus on low power consumption, making themsuitable for use in embedded systems and other applications where energy efficiency is crucial.On the other hand, the Dragon processor is developed by Higon Information Technology Co., Ltd., a company based in Tianjin. Unlike the Loong, the Dragon is a CISC (Complex Instruction Set Computer) processor, which means it has a more complex instruction set architecture. The Dragon family includes models such as the Dragon V9, which is designed for use in servers and high-performance computing applications.One of the key advantages of the Dragon processor is its compatibility with the x86 instruction set, which is widely used by many popular operating systems and applications. This compatibility allows the Dragon to run a vast array of software that has been compiled for x86 architectures, without the need for emulation or recompilation. Additionally, the Dragon processors are designed with a focus on high performance, making them suitable for use in demanding applications such as scientific simulations and data processing.Despite their differences, both the Loong and the Dragon processors share a common goal: to reduce China's reliance on foreign-made processors and foster the growth of a domestic semiconductor industry. This goal has become increasinglyimportant in recent years, as tensions between China and the United States have escalated, and concerns over supply chain security have grown.From a technical standpoint, one of the key differences between the Loong and the Dragon processors lies in their instruction set architectures. As mentioned earlier, the Loong is a RISC processor, while the Dragon is a CISC processor. RISC architectures are generally simpler and more energy-efficient, while CISC architectures are more complex and can execute more complex instructions in a single cycle.Another important difference is their respective performance capabilities. While the Loong processors are designed with a focus on low power consumption, they tend to lag behind the Dragon processors in terms of raw computational power. The Dragon processors, on the other hand, are designed to deliver high performance, making them better suited for demanding applications such as scientific simulations and data processing.It's worth noting that both the Loong and the Dragon processors are still relatively new players in the market, and their adoption and development are closely tied to the broader goals of China's semiconductor industry. As such, it's likely that we'llcontinue to see ongoing improvements and innovations in both processor families as time goes on.From a student's perspective, the competition between the Loong and the Dragon processors is fascinating to observe. On one hand, the Loong's compatibility with the MIPS instruction set and its focus on low power consumption make it an interesting option for embedded systems and other applications where energy efficiency is a priority. On the other hand, the Dragon's compatibility with the x86 instruction set and its focus on high performance make it a compelling choice for demanding applications such as scientific simulations and data processing.Ultimately, the choice between the Loong and the Dragon processors will likely depend on the specific needs of the application and the priorities of the user or organization. For students like myself, the opportunity to learn about and work with these processors can be invaluable, as it provides exposure to different architectures and design philosophies.As I continue my studies in computer science, I'll be keeping a close eye on the developments in the Loong and Dragon processor families, as well as the broader landscape of China's semiconductor industry. It's an exciting time to be in this field,and I can't wait to see what the future holds for these homegrown Chinese processors.。

hpc方案工程

hpc方案工程

hpc方案工程Key Components of an HPC SolutionAn HPC solution is comprised of several key components that work together to provide high-performance computing capabilities. These components include:1. Compute Nodes: The compute nodes are the heart of an HPC system, and they are responsible for executing the computational tasks. These nodes are typically high-performance servers with multiple processors, large amounts of memory, and fast interconnects.2. Interconnect: The interconnect is the network that connects the compute nodes and allows them to communicate with each other. A high-speed, low-latency interconnect is essential for ensuring efficient data transfer and synchronization between the compute nodes.3. Storage: HPC systems require a large amount of storage to store the massive amounts of data generated during computational tasks. High-performance storage solutions, such as parallel file systems and object storage, are used to provide fast and reliable data access.4. Software Stack: The software stack is the collection of software tools and libraries that are used to manage and run HPC applications. This includes the operating system, job schedulers, parallel programming models, and scientific computing libraries.Considerations for Designing an HPC InfrastructureWhen designing an HPC infrastructure, there are several important considerations that need to be taken into account. These considerations include:1. Scalability: An HPC system should be designed to scale to accommodate the increasing computational demands of the organization. This includes the ability to add additional compute nodes, storage capacity, and interconnect bandwidth as needed.2. Performance: The performance of an HPC infrastructure is crucial for meeting the requirements of high-performance computing applications. This includes optimizing the compute nodes, interconnect, and storage for maximum performance and efficiency.3. Reliability: An HPC system needs to be highly reliable to ensure uninterrupted operation and minimal downtime. This includes using redundant components, fault-tolerant designs, and reliable data storage solutions.4. Manageability: Managing an HPC infrastructure can be complex, so it is important to design the system with manageability in mind. This includes centralized management tools, monitoring and alerting systems, and automation for common tasks.Benefits of Implementing a Robust HPC SystemImplementing a robust HPC system can provide several benefits to an organization, including:1. Increased Productivity: HPC systems enable researchers and engineers to perform complex simulations and analyses in a fraction of the time it would take with traditional computing systems. This can significantly increase productivity and accelerate time-to-discovery.2. Cost Savings: Although the initial investment in an HPC system can be substantial, the long-term cost savings can be significant. By consolidating workloads onto a single, high-performance system, organizations can reduce the need for multiple lower-performance systems and decrease overall operational costs.3. Competitive Advantage: Organizations that have access to high-performance computing capabilities have a competitive advantage in their respective fields. They can tackle more complex problems, produce higher-quality results, and stay ahead of the competition.4. Flexibility: HPC systems can be used for a wide range of applications, from scientific research to big data analytics. This flexibility allows organizations to leverage their HPC infrastructure across multiple departments and use cases.ConclusionDesigning and implementing an HPC solution requires careful consideration of the key components, infrastructure design considerations, and the potential benefits of high-performance computing. With the right HPC infrastructure in place, organizations can achieve significant productivity gains, cost savings, and a competitive advantage in their respective fields. As the demand for faster and more powerful computing capabilities continues to grow, it is essential for organizations to invest in robust HPC solutions that can meet their specific needs.。

IT单词-H

IT单词-H
hierarchical 层次结构;层阶架构
hierarchical cell structure (HCS) 分级信元结构,分层信元结构
hierarchical database 层次结构数据库
hierarchical file system (HFS) 层次结构档案系统
hierarchical menu 层次结构式操作指引
hardware/software co-design 硬软件协同设计
hardwire 固定线路
hardwired circuit 固定电路
hardwired control logic 固定线路控制逻辑
hardwired logic 固定线路逻辑
harmonic 谐波
harmonic analyzer 谐波分析仪
header 起始码;标头
header error control (HEC) 信头差错控制,报头差错控制
header suppression 数据报头压缩
heap 堆阵
hearing, threshold 听觉阈
heat 热
heat capacity 热容量
heat conduction 热传导
harmonic balance simulator 谐波平衡模拟器
harmonic distortion 谐波失真
harmonic voltage distortion 谐波电压失真
harmonic, even 偶谐波
harmonic, odd 奇谐波
harmonic, sub- 次谐波
high definition television (HDTV) 高清晰度电视

计算机专业常用英语

计算机专业常用英语
17
10. local a. 局部;本地[机]
localhost 本(主)机
比较 remote a. 远程 remote access 远程访问 remote communications 远程通信 remote terminal 远程终端
11. ring network 环形网络 ring topology 环形拓扑
4
比较 model 模型 module 模块 modulo 模(运算)
11. opcode 操作码( operation code ) 12. decode v. 译码
decoder 译码器,解码器,翻译程序
5
2.2 Microprocessor And Microcomputer
1. integrated circuit 集成电路
8. library (程序)库,库
16
9. single threading 单线程处理方式
Within a program, the running of a single process at a time. 在程序中,一次运行一个进程的方式。
single-precision 单精度 single-user computer 单用户计算机 thread 线程;线索 threaded tree 线索树 threading 线程技术
11
16. idle a. 空闲,等待
Operational but not in use. 用来说明处在可操作状态但不在使用。 idle state 空闲状态
12
18. launch v. 启动,激活 19. prototyping 原型法 20. project n. 投影运算 21. workstation 工作站

建筑学英语【完全版】

建筑学英语【完全版】 01.建筑学序码汉文名英文名注释01.1 总论01.0001 建筑学architecture01.0002 建筑物building01.0003 人体测量学anthropometry01.0004 人体尺寸human dimensions01.0005 人体舒适human comfort01.0006 人类行为human behavior01.0007 [人因]工效学human factorengineering01.0008 人类群居学ekistics01.0009 环境心理学environmentalpsychology01.0010 人类生态学human ecology01.0011 建筑功能building function01.0012 建筑类型学building typology01.0013 空间构图space configuration01.0014 领域性territoriality01.0015 建筑经济学building economics01.0016 价值工程学value engineering01.0017 费用效益cost effectiveness01.0018 建筑美学architectural aesthetics 01.0019 艺术格调artistic touch01.0020 建筑几何学architectural geometry 01.0021 建筑形态学architecturalmorphology01.0022 建筑形式architectural form01.0023 建筑风格architectural style01.0024 建筑环境architectural environment 01.0025 环境艺术environmental art01.0026 建筑文化architectural culture01.0027 建筑文脉architectural context01.0028 建筑符号学architectural semiotics 01.0029 模式语言pattern language01.0030 建筑设计方法学architecturaldesign methodology01.0031 无障碍设计barrier free design01.0032 古建筑保护historical buildingpresvervation01.0033 风水学fengshui01.0034 建筑科学building science01.0035 建筑气候学building climatology01.0036 建筑物理[学]building physics01.0037 建筑光学building optics01.0038 建筑热学building thermodymamics,building thermology01.0039 建筑声学building acoustics01.0040 太阳能建筑solar building01.0041 建筑工程building engineering01.0042 建筑标准化buildingstandardization01.0043 建筑模数building module01.0044 模数协调modular coordination01.0045 建筑工业化buildingindustrialization01.0046 工业化建筑体系industrializedbuilding system01.0047 支撑体系support system01.0048 填充体系infill system01.0049 建筑安全building safety01.0050 建筑防灾building disasterprevention01.0051 建筑节能building energyconservation01.0052 减灾学natural disasterprevention01.0053 建筑防火building fire protection 01.0054 建筑抗震building aseismicity01.0055 建筑病理building pathology01.0056 健康建筑healthy building01.0057 建筑综合症synthetic buildingsyndrome,SBS01.0058 建筑保安building security01.0059 防卫性空间defensible space01.0060 建筑性能building performance01.0061 建筑评价building evaluation01.0062 社会影响评价social impactassessment,SIA01.0063 环境影响评价environmental impactassessment,EIA01.0064 建筑测量building surveying01.0065 建筑勘探building geotechnics01.0066 工程施工engineering construction 01.0067 建筑材料building material01.0068 建筑制品building product01.0069 建筑构造architecturalconstruction01.0070 建筑设备系统building servicesystem01.0071 建筑设备building equipment01.0072 建筑设备安装building equipmentinstallation01.0073 建筑设施building facilities01.0074 建筑设施管理building facilitiesmanagement01.0075 建筑装修builidng finishing01.0076 室内装饰interior decoration01.0077 建筑壁画mural01.0078 浅浮雕bas-relief01.0079 建筑维护building maintenance01.0080 建筑修缮building repair01.0081 建筑管理building management01.0082 建筑业building industry01.0083 建筑立法building legislation01.0084 建筑史architectural history01.0085 古典建筑classical architecture01.0086 古典柱式classical order01.0087 古埃及建筑Egyptian arhcitecture01.0088 美索不达米亚建筑Mesopotamianarchitecture01.0089 古希腊建筑Greek architecture01.0090 古罗马建筑Roman architecture01.0091 拜占庭建筑Byzantine architecture 01.0092 罗曼式建筑Romanesque architecture 01.0093 哥特式建筑Gothic architecture01.0094 文艺复兴建筑Renaissancearchitecture01.0095 巴洛克建筑Baroque architecture01.0096 洛可可建筑Rococo architecture01.0097 伊斯兰建筑Islamic architecture01.0098 新艺术运动Art-nouveau Movement01.0099 现代主义modernism01.0100 国际风格International Style01.0101 后现代主义post-modernism01.0102 功能主义functionalism01.0103 构成主义constructivism01.0104 表现主义expressionism01.0105 手法主义mannerism01.0106 折中主义eclecticism01.0107 结构主义structuralism01.0108 新古典主义neoclassicism01.0109 复古主义revivalism01.0110 民族风格national style01.0111 新理性主义neorationalism01.0112 批判地方主义critical regionalism 01.0113 解构主义deconstruction01.0114 反构成主义deconstructivism01.0115 粗野主义brutalism01.0116 文脉主义contextualism01.0117 新陈代谢主义metabolism01.0118 高技术建筑hightech architecture01.0119 乡土建筑vernacular architecture01.0120 有机建筑organic architecture01.0121 国际建筑师协会Union ofInternational Architects, UIA01.0122 亚洲建筑师协会Architects RegionalCouncil Asia, ARCASIA 01.0123 中国建筑学会Architectural Societyof China, ASC01.2 建筑类型及组成01.0124 单层建筑single-story building01.0125 多层建筑multistory building01.0126 高层建筑highrise building, tallbuilding01.0127 超高层建筑super highrisebuilding, supertall building01.0128 摩天楼skyscraper01.0129 活动房屋mobile house01.0130 建筑队群building group01.0131 裙房podium01.0132 楼层floor01.0133 夹层mezzanine01.0134 底层ground floor01.0135 地下室basement01.0136 半地下室sub-basement01.0137 顶层top floor01.0138 房间room01.0139 走廊corridor01.0140 游廊gallery01.0141 入口entrance01.0142 门斗anteroom01.0143 门厅enrtance hall, vestibule01.0144 接待室reception room01.0145 会议室conference room01.0146 值班室janitor's room01.0147 收发室mail/distribution room01.0148 问询处information desk01.0149 衣帽间coat room, cloak room01.0150 开水间water heater room01.0151 卫生间washroom01.0152 厕所toilet01.0153 浴室bathroom01.0154 电话总机房telephone exchangeroom01.0155 电子计算机房computer room01.0156 广播室broadcasting room01.0157 储藏室storage room01.0158 变电间substation01.0159 锅炉间boiler room01.0160 阳台balcony01.0161 平台terrace01.0162 天井light court01.0163 屋前空地frontage01.0164 居住建筑residential building01.0165 人居human habitat01.0166 住房housing01.0167 独户住宅single family house01.0168 多户住宅multi-family house01.0169 联排式住宅row house, terracehouse01.0170 台阶式住宅stepped house,terraced house01.0171 公寓式住宅apartment house01.0172 板式住宅slab block01.0173 点式住宅point block01.0174 跃层式公寓skip-floor aparment01.0175 外廊式公寓exterior-corridor typeapartmnet01.0176 步行上楼式公寓walk-up apartment01.0177 电梯式公寓elevator apartment01.0178 平房one-story house, bungalow01.0179 农舍cottage01.0180 别墅villa01.0181 庭院式住宅courtyard house01.0182 两层独立公寓maisonette01.0183 宿舍dormitory01.0184 青年公寓youth apartment01.0185 老年公寓house for the elderly01.0186 养老院nursing home01.0187 公共活动室commom room, communityroom01.0188 卧室bedroom01.0189 起居室living room01.0190 书房study01.0191 餐室dining room01.0192 厨房kitchen01.0193 壁柜wall unit, case unit01.0194 吊柜hanging cabinet01.0195 地窖cellar01.0196 教育建筑educational building01.0197 大学建筑university building01.0198 学院建筑institute building,collehe building01.0199 专科学校建筑specail collegebuilding01.0200 中学建筑secondary schoolbuilding01.0201 职业学校建筑professional schoolbuilding01.0202 小学建筑elementary schoolbuilding01.0203 幼儿园kindergarten01.0204 寄宿制托儿所nursery01.0205 全日制托儿所day-care center01.0206 教室classroom01.0207 阶梯教室lecture theater01.0208 电化教室audio-visual classroom01.0209 实验教室laboratory01.0210 美术教室artroom 01.0211 音乐教室music room01.0212 劳作教室handicraft room01.0213 实验工厂practice workshop01.0214 儿童活动室children's playroom01.0215 哺乳室nursing room01.0216 配乳室milk kitchen01.0217 隔离室isolation room01.0218 学生中心students' center01.0219 游戏场地playground01.0220 黑板blackborad01.0221 讲台forum01.0222 文化建筑cultural building01.0223 图书馆library01.0224 博物馆museum01.0225 科技馆science museum01.0226 美术馆art museum01.0227 画廓gallery01.0228 文化中心cultural center01.0229 展览馆exhibition hall01.0230 天文馆planetarium01.0231 水族馆aquarium01.0232 自然博物馆natural history museum 01.0233 青年中心youth center01.0234 妇女中心women's center01.0235 陈列室display room01.0236 展览室exhibition room01.0237 阅览室reading room01.0238 阅览间reading carrel01.0239 微缩图书阅览室microfilm readingroom01.0240 善本图书阅览室rare books readingroom01.0241 文献资料阅览室referenceliterature room01.0242 目录厅catalogue room01.0243 出纳处lending department01.0244 编目室cataloging room01.0245 鉴定室authentication room01.0246 研究室research room01.0247 复印室copying room01.0248 装订室binding room01.0249 书库stack room01.0250 开架管理open stack management01.0251 闭架管理closed stack management 01.0252 书架book shelf01.0253 展览架display shelf01.0254 体育建筑sport building01.0255 体育场stadium01.0256 室内体育场indoor stadium01.0257 体育馆sports hall01.0258 游泳馆swimming hall, natatorium01.0259 健身房gymnasium01.0260 田径场track field01.0261 足球场football court, soccercourt01.0262 篮球场basketball court01.0263 排球场volleyball court01.0264 手球场handball court01.0265 垒球场softball court01.0266 网球场tennis court01.0267 羽毛球场badminton court01.0268 壁球场squash court01.0269 棒球场baseball field01.0270 射击场shooting range01.0271 射箭场archery01.0272 赛马场race course01.0273 斗牛场bullfighting arena01.0274 自行车赛场velodrome01.0275 滑冰场skating rink01.0276 水上运动场aquatic sport waters 01.0277 冰球场ice hockey rink01.0278 曲棍球场hockey field01.0279 高尔夫球场golf course01.0280 跳伞俱乐部parachute club01.0281 保龄球场bowling club01.0282 桑拿浴室sauna bathroom01.0283 按摩室massage room01.0284 练习场warm-up01.0285 看台grandstand01.0286 活动看台movable stand01.0287 裁判席referee's seat01.0288 运动员席sportsman's seat01.0289 固定座位bleacher01.0290 场地field01.0291 跑道track01.0292 跳高场地high jump runway01.0293 跳远场地long jump runway01.0294 三级跳远场地triple jump runway 01.0295 撑竿跳高场地pole vault runway 01.0296 标枪投掷区javelin throwing zone 01.0297 铅球投掷区hammer throwing zone 01.0298 铁饼投掷区discus throwing zone 01.0299 障碍赛跑道hurdle race track01.0300 跳水池diving pool01.0301 武术场地martial arts ground01.0302 举重场地weightlifting platform 01.0303 摔跤场地wrestling ring01.0304 拳击比赛台boxing ring01.0305 击剑场地fencing area01.0306 游泳池swimming pool01.0307 泳道swimming lane01.0308 跳水台diving platform 01.0309 体操台gymnastic floor01.0310 单杠horizontal bar01.0311 双杠parallel bars01.0312 高低杠uneven parallel bars01.0313 吊环rings01.0314 鞍马vaulting horse01.0315 跳马pommel horse01.0316 自由体操free exercise01.0317 平衡木halancing beam01.0318 篮球架backboard01.0319 球门goal01.0320 记分牌scoreboard01.0321 跳伞塔parachuting tower01.0322 观演建筑theatrical building01.0323 剧院theater, playhouse01.0324 表演艺术中心performing artscenter01.0325 歌剧院opera house01.0326 芭蕾舞剧院ballet theater01.0327 京剧院Beijing opera theater01.0328 木偶剧院puppet play theater01.0329 露天剧场open air theater,amphitheater01.0330 话剧院drama theater01.0331 实验剧场experimental theater01.0332 电影院cinema, movie theater01.0333 全景电影院panoramic cinema01.0334 立体电影院stereophonic cinema01.0335 汽车影院drive-in theater01.0336 音乐厅concert hall01.0337 交响乐厅symphony hall01.0338 独唱独奏厅recital hall01.0339 观众厅auditorium01.0340 座席容量seating capacity01.0341 多用途观众厅multiuse auditorium 01.0342 多媒体演出multimedia performance 01.0343 地面升起rakde floor01.0344 视线sight line01.0345 排距row spacing01.0346 错排座席staggered seating01.0347 纵过道longitudinal aisle01.0348 横过道transverse aisle01.0349 天花反射板ceiling reflector01.0350 池座层orchestra level01.0351 池座前排stall01.0352 楼层挑台balcony01.0353 楼面层tier01.0354 包厢box01.0355 迟到席late-comers' seat01.0356 舞台stage01.0357 箱形舞台proscenium frame stage01.0358 旋转舞台revolving stage01.0359 凸出舞台thrust stage01.0360 中心舞台arena stage01.0361 活动舞台flexible stage01.0362 基本台main stage01.0363 侧台side stage01.0364 转台turntable01.0365 升降台elevating stage, stagelift01.0366 车台wagon stage01.0367 表演区acting area01.0368 乐池orchestra pit01.0369 台唇apron, forestage01.0370 台口proscenium01.0371 假台口 false proscenium,adjustable proscenium01.0372 大幕front curtain, house tabs 01.0373 防火幕fire curtain01.0374 天幕cyclorama01.0375 边幕wing sets01.0376 声罩acoustic shell01.0377 布景stage scenery01.0378 道具stage property, prop01.0379 银幕film screen01.0380 宽银幕wide film screen01.0381 立体银幕cinemascope screen01.0382 天桥fly gallery01.0383 灯光渡桥traveling lightinggallery01.0384 舞台塔fly tower01.0385 舞台吊杆flybar, barrten01.0386 手动吊杆hand-driven battern01.0387 电动吊杆motorized winch batten 01.0388 单式吊杆single purchasecounterweight batten01.0389 复式吊杆double purchasecounterweight batten01.0390 排烟窗vent window01.0391 舞台灯光stage lighting01.0392 耳光wall-slot lighting01.0393 面光front lighting01.0394 侧光side lighting01.0395 放映室projection booth,projection room01.0396 放映孔projection port01.0397 观察窗observation port01.0398 后台back stage01.0399 化妆室dressing room, make-uproom01.0400 排练厅rehearsal room01.0401 演员休息室green room 01.0402 舞台监督室stge manager's room 01.0403 灯光控制室light control room01.0404 音响控制室sound control room01.0405 前厅foyer01.0406 售票处box office01.0407 疏散出口emergency exit01.0408 娱乐建筑recreation building01.0409 娱乐中心recreation center01.0410 舞厅ballroom01.0411 俱乐部clubhouse01.0412 夜总会night club01.0413 舞池dancing floor01.0414 医[疗]卫[生]建筑medical building 01.0415 医院hospital01.0416 综合医院general hospital01.0417 精神医院mental health hospital 01.0418 口腔医院dental hospital01.0419 妇科医院gynaecologic hospital01.0420 妇产医院obstetric hospital01.0421 儿科医院pediatric hospital01.0422 传染医院contagious diseasehospital01.0423 肿瘤医院tumour hospital01.0424 眼科医院ophthalmologic hospital 01.0425 疗养院sanatorium01.0426 急球中心emergency care center 01.0427 康复中心rehabilitation center01.0428 中医院traditional Chinesemedical hospital01.0429 医疗站medical station01.0430 卫生所health center01.0431 防疫站health and quarantinestation01.0432 门诊部outpatient department01.0433 急诊部emergency department01.0434 治疗部examination-treatmentcenter01.0435 理疗部therapeutic department01.0436 化疗部chemical treatmentdepartment01.0437 手术部operationdepartment,surgical suite01.0438 针灸部acupuncture department01.0439 放射部radioactive department01.0440 分娩部delivery department01.0441 住院部ward01.0442 同位素室radioisotope unit01.0443 化验室testing laboratory01.0444 挂号处admitting office01.0445 候诊室waiting lounge01.0446 诊室consulting room01.0447 药房pharmacy01.0448 病房patients' room01.0449 隔离病房isolation ward01.0450 阳光室solaria01.0451 营养厨房dietary kitchen01.0452 手术准备室preparation room01.0453 手术消毒室sterilizing room01.0454 麻醉室anesthesia room01.0455 手术洗涤室scrub-up01.0456 停尸房mortuary01.0457 解剖室autopsy room01.0458 中心供应站central supply01.0459 工业建筑industrial building01.0460 火力发电厂steam power station01.0461 选煤厂coal preparation plant01.0462 炼油厂oil refinery01.0463 液化石油气厂liquid petroleum gasplant, LPG plant01.0464 自来水厂water supply andpurification plant01.0465 钢铁厂iron and steel works01.0466 铝厂aluminium factory01.0467 焦化厂coke plant01.0468 机械厂machine making factory01.0469 汽车厂automobile factory01.0470 拖拉机厂tractor factory01.0471 机车车辆厂locomotive and coachwagon factory01.0472 机床厂machine tool factory01.0473 电机厂electric motor factory01.0474 冷冻机厂refrigerating machinewagon01.0475 锅炉厂boiler making factory01.0476 轴承厂bearing factory01.0477 齿轮厂gear factory01.0478 电镀厂electroplating factory01.0479 电解厂electrolysis tactory01.0480 建筑机械厂building equipmentfactory01.0481 建筑材料厂building materialfactory01.0482 建筑五金厂building hardwarefactory01.0483 建筑陶瓷厂building ceramicsfactory01.0484 水泥厂cement works01.0485 砖瓦厂brick and tile factory01.0486 木材厂woodworking factory01.0487 大理石厂marble factory01.0488 精密仪器厂precision instrumentfactory 01.0489 仪器仪表厂instument and meterfactory01.0490 钟表厂clock and watch factory01.0491 眼镜厂spectacles factory01.0492 化工厂chemical plant01.0493 塑料厂plastics plant01.0494 制药厂pharmaceutical factory01.0495 油漆厂paint factory01.0496 制管厂piping factory01.0497 皮毛加工厂leather factory01.0498 纺织厂textile mill01.0499 针织厂knitting mill01.0500 印染厂dyeing plant01.0501 服装厂tailor shop01.0502 鞋厂shoemaking factory01.0503 工艺美术厂handicraft factory01.0504 印刷厂printing press01.0505 玩具厂toy making factory01.0506 面包厂bakery01.0507 面粉厂flour mill01.0508 食品厂food products factory01.0509 清真食品厂muslem food productsfactory01.0510 豆制品厂bean products factory01.0511 饮料厂beverage01.0512 酿酒厂winery01.0513 啤酒厂brewery01.0514 屠宰厂butchery01.0515 肉类加工厂meat products factory 01.0516 卷烟厂cigarette factory01.0517 茶厂tea factory01.0518 糖厂sugar mill01.0519 厂房factory building01.0520 车间workshop01.0521 堆场storage yard01.0522 原料加工车间raw material handingplant01.0523 治炼车间smelting shop01.0524 铸造车间casting shop01.0525 锻造车间forging shop01.0526 冲压车间drop forging shop01.0527 焊接车间welding shop01.0528 金工车间machine-cutting shop01.0529 木工车间carpentry shop01.0530 加工车间 processing plant01.0531 装配车间assembly plant01.0532 冷拉车间cold-drawing shop01.0533 热处理车间heat-treatment shop01.0534 电镀车间electroplating shop01.0535 电解车间electrolysis shop01.0536 油漆车间painting shop01.0537 机修车间machine repair shop01.0538 中试车间pilot plant01.0539 烧制车间furnace room01.0540 精密车间precision workshop01.0541 洁净车间dust-proof workshop,clearoom01.0542 中央试验室central laboratory01.0543 动力站power plant01.0544 锅炉房boiler house01.0545 煤气发生站gas generating station 01.0546 压缩空气站compressed air station 01.0547 氧气站oxygen station01.0548 乙炔站acetylene generatingstation01.0549 充电站battery recharge room01.0550 仓库warehouse, godown01.0551 总仓库central warehouse01.0552 成品库final product storage01.0553 装卸站台loading platform01.0554 厂前区administration quarter01.0555 生活间changing room, lockerroom01.0556 吊车crane01.0557 汽车地磅truck-weighing platform 01.0558 水塔water tower01.0559 电瓶车库battery car room01.0560 商业建筑commercial building01.0561 百货商店department store01.0562 超级市场supermarket01.0563 自选商场self service store01.0564 购物中心shopping center01.0565 市场market hall01.0566 农贸市场farm product market01.0567 鱼市fishmonger, fish stall01.0568 肉市butcher shop01.0569 禽市poultry stall01.0570 蛋市egg stall01.0571 果市fruit stall01.0572 菜市场vegetable market01.0573 批发商店wholesale store01.0574 零售商店retail store01.0575 专卖店speciality shop01.0576 粮店grain store01.0577 副食店foodstuffs store01.0578 食品店provisions shop01.0579 熟食店delicatessen shop01.0580 点心铺pastry store01.0581 杂货铺grocery01.0582 饭馆restaurant01.0583 饮食店cafeteria01.0584 小吃店snack bar 01.0585 快餐店fast food restaurant01.0586 茶馆 tea house01.0587 包子铺stuffed bun house01.0588 食堂canteen01.0589 中药店traditional Chinsesmedicine store01.0590 西药店drugstore01.0591 布店cloth store01.0592 呢绒绸缎店silk and wool fabricstore01.0593 服装店clothing store01.0594 鞋帽店hat and shoes store01.0595 床上用品店bed linens store01.0596 家具店furniture store01.0597 眼镜店spectacles store01.0598 钟表店clocks and watches store01.0599 文具用品店stationary store01.0600 书店bookstore01.0601 花店flower shop01.0602 服饰店haberdashery01.0603 洗染店laundering and dyeingshop01.0604 干洗店dry cleaning shop01.0605 工艺美术品店arts and caftsstore01.0606 金银手饰店jewelry store01.0607 珠宝店jewelry shop01.0608 照相馆photo studio01.0609 理发店barber shop01.0610 美发廊hair salon01.0611 美容院beauty parlour01.0612 浴堂bath house01.0613 旅馆hotel01.0614 旅店inn01.0615 宾馆guesthouse01.0616 汽车旅馆motel01.0617 银行bank01.0618 储蓄所saving bank01.0619 证券交易所stock exchange01.0620 营业厅shopping hall01.0621 售货区Sales area01.0622 顾客活动区customers' area01.0623 橱窗shop window, show window01.0624 收款柜台cashier01.0625 货架shelf01.0626 货柜counter01.0627 卸货间delivery room01.0628 卸货台delivery platform01.0629 主食加工间staple food processingroom01.0630 副食加工间non-staple foodprocessing room01.0631 主食库staple food storage01.0632 副食库non-staple food storage01.0633 调料库condiment storage01.0634 备餐间pantry, food preparationroom01.0635 食具洗涤消毒间ware washing andsterilizing room01.0636 烧火间firing sector01.0637 冷[藏]库cold storage01.0638 冷藏间refrigerated storage room01.0639 冷冻间freezed storage room01.0640 制冻间ice-mking room01.0641 客房guest room01.0642 套间客房suite01.0643 总统客房presidential suite01.0644 单床间single-bed room01.0645 双床间double room01.0646 休息厅looby, loung01.0647 接待厅reception hall,front desk01.0648 总服务台reception desk01.0649 餐厅dining hall01.0650 中餐厅Chinese restaurant01.0651 西餐厅west restaurant01.0652 咖啡厅coffee house, coffee shop01.0653 风味餐厅speciality restaurant01.0654 宴会厅banquet hall01.0655 多功能厅multi-function hall01.0656 酒巴间bar01.0657 洗手间rest room01.0658 洗衣房laundry01.0659 交通建筑transportain building01.0660 航空港airport01.0661 候机楼air-terminal01.0662 售票厅booking hall01.0663 候机厅departure hall01.0664 行李托运站baggage check-in01.0665 旅客通道passenger concourse01.0666 海关检查处customs examination01.0667 登机口boarding gate01.0668 行李提取站bagggage claim01.0669 停机坪apron01.0670 直升机坪helistop01.0671 指挥塔command tower01.0672 飞机跑道runway01.0673 火车站railway terminal, railwaystation01.0674 汽车客运站bus passenger terminal,bus passenger station01.0675 水路客运站waterway passengerterminal, watermqy passengerstation01.0676 候车室waiting lounge01.0677 行李室luggage room01.0678 站台railway platform01.0679 站台雨棚platform shed01.0680 灯塔beacon, lighthouse01.0681 汽车库garage01.0682 多层车库multistory garage01.0683 加油站petrol filling station01.0684 汽车修理站car repair pit01.0685 汽车洗车台car wash01.0686 岗亭sentry box01.0687 农业生产建筑farm building01.0688 粮库granary01.0689 筒仓silo01.0690 种子库seed storage01.0691 选种室seed selection room01.0692 粮食加工厂grain processing plant 01.0693 晒场sunning ground01.0694 温室greenhouse01.0695 塑料大棚plastic-cover greenhouse 01.0696 农机站farm machinery station01.0697 保养间maintenance shop01.0698 农具棚agricultural tools shed01.0699 零件库machine parts storage01.0700 农机修理站agricultural machinerepair station01.0701 种马场stallion barn01.0702 役马场military horse harn01.0703 马厩horse stable01.0704 乳牛场dairy farm01.0705 牛舍stanchion barn01.0706 公牛舍bull barn01.0707 犊牛舍calf barn01.0708 挤乳间milking parlour01.0709 牛乳处理间milkhouse01.0710 养鸡场poultry yard01.0711 鸡舍hencoop01.0712 养猪场pig farm, hog lot01.0713 猪舍pigsty01.0714 饲料储存处feed storage01.0715 饲料加工间feed processing plant 01.0716 食槽manger01.0717 饮水池drinking water pool01.0718 人工采精室sperm collection room 01.0719 授精配种室sperm fertilizationroom01.0720 病兽隔离室isolation barn01.0721 兽医站veterinary stastion01.0722 积肥场fertilizer yard01.0723 沼气池biomass pool01.0724 农业服务中心agricultural servicecenter01.0725 办公建筑office building01.0726 多层办公楼multistory office01.0727 高层办公楼office tower01.0728 行政办公楼administrative building 01.0729 专用办公楼special-use officebuilding01.0730 综合性办公楼multiuse officebuilding01.0731 智能办公楼intelligent building,smart building01.0732 单间式布局private office layout 01.0733 大空间布局open landscape layout 01.0734 单走道布局single-corridor layout 01.0735 双走道布局double-corridor layout 01.0736 单外廊布局singleexterior-corridor layout01.0737 双外廊布局doubleexterior-corridor layout01.0738 办公室office room01.0739 设计室design studio01.0740 绘图室driafting room01.0741 档案室file room01.0742 晒图室reproduction room01.0743 图档室drawings and documentsroom01.0744 打字室typing room01.0745 模型室model shop01.0746 公共建筑public building01.0747 国际会议大厦internationalconvertion hall01.0748 国家会议大厦state conventionhall01.0749 市政厅municipal hall, city hall 01.0750 会议厅assembly hall01.0751 礼堂auditorium01.0752 主席台presidium01.0753 同声传译控制室simultaneousinterpretation booth01.0754 翻译室interpreters' room01.0755 监听室monitor room01.0756 扩音控制室broadcasting controlroom01.0757 电视转播室television transmissionroom01.0758 电视转播车television transmissionvehicle01.0759 总指挥室general director's room 01.0760 法院courthouse 01.0761 法庭courtroom01.0762 法官室judge's suite01.0763 秘书室law clerk's room01.0764 律师室lawyer's room01.0765 证人室witness' room01.0766 拘留室detention room01.0767 警察局police station01.0768 派出所police substation01.0769 监狱prison, jail01.0770 牢房prison cell01.0771 接收牢房incarceration cell01.0772 隔离牢房isolation cell01.0773 检查室examination room01.0774 讯问处interrogation room01.0775 看守室guards' room01.0776 瞭望室watchtower01.0777 消防站fire station01.0778 消防车库fire engine room01.0779 训练塔training tower01.0780 通信建筑communication building 01.0781 邮局post office01.0782 电信楼telecommunication building 01.0783 营业柜台clerk counter01.0784 书写台writing counter01.0785 电话间telephone booth01.0786 广播楼broadcasting station01.0787 电视中心television center, TVcenter01.0788 卫星通信地面站satellite groundstation01.0789 录音室recording room01.0790 演播室studio01.0791 微波塔microwave transmissiontower01.0792 电视塔TV transmission tower01.0793 电影制片厂motion picture studio 01.0794 科学建筑science building01.0795 研究中心research center01.0796 试验楼laboratory building01.0797 试验室laboratory room01.0798 物理试验室physics laboratory01.0799 化学试验室chemistry laboratory 01.0800 光学试验室optics laboratory01.0801 声学试验室acoustic laboratory01.0802 混响室reverberationroom01.0803 隔声室soundproof room01.0804 消声室sound attenuation room,anechoic room01.0805 热工试验室thermal sciencelaboratory01.0806 生物试验室biology laboratory01.0807 机械性能试验室mechanicalproperties laboratory01.0808 无菌室bacteria-free room01.0809 计量室metrology room01.0810 天平室balance room01.0811 电子显微镜室electronic microscopyroom01.0812 试验台testing counter01.0813 通风罩ventilation hood01.0814 天文台observatory01.0815 气象台meteorological station01.0816 宗教建筑religious building01.0817 庙temple01.0818 寺buddhist temple01.0819 庵nunnery01.0820 祠shrine01.0821 观taoist temple01.0822 山门temple gate01.0823 大殿main temple hall01.0824 经堂scripture hall01.0825 钟楼bell tower01.0826 鼓楼drum tower01.0827 纪念建筑memorial building01.0828 纪念碑memorial monument01.0829 台座pedestal01.0830 纪念堂memorial hall01.0831 纪念牌坊monumental gateway01.0832 地下建筑underground building01.0833 人防地下室air-raid shelter01.0834 防核尘地下室fallout shelter01.0835 地铁车站subway station, metrostation01.0836 地下商场underground store01.0837 地下窑居underground dwelling01.0838 地下珍宝馆underground treasurechamber01.0839 地下车库underground garage01.0840 地下仓库underground warehouse01.0841 地下金库underground goldtreasury01.0842 地下冷库underground cold storage 01.0843 地下粮仓underground granary01.0844 地下试验室underground testinglaboratory01.0845 生土建筑earth building01.0846 窑居cave dwelling01.0847 夯土房rammed earth construction 01.0848 土筑房earthwork house01.0849 土坯房adobe house01.0850 覆土建筑earth-coveredconstruction 01.0851 自行车棚bicycle shed01.0852 围墙fence wall, enclosure wall 01.0853 大门entrance gate, main door01.0854 门房gatehouse01.3 建筑设计01.0855 设计管理design administration01.0856 建筑法buliding law,buildingordinance01.0857 建筑师注册法architects'registration ordinance 01.0858 职业工程师法professionalengineers' law01.0859 建筑主管机关building authority01.0860 建筑设计院building design institute 01.0861 建筑设计所building design office01.0862 建筑师architecf01.0863 结构工程师structural engineer01.0864 职业工程师professional engineer01.0865 咨询工程师design consultant01.0866 估价师estimator, quantity surveyor 01.0867 设计委托design commission01.0868 设计协议design agreement01.0869 设计合同design contract01.0870 设计义务design liability01.0871 损害义务tort liability01.0872 设计费design fee01.0873 收费标准fee scale01.0874 百分比收费percentage cost fee01.0875 单位面积收费unit area fee01.0876 总额收费lump sum fee01.0877 成本附加费cost plus fee01.0878 资质审查qualification01.0879 注册registration01.0880 执照license01.0881 合伙制设计事务所design partnership 01.0882 设计规范design code01.0883 设计标准design approval01.0884 职业道德守则code of professionalethics01.0885 设计程序design process01.0886 可行性研究feasibility study01.0887 机会研究opportunity study01.0888 建筑策划architectural programming 01.0889 场址选择site selection01.0890 需求预测demand forecasting01.0891 价格分析price analysis01.0892 建筑条件construction conditions01.0893 设计方案design alternative01.0894 劳动定员manpower quota01.0895 实施计划implementation schedule01.0896 投资额investment cost。

云计算Cloud-Computing-外文翻译

毕业设计说明书英文文献及中文翻译学生姓名:学号:计算机与控制工程学院:专指导教师:2017 年 6 月英文文献Cloud Computing1。

Cloud Computing at a Higher LevelIn many ways,cloud computing is simply a metaphor for the Internet, the increasing movement of compute and data resources onto the Web. But there's a difference: cloud computing represents a new tipping point for the value of network computing. It delivers higher efficiency, massive scalability, and faster,easier software development. It's about new programming models,new IT infrastructure, and the enabling of new business models。

For those developers and enterprises who want to embrace cloud computing, Sun is developing critical technologies to deliver enterprise scale and systemic qualities to this new paradigm:(1) Interoperability —while most current clouds offer closed platforms and vendor lock—in, developers clamor for interoperability。

sigcomm2019-hpcc高精度拥塞控制-alibaba

• Slow convergence ➢ No precise feedback indicating how much to increase/decrease • Standing queue ➢ Feedback relies on queue • Complex parameter tuning ➢ No precise feedback need heuristics: lots of parameters
批注本地保存成功开通会员云端永久保存去开通
HPCC: High Precision Congestion Control
Yuliang Li
Rui Miao, Hongqiang Harry Liu, Yan Zhuang, Fei Feng, Lingbo Tang, Zheng Cao, Ming Zhang, Frank Kelly, Mohammad Alizadeh, Minlan Yu
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• Feedback (ECN/delay) is imprecise
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英特尔 AVX-512 技术指南 - 数据流工作负载的超并行多哈希计算说明书

Technology GuideIntel® AVX-512 - Ultra Parallelized Multi-hash Computation for Data Streaming WorkloadsAuthorsLeyi Rong Yipeng Wang Weigang Li Hongjun Ni 1IntroductionSketch-based algorithms1 are emerging technologies that are broadly used in network measurement and network telemetry workloads, generating approximate estimations of networking flows. It is used to prevent distributed denial-of-service (DDoS) attacks, monitor network usage, and for various Quality of service (QoS) purposes. Compared to hash tables or other lossless algorithms, sketch-based algorithms are designed with a compact and optimized data structure for memory efficiency and computing throughput.The core data structure, i.e. Sketch, consists of a two-dimensional (2D) array. Each row of the array corresponds to a resulting digest space indexed by an independently computed hash function. With more independent hash functions, more accurate estimation results can be provided. Nevertheless, increasing the number of hash computations increases the amount of CPU consumption, which may prevent the application from processing high-volume networking traffic. Thus, a high throughput multi-hash computation methodology is desired in this domain. Note that the term "multi-hash" in this technology guide does not correspond to the following Intel whitepaper2, which by contrast proposes extensions to cryptographic hash algorithms.This technology guide proposes a novel model to accelerate multi-hash computation by leveraging Intel® Advanced Vector Extensions 512 (Intel® AVX-512) instructions. This proposed innovation achieves an average performance gain of up to 2x for the critical key-add and key-lookup operations, compared with the standard CRC-32 instruction approach for state-of-the-art algorithms. Moreover, as different workloads have diverse requirements for the hashing algorithm (randomness, cryptography, small data velocity, etc.), our proposed model supports algorithm customization for different purposes. The solution provides developers with a robust, flexible foundation to build high-throughput networking measurement and monitoring applications. By leveraging its optimized data plane, implementers can achieve excellent performance across a diverse range of network telemetry workloads.This document is part of the Network & Edge Platform Experience Kits.1Finding Frequent Items in Data Streams. In Proc. of ICALP.2Multi-Hash: A Family of Cryptographic Hash Algorithm Extensions. Intel White Paper (July 2012)Table of Contents1Introduction (1)1.1Terminology (3)1.2Reference Documentation (3)2Overview (3)3Technology Description (4)3.1Background (4)3.2Motivation (5)3.3New Proposal Model (5)3.3.1Parallel Hash Computation with Splitting Input and Vectorized Seeds by Leveraging Intel® AVX-512 (6)3.3.2Accelerate Multiplication and Addition Operations by Leveraging Intel AVX-512 IFMA Instruction in HashComputation (8)3.3.3Accelerate Sketch Counter Updates by Leveraging Intel AVX-512 Gather and Scatter Instructions (8)4Performance Benchmarking (9)4.1Benchmarking Platform (9)4.2Benchmarking Results (9)5Summary (10)FiguresFigure 1.Example Sketch data structure (4)Figure 2.Example Bloom filter algorithm (5)Figure 3.Example Sketch algorithm with different seeds for hash functions (5)Figure 4.Ultra parallelized multi-hash computation workflow (6)Figure 5.Parallelized initializing the multi-hash computation (7)Figure 6.Continuously processing the input data as 8-byte-block (7)Figure 7.Processing the remaining input data less than 8 Bytes (8)Figure 8.Performance benchmarking on Sketch Add compared with CRC-32 instruction (10)Figure 9.Performance benchmarking on Sketch Lookup compared with CRC-32 instruction (10)TablesTable 1.Terminology (3)Table 2.Reference Documents (3)Table 3.Performance Benchmark Platform Configuration (9)Document Revision History001 August 2023 Initial release.1.1TerminologyTable 1. TerminologyCRC-32 32-Bit Cyclic Redundancy CheckDPDK Data Plane Development Kit ()IFMA Integer Fused Multiply AddIntel® AVX Intel® Advanced Vector Extensions (Intel® AVX) ISA Instruction Set ArchitectureMAD Multiply-Add-Divide1.2Reference DocumentationTable 2. Reference DocumentsDPDK Official Website https:///Intel® 64 and IA-32 Architectures Software Developer's Manual https:///content/www/us/en/developer/articles/technical/intel-sdm.htmlhttps:///content/www/us/en/develop/articles/intelsdm.htmlIntel® 64 and IA-32 Architectures Software Optimization Reference Manual https:///content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf2OverviewTo our best knowledge, there is no highly parallel solution for multi-hash computation. We came up with the following three alternative solutions as the initial options:ing specific hardware (for example, network adapter, FPGA) to do the hash computationing a long-output-size hash function(for example, SHA3-5123), then evenly dividing the results into multiple parts forthe multi-hash resultsing CRC-32 instruction accelerated hash function with different seedsThere are some disadvantages of the aforementioned proposed solutions:1.Specific hardware (for example, network adapter): The hashing algorithm runs in specific hardware that is normallyfixed and rigid, therefore, it can not meet the diverse requirements of the hashing algorithm used in various data stream algorithms. Also, data stream analysis applications are usually run at the top layer of the networking stack. For example, many firewalls and networking telemetry applications run after the networking packets are decrypted anddecompressed. Sending data stream back to the hardware devices is subject to long device communication latency. It's better to produce the hash result close to the workload that runs on the CPU.2.Long-output-size hash function: Hashing algorithms such as SHA3-512 can generate long hash values that can be usedto substitute multiple shorter hashing computations. But there are several caveats. 1) Existing long-output hashingalgorithms are not flexible enough to be customized for performance-efficiency trade-offs. 2) The algorithm must have an excellent avalanche effect, i.e., when an input changes slightly, the output should change significantly. This requires more complex arithmetic, which results in lower performance. The performance on Intel® Xeon® Processor E3-1220 v5 of SHA3-512 is 164cpb4 (cycle per byte) with 8 byte of input size. Although the performance benchmarking platforms are not the same, the existing long-output hashing algorithm falls significantly behind in terms of throughput whencompared to the proposed model of 4.5 cpb.3.CRC-32 instruction: Intel has introduced hardware CRC-32 computation ISA to accelerate CRC hashing computation.But the CRC-32 based implementation lacks flexibility and parallelism compared to our proposal. The performance data shows that our proposal achieves 2x throughput by using Intel AVX-512 with a customized hashing algorithm compared to CRC-32 based algorithm.3SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions. NIST (August 2015)4https:///wiki/Secure_Hash_Algorithms#Comparison_of_SHA_functionsThis technology guide proposes a novel model to process multiple hash functions in parallel by leveraging Intel AVX-512 instruction sets. Various data stream algorithms, such as sketch as well as other classic algorithms like Bloom filter, could benefit from this proposal.The model consists of three key ideas:•Parallel hash computation with splitting input and vectorized seeds by leveraging Intel AVX-512•Accelerate multiplication and addition arithmetic using Intel AVX-512 IFMA instruction in hash computation•Accelerate sketch counter updates by leveraging Intel AVX-512 gather and scatter instructions3Technology Description3.1BackgroundMulti-hash computation (multiple independent hashing functions) has been broadly used in many algorithms of the data stream analysis domain, like sketch-based algorithms, Bloom filter, etc. Figure 1 shows the fundamental data structure of a sketch as an example (a d x m 2D array). Sketch-based algorithms are popular and effective approaches used in the network measurement and network monitoring domains to estimate the size of networking flows. It is used to prevent DDoS attacks, monitor networking usages, and for various QoS purposes.In a common scenario, when a data stream (for example, a stream of networking packets) goes through the system, the sketch-based algorithm will process d times of independent hash computations for each packet. The corresponding hash digests, i.e., the results generated by each hash function, will be used to index the counter among m counters (bins) of each row. For each packet (key) encountered, the corresponding counter will be incremented or decremented. The eventual counter values are summarized from all d arrays that can be used to estimate the frequency of the key (i.e., the size of a networking flow). The multi-hash computation will help to improve the accuracy of the frequency estimation results, especially for heavy hitter data streams. In other words, more hashing computations tend to result in better accuracy.Figure 1. Example Sketch data structureBesides sketch, Bloom filter based algorithm also leverages multiple independent hash functions to reduce the false positives when querying certain items in a data set. As shown in Figure 2, the example Bloom filter array consists of 12 elements, and a set of four independent hash functions are used to update the array for each key.Figure 2. Example Bloom filter algorithm3.2MotivationBased on our analysis and performance profiling of a state-of-the-art sketch-based algorithm, hash computation is the number one performance hotspot of the total CPU consumption. As high throughput networking applications (100Gb – 1Tb) become more and more common in data center use cases, it is critical to develop fast multi-hashing algorithms with minimal CPU consumption.Our investigation shows that existing CPU-based algorithms are not flexible nor performant enough to meet high throughput requirements. One may argue that specialized hardware (for example, network adapters, FPGA) can be used to compute hash instead of using CPU. However, our investigation found networking profiling tasks tend to require maximum flexibility and could be high in the networking stack. In other words, in many use cases, network adapter-provided computation is either too rigid or not usable. Softwares such as firewalls and networking telemetry are mainly running in CPU with processed data streams. CPU cores are still the primary computing resources used by many of our customers' software applications. More discussions can be found in Section 2.3.3New Proposal ModelMultiple independent hash computations require different seeds to be the inputs to each computation. With different seeds, the same hashing function could generate independent (randomized) results. The seeds can be random numbers to get a good mixture to result in a hash digest with good randomness. Figure 3 shows a sketch using various seeds but the same hash function to generate independent hash values.Figure 3. Example Sketch algorithm with different seeds for hash functionsOur proposed approach follows data-level-parallelism by taking multiple seeds as input, and calculating multiple hashes in parallel. The implementation is based on xxHash5, which is a fast and popular non-cryptographic hash algorithm. Other algorithms can be easily adapted to our model as well for even better throughput. Our key innovations can be summarized as the following.3.3.1Parallel Hash Computation with Splitting Input and Vectorized Seeds by Leveraging Intel® AVX-512To calculate eight independent hash values, we use eight random seeds, then continuously split the input data stream (for example, an input key) into 64-bit width data chunks and then get consumed one by one. To fully take advantage of Intel AVX-512 ISA, the data chunk size multiplies the seed count should be equal to 512. For example, if the seed count is four, then the data stream should be divided into 128-bit chunks. The process is roughly illustrated in Figure 4.Figure 4. Ultra parallelized multi-hash computation workflowWe have pre-defined five different prime numbers (P1 to P5) and eight different seeds to be used during the computation. The five prime numbers are getting involved in the hash computation later to target a good mixture of hash results. Each prime number is broadcasted into the vector of eight items. The eight different seeds are also put into a 512-bit wide vector register. The algorithm also broadcasts the truncated 64-bit-wide input data into the 512-bit-wide vector with eight copies. Then it mixes the 8-seed vector and the pre-defined five prime numbers by using addition, multiplication, rotation, shift, and xor arithmetic operations in a vectorized style.The whole process can be broken into the following steps:1.Initially, the seed vector and the P5 vector are added, and then adds the vectorized stream length in byte count. Then ittemporarily stored the result in vector m. as shown in Figure 5.5https:///Figure 5. Parallelized initializing the multi-hash computation2.Read the input data stream (for example, an input key) by 8-byte-stepping iteratively; then broadcast to an Intel AVX-512 vector register and execute the vectorized multiplication and rotation operations with input data vector and P2;then take XOR operation with the step1's result vector m to generate the intermediate result vector m'; then execute a vectorized left-rotation. After that, multiply with vector P1; then take addition with vector P4 to generate the vector m".If the input data stream length is larger than 8 bytes(64-bit), the generated vector m" will be taken to participate in the new round computation with the next 64b length of input data. Until there are no more chunks of 8-byte-block of the input data left, the arithmetic of the vectorized 8-byte-block data input will be finished. This step is shown in Figure 6.Figure 6. Continuously processing the input data as 8-byte-block3.As there might be less than eight bytes of input data left that needs to be processed after the previous 8-byte-steppingcalculation, it might need to cope with the remaining input data. The process is similar to the previous step 2, withvectorized processing of the remaining input data by leveraging add/multiply/rotate/shift/xor arithmetic operations.Finally, after consuming all input data, apply the last avalanche operation to the previous intermediate result to get the final vector digest d of all eight seeds. The full process is shown in Figure 7.Figure 7. Processing the remaining input data less than 8 Bytes3.3.2Accelerate Multiplication and Addition Operations by Leveraging Intel AVX-512 IFMA Instruction in HashComputationIntel AVX-512 IFMA instruction is introduced in 8th Gen Intel® Core™ i3 Processors and 3rd Gen Intel® Xeon® Scalable Processors, which can support fused multiply and add operation of integers belonging to Intel AVX-512 instruction sets. Since MAD (Multiply-Add-Divide) operation is essential in many hash functions to spread out the keys into the hash buckets, the vectorized Intel AVX-512 IFMA instruction will speed up the process of multiplication and addition operations. Replacing the vectorized multiplication and addition described in the above section with Intel AVX-512 IFMA instruction can accelerate the computation.3.3.3Accelerate Sketch Counter Updates by Leveraging Intel AVX-512 Gather and Scatter InstructionsSketch-based algorithms require a counter-update after the proposed hashing computation. Instead of sequentially updating the sketch counter arrays one by one, the Intel AVX-512 gather and scatter instructions can be used as the multiple hash digests are already generated in the previous vectorized hash computation. By using Intel AVX-512 gather and scatter instructions, thesketch counter array can be updated in parallel.4Performance Benchmarking4.1Benchmarking PlatformAs Intel AVX-512 instructions consume wider data per instruction and use more power, in some Intel processors, the CPU frequency may be lower when Intel AVX-512 instructions are executed. As the potential frequency reduction when using Intel AVX-512 is reduced in more recent Intel Xeon Scalable processor families, we use the 4th Gen Intel® Xeon® Scalable processor as the performance benchmarking platform. Table 3 describes the performance benchmarking platform details6.Table 3. Performance Benchmark Platform ConfigurationArchitecture x86_64CPU Model Intel® Xeon® Gold 6454S CPU# Socket(s) 2# NUMA node(s) 2Core(s) per socket 32BIOS version EGSDREL1.SYS.0091.D05.2210161328Microcode 0x2b000181SpeedStep, TurboBoost DisabledCore Frequency 2.2 GHzOS Ubuntu 22.04 (Jammy Jellyfish)Kernel 5.15.0DPDK Version V23.07Compiler GCC 11.3.0Grub Cmdline hugepagesz=1G hugepages=40 default_hugepagesz=1G isolcpus=1-15,65-79,33-47,97-111 intel_iommu=on iommu=pt nohz_full=1-15,65-79,33-47,97-111 rcu_nocbs=1-15,65-79,33-47,97-111 nmi_watchdog=0 audit=0 nosoftlockup processor.max_cstate=0intel_idle.max_cstate=0 hpet=disable mce=off tsc=reliable numa_balancing=disable intel_pstate=disableTest Command # DPDK_TEST=member_perf_autotest ./build/app/test/dpdk-test -l 6 --force-max-simd-bitwidth=512 --no-pci4.2Benchmarking ResultsThe optimal implementation solution based on the Count-Min Sketch algorithm is upstreamed on DPDK 22.11 release. The key size for the performance benchmarking is in the range of 4, 8, 9, 13, 16, 32, 37, 40, 48, and 64 bytes, which are the typical key size of the representative value of a data stream when using a sketch-based algorithm. As the performance benchmarking comparison reference, the CRC hash implementation, which is accelerated by CRC-32 instruction, is selected. As the CRC instruction hash implementation is proved as a high-performance hash function and the seed number is eight, in other words, it can be considered as eight hash functions. The test data set consists of 10 M packets of each key size in the above key size range. As the Add and Lookup operations are the most common operations in such sketch-based algorithms, both of the operations will invoke the multiple hash computation as the basic step. Here, the performance benchmarking comparison of Add and Lookup operations are illustrated in Figure 8 and Figure 9. It shows that the accelerated solution achieves an average 2.7x performance gain on the Add operation and 2.4x on the Lookup operation. Concerning the hash-collision ratio, it depends on the underlying hash algorithm. Taking our implementation underlying hash algorithm, xxHash64, for example, the collision test result looks good7.6 Performance varies by use, configuration and other factors. Learn more at /PerformanceIndex.7https:///Cyan4973/xxHash/wiki/Collision-ratio-comparison#testing-64-bit-hashes-on-large-inputs-Figure 8. Performance benchmarking on Sketch Add compared with CRC-32 instructionFigure 9. Performance benchmarking on Sketch Lookup compared with CRC-32 instruction5SummaryThis technology guide demonstrates a brand new ultra-parallelized multi-hash computation model for data streaming workloads. The model offers several advantages, which have been detailed through the recently unveiled technique:1.High-performance: This technology guide proposes a novel model by leveraging Intel AVX-512 instruction sets toget data-level parallelism when processing multi-hash computations. Based on xxHash, we achieve a performancegain of up to 2x on key-add and key-lookup operations compared to the standard CRC-32 instruction.2.Flexibility: Although the algorithm implementation is evaluated based on xxHash, other simpler hashing algorithmscan also be used with this model to gain even more performance, given the flexibility of the model.3.Scalability: The model can be scaled to support keys of various lengths and various numbers of hashes as required,based on the level of parallelism supported by Intel AVX-512 instructions.Technology Guide | Intel® AVX-512 - Ultra Parallelized Multi-hash Computation for Data Streaming Workloads11Performance varies by use, configuration and other factors. Learn more at /PerformanceIndex .Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure.Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.Intel technologies may require enabled hardware, software or service activation.Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy.Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not "commercial" names and not intended to function as trademarks.The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.© Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.0823/DN/WIT/PDF785248 -001US。

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High-Performance,Parallel,Stack-Based Genetic Programmingby Kilian Stoffel and Lee SpectorFull citation:Stoffel,K.,and L.Spector.1996.High-Performance,Parallel,Stack-Based Genetic Programming.In Koza,John R.,Goldberg,David E.,Fogel,David B., and Riolo,Rick L.(editors)Genetic Programming1996:Proceedings ofthe First Annual Conference,224-229.Cambridge,MA:The MIT Press.High-Performance,Parallel,Stack-Based Genetic ProgrammingKilian Stoffel*stoffel@*Department of Computer Science University of MarylandCollege Park,MD20742Lee Spector*lspector@School of Cognitive Science and Cultural StudiesHampshire CollegeAmherst,MA01002ABSTRACTHiGP is a new high-performance genetic pro-gramming system.This system combines tech-niques from string-based genetic algorithms,S-expression-based genetic programming systems,and high-performance parallel computing.Theresult is a fast,flexible,and easily portable geneticprogramming engine with a clear and efficientparallel implementation.HiGP manipulates andproduces linear programs for a stack-based vir-tual machine,rather than the tree-structured S-expressions used in traditional genetic program-ming.In this paper we describe the HiGP virtualmachine and genetic programming algorithms.We demonstrate the system’s performance on asymbolic regression problem and show that HiGPcan solve this problem with substantially less com-putational effort than can a traditional geneticprogramming system.We also show that HiGP’stime performance is significantly better than thatof a well-written S-expression-based system,alsowritten in C.We further show that our parallelversion of HiGP achieves a speedup that is nearlylinear in the number of processors,without man-dating the use of localized breeding strategies.1Performance of GeneticProgramming SystemsGenetic programming is a technique for the automatic gen-eration of computer programs by means of natural selection [Koza1992].The genetic programming process starts by creating a large initial population of programs that are ran-dom combinations of elements from problem-specific func-tion and terminal sets.Each program in the initial population is then assessed forfitness,and thefitness values are used in producing the next generation of programs via a variety of genetic operations including reproduction,crossover,and mutation.After a preestablished number of generations,or after thefitness improves to some preestablished level,the best-of-run individual is designated as the result and is pro-duced as the output from the genetic programming system. The performance impact of alternative approaches to ge-netic programming can only be assessed by measuring per-formance over a large number of runs.This is because the algorithm includes random choices at several steps;in any particular run the effects of the random choices may easily obscure the effects of the alternative approaches.To analyze the performance of a genetic programming system over a large number of runs one canfirst calculate P(M,i),the cumulative probability of success by generation i using a population of size M.For each generation i this is simply the total number of runs that succeeded on or before the i th generation,divided by the total number of runs con-ducted.Given P(M,i)one can calculate I(M,i,z),the number of individuals that must be processed to produce a solution by generation i with probability greater than z.I(M,i,z)can be calculated using the following formula:For the analyses in this paper a value of z=99%is always used.The P(M,i)and I(M,i,z)measures were developed by Koza and are dis-cussed on pages99through103of[Koza1994].particularly strong interest in parallelizing genetic program-ming systems.Most previous high performance genetic programming systems have either been wedded to particular computer ar-chitectures,or have been hampered by high overheads in distributingfitness evaluation and in coordinating reproduc-tion across parallel machines.For example,Koza and Andre have implemented an S-expression-based genetic program-ming system on a network of transputers and have achieved considerable speed improvements over serial implementa-tions[Koza and Andre1995].Their approach relies on a hardware base that is less expensive than parallel supercom-puters but is nonetheless somewhat exotic.They used lo-cal breeding strategies with migration;they report that this reduces computational effort as compared with a panmic-tic(globally interbreeding)population on the problems they tried.Others have reported similar improvements from the use of localized breeding strategies,both in genetic program-ming and in string-based genetic algorithms(e.g.,[Collins and Jefferson1991]).It is not yet clear,however,that par-ticular localized breeding strategies are always beneficial, and it is important that high-performance genetic program-ming systems not be swamped with communication over-heads when less localized or global(panmictic)strategies are used.Nordin and Banzhaf have developed a“compiling”ge-netic programming system that directly manipulates SPARC machine code[Nordin and Banzhaf1995].Through a com-bination of compactfixed-length representations,simplified memory management,and non-interpreted program execu-tion they have achieved dramatic speed improvements over traditional genetic programming systems.Their system de-pends on details of the SPARC architecture and would re-quire significant redesign for other machines.Juill´e and Pollack have developed a SIMD(single in-struction multiple data)parallel genetic programming sys-tem that represents programs as S-expressions but“precom-piles”them into programs for a virtual stack machine prior to execution[Juill´e and Pollack1995].They note that the variation in S-expression sizes across the population can in-troduce overhead,and they use local breeding strategies to reduce interprocessor communication costs.S-expression-based program representations are respon-sible for several of the performance limitations of previous systems.These representations make strong demands on a system’s memory allocation subsystems and they are expen-sive to manipulate and to move between processors.In addi-tion,less prior research has been conducted on the optimiza-tion and parallelization of S-expression interpreters than on techniques for more common models of computation. These limitations of previous systems lead us to consider the idea of genetic programming with small,linear programs that can be executed on stack-based virtual machines for which portable,high performance interpretation techniques have already been developed.We were encouraged by pre-vious work that explored the performance benefits of lin-ear program representations(e.g.,[Keith and Martin1994]). We were further encouraged by Perkis’s work on stack-based genetic programming[Perkis1994],in which he used lin-ear programs that were executed on a stack-based virtual machine.In contrast to the work of Keith and Martin and of Juill´e and Pollack,Perkis performed string-based genetic operations(e.g.string-based crossover)directly on the lin-ear programs.The safety of the resulting programs was guaranteed by specifying that all functions take their argu-ments from the stack,and that function calls that occur with too few items on the stack simply do ing this scheme,Perkis reported lower computational efforts than were required using traditional S-expression-based genetic programming.In HiGP we have combined elements of the stack-based program frameworks of Perkis and of Juill´e and Pollack,the linear chromosomes of string-based genetic algorithms(also used in Nordin and Banzhaf’s and Perkis’s systems),the ef-ficient,low level execution model of Nordin and Banzhaf, a machine independent virtual stack machine,and high-performance parallel programming techniques.3The HiGP Virtual Stack Machine HiGP programs are executed on a virtual machine that is sim-ilar to a pushdown automaton.The virtual machine consists of three components:an input tape containing a linear pro-gram,a pushdown stack,and afinite-state control unit.The contents of the input tape are restricted to a small set of words that have been defined as HiGP operators.The contents of pushdown stack are restricted to double precisionfloating point numbers.Thefinite-state control unit reads the input tape and executes,for each word,the function call for the corresponding operator.The operators may perform arbi-trary computations and manipulate the values on the stack. They may also reposition the read head on the input tape;this allows for the implementation of conditionals and loop struc-tures.Return values are generally read from the top of the stack at the end of program execution.The system includes two basic stack operators,pop and dup.The pop operator removes the topmost element from the stack,while the dup operator pushes a duplicate of the top element onto the stack.The system also includes a fam-ily of push operators that correspond to the terminal set in a traditional genetic programming system;each push oper-ator pushes a single pre-determined value onto the stack. The system also includes a noop operator that does noth-ing.This is necessary because all programs in the system have the same length,and because we do not wish to pre-determine the number of actual problem-solving operators that should appear in solution programs.With the inclusion of the noop operator thefixed program size becomes a sizeinput tape (instructions)value stack Figure1:The virtual stack machinelimit,analogous to the depth limits used in S-expression-based genetic programming systems.“Shorter”programs are encoded byfilling in extra program steps with noop s. Note that this provides the sameflexibility with respect to program size as do S-expression-based genetic programming systems.If one suspects that a large program may be re-quired,then one can set the program size to an arbitrarily large number.In such a case,however,the system may still produce efficient,parsimonious programs;it may do so by producing programs that consist mostly of noop s.Any additional,problem-specific operators must take their input values from the stack and must push their results back onto the stack.When there are not enough values on the stack for an operator it is skipped by thefinite-control unit and the stack remains untouched(as in[Perkis1994]).A simple example may help to clarify the operation of the virtual stack machine.Consider the following program:push-x noop push-y*push-x push-z noop -+noop noopThe noop s in this program have no effect and the remain-der is equivalent to the Lisp expression:(+(*x y)(-x z))and to the C expression:(x*y)+(x-z)For the test examples presented in this paper we used only the four basic arithmetic operators:+(addition),-(subtraction),*(multiplication)and%(protected division [Koza1992]).Although conditionals,loops,and other con-trol structures were not used for the examples in this paper, several have been implemented for HiGP.For example,one implemented control structure reads a value from the stack and executes the next instruction if the value,when trun-cated,is zero;otherwise it jumps over the next instruction.Another control structure jumps over a number of instruc-tions;the number is obtained by truncating the value on the top of the stack.These control structures,along with sev-eral other features of our virtual stack machine,are similar to those of the FORTH programming language[Brodie1981]. The extension of the virtual stack machine with additional operators and control structures is trivial;the FORTH lan-guage provides examples of what such extensions might look like.4Genetic Programming in HiGPOne nice feature of the HiGP program representation is that one can use the same genetic operators that are used in string-based genetic algorithms.Each gene in the chromosome rep-resents an operator for the virtual machine.Since the oper-ators communicate with one another only by means of the stack,and since stack-underflow is handled gracefully(by ignoring offending operators),every possible ordering of op-erators represents a syntactically correct program.Arbitrary string-based manipulations of the chromosomes are there-fore acceptable.In fact,it would be possible to use many existing,off-the-shelf genetic algorithm packages to perform the genetic operations on HiGP programs.In the current im-plementation we use three standard genetic operators:re-production,single-point crossover,and point mutation.The population is initialized by setting each gene in each chro-mosome to a random member of the operator set.An additional consideration for genetic programming is the implementation of ephemeral random constants[Koza 1992].In HiGP constants are not included directly in pro-grams(chromosomes)because a small,fixed gene size is im-portant for optimized,high-performance execution and ma-nipulation of HiGP programs.Because some applications call for constants with representations that are larger than the optimal gene size(for example,double precisionfloating-point constants in an application with a small number of op-erators and constants)HiGP maintains a table in which con-stants are stored.Inside the programs the constants are rep-resented by their positions in the table.The“execution”of a constant causes the corresponding value from the table to be pushed onto the stack.The ephemeral random constants in the table are initialized at the beginning of a run and remain unchanged during the entire run;this differs from Koza’s im-plementation,in which new constants may be generated by the mutation operator at any point in a run.Our point mu-tation operator can transform one constant into another,or into an operator,but the set of available constants does not change during a run.The size of the constant table is lim-ited only by the size of the alphabet for the virtual stack ma-chine,which is in turn determined by the operator word-size. Because the word-size is a variable parameter in the current implementation,any number of ephemeral random constants can be supported.5Advantages of the HiGP approach HiGP has several advantages over traditional S-expression-based genetic programming systems.HiGP programs are offixed length and our experience is that they can be quite small.We have solved several problems with programs only 32operators in length,with less than a byte required for each operator.This makes it easy to optimize memory allocation, to create populations with millions of individuals,and to ef-ficiently pass programs between processors in multiproces-sor architectures.Load-balancing duringfitness evaluation is also eased by thefixed program length.These factors com-bine to allow for nearly linear speedups with added proces-sors,even when a global breeding strategy is used.Of course many problems will require longer programs,but all compo-nents of the system should scale at worst linearly with pro-gram length.In addition,the evolutionary dynamics of systems of lin-ear programs appear in some cases to be superior to those of S-expression-based genetic programming(e.g.,in[Perkis 1994]and below).We do not yet have a theoretical explana-tion of why this should be so.6Example:Symbolic RegressionThe goal of the symbolic regression problem,as described in[Koza1992],is to produce a function thatfits a provided set of data points.For each element of a set of(x,y)points, the program should return the correct y value when provided only with the x value.For our experiments we obtained our data points from the equation y=x.One can view the task of the genetic programming system as that of“rediscover-ing”this formula from the data points used asfitness cases. We used20fitness cases,with randomly selected x values between-1and1.We used a function set consisting of the two-argument ad-dition function+,the two-argument subtraction function-, the two-argument multiplication function*,and the two-argument protected division function%.We used a single “terminal”operator push-x that pushes the x value onto the stack.We did not use ephemeral random constants or any other constants.We ran HiGP with tournament selection (tournament size=5),a90%crossover rate,a10%repro-duction rate,and no mutation.We conducted100runs,each with a population size of500,and each for a maximum of30 generations.The length of each individual program was set to32operators.We also conducted100runs of the lil-gp S-expression-based genetic programming system[Zongker1995]on this problem.We used parameters that were as similar as pos-sible to those used for HiGP:function set=+,-,*, %,terminal set=X,tournament selection(size=5),90% crossover,10%reproduction,no mutation,100runs,popula-tion=500,generations=30.The depth limit presented a more difficult problem since the HiGP concept of length limit and Table1:Results for HiGP and for lil-gp using different depth limitstime/gen.0.084212,5210.18671,4810.23882,2100.281065,2160.301277,0300.361471,4810.381690,3790.41the lil-gp concept of depth limit are quite different.Low-ering the depth limit in lil-gp improves its execution speed considerably,but in some cases this may make it more diffi-cult or impossible tofind correct programs.It is not clear,in general,how the depth limit influences computational effort. For this reason we ran lil-gp with a range of depth limits.We used a depth limit of4for the low end of the range;this is the lowest limit for which lil-gp was able tofind any correct pro-grams at all.We used17for the high end of the range;this is the default for lil-gp and,according to our data,much larger than optimal.We believe that lil-gp,which is implemented in C,is a well-written program that provides a reasonable compar-ative benchmark for S-expression-based genetic program-ming.One way to establish the relative time performance of the two systems would be to compare the times that each system takes for a complete set of100runs.However,the number of generations computed by the two systems are dif-ferent,as indicated by the computational effort results re-ported below.To remove this factor from the time perfor-mance comparisons we computed the time used by each sys-tem to evaluate one generation.For HiGP the execution time per generation is nearly constant,because of thefixed length of the programs and because of the absence of conditionals or looping operators in the test problem.For lil-gp the time for the execution of one generation can change significantly as the structures of the S-expressions evolve.We therefore used the mean value over100runs for all evaluated genera-tions.Our results,obtained on a Sun SPARC5,are summarized in Table1.HiGP was clearly superior both with respect tocomputational effort and with respect to time performance. The best computational effort for lil-gp was obtained with a depth limit of10,but even this effort(65,216)was nearly double that required by HiGP(32,729).In addition,the time performance of lil-gp with a depth limit of10was quite poor; the time required per generation was0.30seconds,while HiGP required only0.08seconds per generation.The best time performance for lil-gp was obtained with a depth limit of4,but even this time(0.16seconds)was double that of HiGP(0.08seconds).In addition,the computational effort required by lil-gp with a depth limit of4was quite poor;it was212,521,which is over six times greater than the effort required by HiGP(32,729).7Parallel HiGPThe parallel version of HiGP was developed to run on MIMD (multiple instruction multiple data)supercomputers,but it was not tailored for any one particular system.We used the MPI(message passing interface)communication library, which is available for many different parallel computer sys-tems.This greatly simplifies the process of porting HiGP to various different computer systems.The system was written within the SPMD(single program multiple data)paradigm; all nodes of the parallel system execute identical programs but on different data.The population is distributed evenly across the processors, with each processor maintaining its own local copy of afit-ness table for the entire population.This allows much of the breeding process(including selection)to occur locally,along withfitness evaluation.During thefitness evaluation phase,all processors evalu-ate thefitness of their individuals in parallel.Because each processor hosts the same number of programs,and because all of the evolving programs are the same length,all of the processors completefitness evaluation at nearly the same time.Load balancing may be more complicated for applica-tions with function sets that include functions of widely vary-ing runtimes,and for applications that include conditional and looping operators in their function sets.At the end of thefitness evaluation phase all computedfitness values are exchanged between processors and allfitness tables are up-dated.During the breeding phase each processor independently produces its own segment of the next generation.The choice of which genetic operators to apply is determined locally,us-ing the percentages specified for the whole population.For example,if it has been specified that60%of the next gen-eration should be produced by crossover,30%by reproduc-tion,and10%by mutation,each processor can choose oper-ators according to these percentages locally and the correct global percentages will result.Selection is also performed locally,using the localfitness tables to perform eitherfitness-proportionate or tournament selection.Interprocessor com-munication is only required to exchange the actual individu-als that have been selected for use in genetic operations(and then only when they are not local).Notice that the breeding strategy is global(panmictic) even though selection occurs locally on individual proces-sors.The need for interprocessor communication is mini-mized,and there are low communication overheads both for the distribution offitness values and for the transportation of the small linear programs.Notice also that it would be triv-ial to modify HiGP to make use of localized breeding strate-gies;although little would be saved with respect to commu-nication costs,improvements in computational effort might result for certain problems.time91.4147.1227.3216.8210.898163264128124816[secs][number of nodes]execution timeFigure2:Parallel execution times for one run on up to 16processors on an IBM SP2.The HiGP strategy leads to a very efficient implementa-tion,as Figure2shows.We were able to execute a pro-gram which took seconds on one single node of the IBM SP2nearly times faster on nodes in seconds. This leads to an efficiency(number of times faster divided by number of nodes)of more than,which is good for a communication-intensive program.Note also that the graph in Figure2is nearly linear.8ConclusionsHiGP is a new high-performance genetic programming sys-tem that combines techniques from string-based genetic algorithms,S-expression-based genetic programming sys-tems,and high-performance parallel computing.HiGP is fast,flexible,and easily portable.It also has a clear and effi-cient parallel implementation that is not tied to any particularparallel computer architecture.HiGP manipulates and produces linear programs for a stack-based virtual machine,rather than the tree-structured S-expressions used in traditional genetic programming.This appears to have several benefits;along with the optimiza-tions that it allows for memory management and paralleliza-tion,it appears to decrease the computational effort required to produce a correct program,at least for the regression prob-lem that we presented.We showed that HiGP’s time performance is significantly better than that of lil-gp,a well-written S-expression-based system which is also written in C.We further showed that our parallel version of HiGP achieves a speedup that is nearly linear in the number of processors,without mandating the use of localized breeding strategies. AcknowledgmentsThe research described in this paper was supported in part by grants from ONR(N00014-J-91-1451),AFOSR(F49620-93-1-0065),and ARPA contract DAST-95-C0037. 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