MAX10 FPGA器件概述
FPGA概述PPT课件
6.底层内嵌功能单元 内嵌专用硬核是相对于底层嵌入的软核而言 的，硬核（Hard Core）使FPGA具有强大 的处理能力，等效于ASIC电路。
•12
1.3 IP核简介
IP（Intelligent Property）核
是具有知识产权的集成电路芯核总称，是 经过反复验证过的、具有特定功能的宏模 块，与芯片制造工艺无关，可以移植到不 同的半导体工艺中。
通道绑定原 理示意图
•28
5.预加重技术 在印制的电路板上，线路是呈现低通滤波 器的频率特性的，为解决高频部分的损失， 就要采取预加重技术。
预加重技术的思想是：在传输信号时，抬高 信号的高频信号，以补偿线路上高频分量的 损失。
•29
没有预加重 的发送波形
•30
预加重后的 发送波形
没有预加重 的接收波形
典型的IOB内部结构示意图
2.可配置逻辑块(CLB)
CLB是FPGA内的基本逻辑单元 .
CLB的实际数量和特性会依据器件的不同而不同，但是每 个CLB都包含一个可配置开关矩阵，此矩阵由选型电路(多 路复用器等)、触发器和4或6个输入组成。
典型的CLB结 构示意图
3. 数字时钟管理模块（DCM）
目前FPGA中多使用4输入的LUT，所以每一 个LUT可以看成是一个有4位地址线的RAM。当用 户通过原理图或HDL语言描述一个逻辑电路以后， PLD/FPGA开发软件会自动计算逻辑电路的所有可 能结果，并把真值表(即结果)写入RAM，这样，每 输入一个信号进行逻辑运算就等于输入一个地址去 进行查表，找出地址对应的内容，然后输出即可。
DLL简单模 型示意图
Xilinx DLL的典 型模型示意图
在FPGA设计中，消除时钟的传输延迟，实现高扇出 最简单的方法就是用DLL，把CLK0与CLKFB相连 即可。 利用一个DLL可以 实现2倍频输出
FPGA可编程逻辑器件芯片10M04DCU324C7G中文规格书
Multi-Point SupportSet only the speed for endpoint 0 because endpoint 0 only has the facilities to handle control transactions and there-fore is always associated with a device endpoint 0. Use bits 7–6 of the Type 0 register to set the speed. The register is located at address 0x1A when the index register is set to 0.Multi-Point OperationAfter allocating functions to endpoints and recording the operating speed of the target device, multi-point opera-tions can be configured. Most operations in a multi-point set-up are the same as for the equivalent actions where the core is attached to a single other device.However, more steps are required when:•The option of dynamically switching the allocation of functions to endpoints is taken (for example, to allow the support of a wider range of devices).•The control packets normally associated with endpoint 0 are handled through a different endpoint.If dynamic allocation is used, the program must monitor the current data toggle state associated with the endpoint and with each of the devices that are allocated to that endpoint. This knowledge allows the program to select the correct data toggle state when switching occurs between one device and the other. (This action is the programs re-sponsibility. The core cannot determine what data toggle state is expected when a function switches in and out of use.)The data toggle state can be switched from its current state by writing to the appropriate USB_EP[n]_TXCSR_H or USB_EP[n]_RXCSR_H register. This activity sets the data toggle write enable and data toggle bits that are included in the registers when the core is in host mode.Data toggle write enable and data toggle bits are also included in the USB_EP0_CSR[n]_H register. However, con-trol operations carried out through endpoint 0 of the core normally leave the data toggle in the expected state. Where control packets are handled through an endpoint other than endpoint 0, programs must prompt for each setup token to be sent. Programs must set the USB_EP[n]_TXCSR_H.SETUPPKT bit when the core operates in host mode, along with the USB_EP[n]_TXCSR_H.TXPKTRDY bit. If the USB_EP[n]_TXCSR_H.SETUPPKT bit is not set, an OUT token is sent.Use endpoint 0 of the USB controller to handle control packets for all of the devices attached to the controller, and to switch the allocation of this endpoint, as appropriate. Sending the correct token is ensured, as is ensuring that the data toggle is correctly set for this endpoint.Using a different endpoint for this function is possible, as described, but note the following:•The control function must be allocated to an Rx/Tx endpoint pair (with the same endpoint number).•The chosen endpoints must each be associated with FIFOs that can accommodate the packet size associated with EP0 transactions at the chosen operating speed. The size is a minimum of 8 bytes for low-speed or full-speed transactions but 64 bytes for high-speed transactions.Suspending and Resuming the ControllerSuspend or Resume by Inactivity on the USB Bus (L0 to L2 State) in Peripheral ModeThe following steps occur in this mode.1.Entry into suspend mode. When operating as a peripheral, the USB controller monitors activity on the USBand when no activity has occurred for 3 ms, the controller goes into suspend mode. If the USB_IRQ.SUSPEND interrupt has been enabled, the USB controller now generates an interrupt. The USB_IRQ.SUSPEND output also goes low (if enabled).The POWERDWN signal is also asserted to indicate that the application can stop USB_CLKIN to save power.POWERDWN then remains asserted until either power is removed from the bus (indicating that the device has been disconnected) or resume signaling or reset signaling is detected on the bus.2.When resume signaling occurs on the bus, the USB_CLKIN must be restarted, if necessary. The USB controllerthen automatically exits suspend mode. If the USB_IRQ.RESUME interrupt is enabled, the USB controller gen-erates an interrupt.3.Initiating a remote wake-up. T o initiate a remote wake-up while the controller is in suspend mode, set theUSB_POWER.RESUME bit=1. ( If USB_CLKIN has been stopped, it must be restarted before this write can oc-cur.) The software must leave then this bit set for approximately 10 ms (minimum of 2 ms, a maximum of 15 ms) before resetting it to 0. By this time the hub is driving resume signaling on the USB.NOTE:The USB_IRQ.RESUME interrupt is not generated when the software initiates a remote wake-up. Suspend or Resume by Inactivity on the USB Bus (L0 To L2 State) in Host Mode The following steps occur in this mode.1.Entry into suspend mode. When operating as a host, the USB controller can be prompted to go into suspendmode by setting the USB_POWER.SUSPEND bit. When this bit is set, the USB controller completes the current transaction then stops the transaction scheduler and frame counter. No further transactions start and no SOF packets are generated. If the USB_POWER.SUSEN bit is set, the UTMI+ PHY goes into low-power mode when the controller goes into suspend mode and stops USB_CLKIN.2.Sending resume signaling. When the application requires the controller to leave suspend mode, it clears theUSB_POWER.SUSPEND bit, sets the USB_POWER.RESUME bit, and leaves it set for 20 ms. While theUSB_POWER.RESUME bit is high, the controller generates resume signaling on the bus. After 20 ms, the pro-cessor core must clear the USB_POWER.RESUME bit, at which point the frame counter and transaction schedu-ler start.3.Responding to remote wake-up. If resume signaling is detected from the target while the USB controller is insuspend mode, the UTMI+ PHY is brought out of low-power mode and restarts USB_CLKIN. The controller then exits suspend mode and automatically sets the USB_POWER.RESUME bit to 1 to take over generating the resume signaling from the target. If the USB_IRQ.RESUME interrupt is enabled, the USB controller generates an interrupt.USB Event Control•When SRP signaling is detected (A device only)•When device disconnect is detected (host mode)•When a session ends (peripheral mode)•When a device connection is detected (host mode)•At start of frame (SOF)•When reset signaling is detected on USB (peripheral mode)•When babble is detected (host mode)•In suspend mode, when resume signaling is detected on USB•When suspend signaling is detected (peripheral mode)The software generates interrupts for the following VBUS control requests:•Drive VBUS greater than 4.4 V (default A device)•Stop driving VBUS•Start charging VBUS (peripheral mode)•Stop charging VBUS•Start discharging VBUS (peripheral mode)•Stop discharging VBUSInterrupt HandlingWhen interrupted with a USB interrupt, the processor core must read the interrupt status register to determine which endpoints have caused the interrupt and jump to the appropriate routine. If multiple endpoints have caused the interrupt, endpoint 0 must be serviced first, followed by the other endpoints. The USB Interrupt Service Rou-tine figure shows a flowchart for the USB interrupt service routine.。
MAX10设计指南
M10-GUIDELINES
该应用笔记提供了一组清单列表，它包括使用 MAX®10 FPGA 创建设计时需要考虑的设计 指南，建议和因素。
■
使用该文件可以帮助您在设计的初期规划 FPGA 和系统，这对于成功完成设计是至关 重要的。 在整个设计过程中遵循 Altera 的建议，可以使您获得最佳效果、避免出现常见问题 以及提高设计生产效率。
■
图 1 显示了 MAX10 设计流程。该文档中的这一部分对设计流程的每个部分提供清单列 表和设计指南。
图 1. MAX10 设计流程
Board Design
Power Pins Planning Specifications Design Specifications • IP Selection Early Planning Early Board Design Planning Early Pin Planning and I/O Assignment Hierarchical Team-based Design Planning Clock Planning Formal Verification I/O SSN Considerations Power Analysis and Optimization Configuration Pins Planning Design Entry Design Implementation Synthesis and Compilation Timing Optimization and Analysis Functional Timing Simulation
3.
查看可用的设计工具
考虑可用的设计、估计器、系统建立程序和验证工具。以下项目是 Altera 提供 的一些可用工具：
Altera MAX_10_双映像配置方法
Altera MAX_10_双映像配置方法发布时间：2015-03-03在上篇“Altera MAX_10_单映像配置方法”中介绍了MAX 10 FPGA的内部配置，并且对单映像配置过程做了演示，此篇继续配置这个主题，介绍双映像配置过程：工程继续使用LED_FLASH，上篇中新建了LED_BREATH版本，工程有两个版本：LED_Flash 和LED_BREATH▼▼制作双配置映像，需要相应地在设置中奖内部配置模式设置Dual Compressed Image▼然后开始编译，但是出现了错误Error (169130): Configuration mode specified as Remote but remote update block is not found in design，是缺少了什么模块查阅相关文档，原来是缺少这货：Altera Dual Boot IP，必须在工程中例化这个IP才能实现双映像配置。
由于此IP接口是Avalon-MM的，需要先在Qsys中包装一下▼▼在IP Catalog中搜索Dual Boot IP，然后点击添加▼只需配置此IP的时钟，此例中为50MHz▼将clk和reset连接后，一个基于Dual Boot IP的简单Qsys系统完成了▼点击Generate HDL…，在弹出对话框中设置后，点击Generate▼系统生成后，在顶层Verilog代码中例化生成的Qsys系统dualboot dualboot_u(.clk_clk(clk), // clk.clk.reset_reset_n(1'b0) // reset.reset_n );▼成功编译后，可在层次结构中看到dualboot系统模块▼切换另一个版本，记得内部配置模式也设置成Dual Compressed Image，不同的版本其设置是独立的，然后重新编译；两个版本分别生成两个sof文件：LED_Flash.sof和LED_BREATH.sof。
MAX10 FPGA器件体系结构
MAX 10 FPGA器件体系结构MAX 10器件包含下面组件：•逻辑阵列模块(LAB)•模数转换器 (ADC)•用户闪存(UFM)•嵌入式乘法器模块•嵌入式存储器模块 (M9K)•时钟和锁相环 (PLL)•通用I/O•高速LVDS I/O•外部存储器接口•配置闪存 (CFM)© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.ISO 9001:2008 Registered101 Innovation Drive, San Jose, CA 95134图1: MAX 10器件的典型的器件平面规划•每个模块的数量和位置根据每个MAX 10器件的不同而有所不同。
MAX10FPGA配置用户指南.pdf
MAX 10 FPGA配置用户指南订阅UG-M10CONFIG | 2017.07.20内容内容1 MAX® 10 FPGA配置概述 (4)2 MAX 10 FPGA配置方案和功能 (5)2.1 配置方案 (5)2.1.1 JTAG配置 (5)2.1.2 内部配置 (6)2.2 配置功能 (12)2.2.1 远程系统更新 (12)2.2.2 配置设计安全 (18)2.2.3 SEU缓解与配置错误检测 (21)2.2.4 配置数据压缩 (25)2.3 配置详细信息 (26)2.3.1 配置序列 (26)2.3.2 MAX 10配置管脚 (29)3 MAX 10 FPGA配置设计指南 (30)3.1 双用配置管脚 (30)3.1.1 指南：复用配置管脚 (30)3.1.2 使能双用管脚 (31)3.2 使用JTAG对MAX 10器件进行配置 (31)3.2.1 JTAG配置设置 (32)3.2.2 JTAG配置中的ICB设置 (33)3.3 使用内部配置对MAX 10器件进行配置 (34)3.3.1 选择内部配置模式 (34)3.3.2 .pof和ICB设置 (34)3.3.3 将.pof文件编程到内部闪存 (36)3.4 在 Intel Quartus Prime软件中实现ISP钳位 (37)3.4.1 创建IPS文件 (37)3.4.2 执行IPS文件 (37)3.5 通过用户逻辑访问远程系统更新 (37)3.6 错误检测 (38)3.6.1 验证错误检测功能 (38)3.6.2 使能错误检测 (39)3.6.3 通过用户逻辑访问错误检测模块 (40)3.7 使能数据压缩 (41)3.7.1 使能设计编译前的压缩 (41)3.7.2 使能设计编译后的压缩 (42)3.8 AES加密 (42)3.8.1 生成.ekp文件和加密配置文件 (42)3.8.2 从.ekp文件生成.jam/.jbc/.svf文件 (44)3.8.3 编程.ekp文件和加密的POF文件 (44)3.8.4 内部配置中的加密 (45)3.9 MAX 10 JTAG安全设计实例 (47)3.9.1 内部JTAG接口 (48)3.9.2 内部JTAG模块访问的WYSIWYG Atom (48)内容3.9.3 执行LOCK和UNLOCK JTAG指令 (50)3.9.4 验证JTAG安全模式 (51)4 MAX 10 FPGA配置IP内核实现指南 (52)4.1 Altera Unique Chip ID IP内核 (52)4.1.1 例化Altera Unique Chip ID IP内核 (52)4.1.2 复位Altera Unique Chip ID IP内核 (52)4.2 Altera双配置IP内核 (53)4.2.1 例化Altera双配置IP内核 (53)5 Altera双配置IP内核参考 (54)5.1 Altera双配置IP内核Avalon-MM地址映射 (54)5.2 Altera双配置IP内核参数 (55)6 Altera Unique Chip ID IP内核参考 (56)6.1 Altera Unique Chip ID IP内核端口 (56)A MAX 10 FPGA配置用户指南的附加信息 (57)A.1 MAX 10 FPGA配置用户指南的文档修订历史 (57)1 MAX® 10 FPGA配置概述您可以使用下面的配置方案对MAX® 10配置RAM (CRAM)进行配置:•JTAG 配置—使用JTAG接口。
alteramax10fpga
Altera MAX10 FPGA
今天收到了友晶的NEEK开发套件，感谢爱板网的厚爱再一次给我评测FPGA开发板的机会，快递小哥也很热情，老规矩先秀秀开箱图。
用过友晶开发板应该不陌生这个风格的包装盒。
迫不及待插上了电源准备上电启动默认的程序
以前用过的友晶的开发板1993 年推出的Altera MAX? CPLD 系列广受赞誉，该系列提供了有史以来功耗最低、成本最低的CPLD 。
新推出的MAX 10 FPGA 作为非易失的可编程逻辑器件，代表着一个在FPGA 性能及集成上的重大飞跃。
MAX 系列Mature CPLD FamiliesMAX II
CPLDMAX IIZ
CPLDMAX V
CPLDMAX 10 FPGA推出年份1995 - 20022004200720102014工艺技术0.50-0.30 μm180
nm180 nm180 nm55 nm关键特性5.0 V I/OsHigh I/O
countLow static powerLow cost and powerNon-volatile integration。
MAX 10嵌入式存储器用户指南说明书
MAX 10嵌入式存储器用户指南订阅反馈UG-M10MEMORY2015.11.02101 Innovation Drive San Jose, CA 内容MAX® 10嵌入式存储器概述..............................................................................1-1 MAX 10嵌入式存储器体系结构和功能............................................................2-1 MAX 10嵌入式存储器一般特性............................................................................................................2-1控制信号...........................................................................................................................................2-1奇偶校验位......................................................................................................................................2-2读使能...............................................................................................................................................2-2Read-During-Write..........................................................................................................................2-3字节使能...........................................................................................................................................2-3Packed模式支持.............................................................................................................................2-4地址时钟使能支持.........................................................................................................................2-5异步清零...........................................................................................................................................2-6 MAX 10嵌入式存储器操作模式............................................................................................................2-7支持的存储器操作模式.................................................................................................................2-8 MAX 10嵌入式存储器时钟模式............................................................................................................2-9时钟模式中的异步清零..............................................................................................................2-10同时的读和写中的输出读数据.................................................................................................2-10时钟模式的独立时钟使能..........................................................................................................2-10 MAX 10嵌入式存储器配置...................................................................................................................2-11端口宽度配置................................................................................................................................2-11双端口模式的存储器配置..........................................................................................................2-11最大模块深度配置.......................................................................................................................2-12 MAX 10嵌入式存储器设计考量........................................................................3-1实现外部冲突解决.....................................................................................................................................3-1定制Read-During-Write行为..................................................................................................................3-1相同端口Read-During-Write模式.............................................................................................3-2混合端口Read-During-Write模式.............................................................................................3-3考虑上电状态和存储器初始化...............................................................................................................3-4控制时钟以降低功耗.................................................................................................................................3-5选择Read-During-Write输出..................................................................................................................3-6 RAM：1-Port IP内核参考.................................................................................4-1 RAM：MAX 10器件的1-Port IP 内核信号.........................................................................................4-2MAX 10器件的RAM: 1-Port IP内核参数............................................................................................4-3RAM: 2-PORT IP内核参考................................................................................5-1 MAX 10器件的RAM: 2-Port IP内核信号(简单双端口RAM)........................................................5-5 MAX 10器件的RAM: 2-Port IP内核信号(真双端口RAM) ...........................................................5-7 MAX 10器件的RAM: 2-Port IP内核参数............................................................................................5-9 ROM：1-PORT IP内核参考..............................................................................6-1 MAX 10器件的ROM：1-PORT IP内核信号......................................................................................6-2 MAX 10器件的ROM：1-PORT IP内核参数......................................................................................6-4 ROM: 2-PORT IP内核参考................................................................................7-1 ROM: MAX 10器件的2-PORT IP内核信号........................................................................................7-3 MAX 10器件的ROM:2-Port IP内核参数 ...........................................................................................7-4移位寄存器（基于RAM）IP内核参考............................................................8-1 MAX 10器件的移位寄存器(基于RAM)IP内核信号........................................................................8-1 MAX 10器件的移位寄存器(基于RAM) IP内核参数.......................................................................8-2 FIFO IP内核参考................................................................................................9-1 MAX 10器件的FIFO IP内核信号 ........................................................................................................9-2 MAX 10器件的FIFO IP内核参数 ........................................................................................................9-4ALTMEMMULT IP内核参考...........................................................................10-1 MAX 10器件的ALTMEMMULT IP内核信号..................................................................................10-1 MAX 10器件的ALTMEMMULT IP内核参数..................................................................................10-2 MAX 10嵌入式存储器用户指南的附加信息...................................................A-1 MAX 10嵌入式存储器用户指南的文档修订历史.............................................................................A-1MAX® 10嵌入式存储器模块已被优化，以用于诸如高吞吐量数据包处理、嵌入式处理器编程和嵌入式数据存储的应用程序。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
MAX 10 FPGA器件概述MAX® 10器件是单芯片，非易失性，低成本的可编程逻辑器件（PLD），集成了一组优化的系统组件。
MAX 10器件的特性如下：•内部存储的双配置闪存•用户闪存•即时接通支持•集成的模拟到数字转换器（ADC）•单芯片Nios II软核处理器支持MAX 10器件是系统管理，I/O扩展，通信控制平面，工业，汽车和消费者应用程序的理想解决方案。
相关链接MAX 10 FPGA器件数据表MAX 10器件的主要优势表1: MAX 10器件的主要优势© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos aretrademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.ISO 9001:2008 Registered101 Innovation Drive, San Jose, CA 95134MAX 10器件特性汇总表2: MAX 10器件的特性汇总2MAX 10器件特性汇总M10-OVERVIEW2015.11.02Altera 公司M10-OVERVIEW 2015.11.02MAX 10器件特性汇总3Altera 公司反馈MAX 10器件订购信息图1: MAX 10器件的订购代码样例和可用选项——初步器件系列WLCSP 封装类型36 : 36 pins, 3 mm x 3 mm 81 : 81 pins, 4 mm x 4 mmEQFP 封装类型144 : 144 pins, 22 mm x 22 mm UBGA 封装类型169 : 169 pins, 11 mm x 11 mm 324 : 324 pins, 15 mm x 15 mmFBGA 封装类型256 : 256 pins, 17 mm x 17 mm484 : 484 pins, 23 mm x 23 mm672: 672 pins, 27 mm x 27 mm MBGA 封装类型153 : 153 pins, 8 mm x 8 mm可选后缀指示特定器件选项 或运输方法 SC : 单电源::SA :单电源DC 双电源DF 双电源DA双电源特性选项02 : 2K 04 : 4K 08 : 8K 16 : 16K 25 : 25K 40 : 40K 50:50K 成员代码10M : MAX 10G : RoHS6ES : 工程样品: 商用级 (T = 0° C to 85° C): 工业级(T = - 40° C to 100° C): 汽车级 (T = - 40° C to 125° C)JJJ 注意:在Quartus Prime 软件中，默认情况下–I6 速度等级MAX 10 FPGA 器件选项是不可用的。
请联系您当地的Altera 销售代表以获得支持。
相关链接Altera 产品选择器提供关于Altera 产品的最新信息。
MAX 10器件特性选项表3: MAX 10器件特性选项4MAX 10器件订购信息M10-OVERVIEW2015.11.02Altera 公司MAX 10器件最大资源表4: MAX 10器件的最大资源数—初步(1)包括用户闪存和配置闪存的最大可能值。
请参考MAX 10用户闪存用户指南来获得更多信息 。
M10-OVERVIEW 2015.11.02MAX 10器件最大资源5Altera 公司反馈MAX 10器件每种封装的I/O 资源表5: MAX 10单电源供电器件的封装规划—初步表6: MAX 10双电源供电器件的封装规划—初步相关链接•MAX 10通用I/O 用户指南•MAX 10高速LVDS I/O 用户指南6MAX 10器件每种封装的I/O 资源M10-OVERVIEW2015.11.02Altera 公司MAX 10纵向移植支持纵向移植支持将您的设计移植到相同封装中有类似I/O 和ADC 资源的不同密度的其它MAX 10器件中。
MAX 10 I/O 纵向移植支持图2: MAX 10器件间的移植能力—初步•箭头表示移植路径。
包含在每条纵向移植路径中的器件呈阴影。
有些封装有几条移植路径。
相同路径中有较少I/O 资源的器件呈更浅的阴影。
•要实现相同移植路径中不同器件型号之间完整的I/O 移植，需要限制I/O 的使用来匹配最低I/O 数的产品系列。
注意:要验证管脚移植能力，请使用Quartus Prime 软件Pin Planner 中的Pin Migration View 视图。
M10-OVERVIEW 2015.11.02MAX 10纵向移植支持7Altera 公司反馈MAX 10 ADC 纵向移植支持图3: MAX 10器件间的ADC 纵向移植—初步箭头表示ADC 移植路径。
包含在每条纵向移植路径中的器件呈阴影。
双ADC 器件：每个ADC (ADC1和ADC2)支持1个专用模拟输入管脚和8个双功能管脚。
单ADC 器件：单ADC 支持1个专用模拟输入管脚和16个双功能管脚。
单ADC 器件：单ADC 支持1个专用模拟输入管脚和8个双功能管脚。
表7: ADC 移植的管脚移植条件逻辑单元和逻辑阵列模块LAB 包括16个逻辑单元和1个LAB-wide 控制模块。
LE 是MAX 10器件体系结构中逻辑的最小单元。
每个LE 有4个输入，一个四输入查找表（LUT ），一个寄存器和输出逻辑。
四输入LUT 是一个功能生成器，通过4个变量可以实现任何功能。
8MAX 10 ADC 纵向移植支持M10-OVERVIEW2015.11.02Altera 公司图4: MAX 10器件系列LERegister Chain模拟到数字转换器MAX 10器件有多达两个ADC 。
您可以使用ADC 监控多个不同的信号，包括片上温度。
表8: ADC 特性M10-OVERVIEW 2015.11.02模拟到数字转换器9Altera 公司反馈用户闪存MAX 10器件中的用户闪存（UFM ）模块存储非易失性信息。
UFM 提供一个理想的存储解决方案，通过使用Avalon Memory-Mapped (Avalon-MM)从接口协议进行访问。
表9: UFM 特性嵌入式乘法器和数字信号处理支持MAX 10器件支持高达144个嵌入式乘法器模块。
每个模块支持一个独立的18×18-bit 乘法器或两个独立的9×9-bit 乘法器。
通过片上资源与MAX 10器件中外部接口的相结合，您能够构建具有高性能，低系统成本和低功耗的DSP 系统。
MAX 10器件可单独使用，也可用作DSP 器件协处理器以提高DSP 系统的性价比。
通过使用下面的选项可以控制嵌入式乘法器模块的操作：•使用Quartus Prime 参数编辑器对相关的IP 内核进行参数化•通过VHDL 或Verilog HDL直接映射乘法器为MAX 10器件提供的系统设计功能：•DSP IP 内核：•通用DSP 处理功能，例如：有限脉冲响应（FIR ），快速傅立叶变换（FFT ）和数控振荡器（NCO ）功能•通用视频和图像处理功能套件•终端市场应用的完整参考设计•Quartus Prime 软件与MathWorks Simulink 和MATLAB 设计环境之间的DSP Builder 接口工具•DSP 开发工具10用户闪存M10-OVERVIEW2015.11.02Altera 公司嵌入式存储器模块嵌入式存储器结构由M9K 存储器模块列组成。
MAX ® 10器件中的每个M9K 存储器模块都提供一个能够运行在高达284 MHz 的9 Kb 片上存储器。
M9K 存储器模块可以配置成RAM ，FIFO 缓冲器或者ROM 。
MAX 10器件存储器块被优化用于高吞吐量数据包处理，嵌入式处理器程序和嵌入式数据存储等应用。
表10: M9K 操作模式和端口宽度时钟和PLLMAX® 10器件提供以下资源：全局时钟（GCLK ）网络和具有116-MHz 内置振荡器的锁相环（PLL ）。
MAX 10器件最多可支持20个操作频率高达450 MHz 的全局时钟(GCLK)网络。
GCLK 网络具有高驱动强度和低偏斜。
PLL 对器件时钟管理、外部系统时钟管理以及高速I/O 接口提供了可靠的时钟管理与综合。
高精确度和低抖动PLL 具有如下特性：•降低了电路板上所需要的振荡器的数量•通过从单一参考时钟源的多个时钟频率综合，减少器件中使用的时钟管脚•频率综合•片上时钟去偏斜•抖动衰减•动态相移•零延迟缓存•计数器重配置•带宽重配置•可编程输出占空比•PLL 级联•参考时钟切换•ADC 模块驱动M10-OVERVIEW 2015.11.02嵌入式存储器模块11Altera 公司反馈FPGA 通用I/OMAX ® 10 I/O 缓存支持多种可编程特性。