基于FPGA的温度传感器DS B 读写代码

1: begin dq <= 1'bz ; if (cnt == 17'd4) begin READ_BIT_CNT <= 2 ; cnt <= 17'd0 ; end else begin cnt <= cnt + 1'b1 ; end end
2: begin dq <= 1'bz ; tmp_bit <= dq ; if (cnt == 17'd1) begin READ_BIT_CNT <= 3 ; cnt <= 17'd0 ; end
input clk1m;
inout dq; //单数据总线
input rst_n; //复位
input reset_n;
output[23:0] DS_dataout; //接收数据寄存器，保存直至下一个数据来到
output DS_fifo_wr;
//写数据到 FIFO，产生一个时钟周期的高电平
reg dq;
begin STATE <= WRITE_LOW ;
end else begin
STATE <= WRITE_HIGH ; end WRITE_BYTE_CNT <= WRITE_BYTE_CNT +
end 8:
begin if (WRITE_BYTE_FLAG == 0) begin STATE <= CMD_44 ;
//DS_wr_int 信号寄存器，捕捉下降沿滤
always @ (posedge clk or negedge rst_n) begin if(!rst_n) begin
DS_rx_int0 <= 1'b0; DS_rx_int1 <= 1'b0; DS_rx_int2 <= 1'b0; end else begin DS_rx_int0 <= DS_wr_int;
温度传感器 DS18B20Verilog 读写代码 `timescale 1ns / 1ps module DS18B20 (clk,clk1m,dq, rst_n, reset_n,DS_dataout, DS_fifo_wr); // 约 5-6ms 完成一次读温度
input clk; //50M 主时钟
STATE <= WAIT4MS ; DS_wr_int <= 1'b0;
end
default : begin STATE <= RESET ;
end endcase
end end
assign DS_dataout = DS_dataout_r;
reg DS_rx_int0,DS_rx_int1,DS_rx_int2; 波用
reg [15:0] DS_dataout_r;
reg DS_wr_int;
//FIFO 写入请求的下降沿信号
//------------------------------------------定义的状态
parameter[3:0] RESET = 0;
//复位状态
parameter[3:0] CMD_CC = 1;
else begin
cnt <= cnt + 1'b1 ; end end 3: begin dq <= 1'bz ; if (cnt == 17'd55) begin
cnt <= 17'd0 ; READ_BIT_CNT <= 0 ; STATE <= GET_TMP ; end else begin cnt <= cnt + 1'b1 ; end end default : begin READ_BIT_CNT <= 0 ;
DS_wr_int <= 1'b1; end else begin
case (STATE) RESET : begin
if (cnt >= 17'd0 & cnt < 17'd500) begin
dq <= 1'b0 ; cnt <= cnt + 1'b1 ; STATE <= RESET ; end else if (cnt >= 17'd500 & cnt < 17'd510) begin dq <= 1'bz ; cnt <= cnt + 1'b1 ; STATE <= RESET ; end else if (cnt >= 17'd510 & cnt < 17'd750) begin
dq <= 1'bz ; if (cnt == 17'd5) begin
cnt <= 17'd0 ; WRITE_LOW_CNT <= 2 ; end else begin cnt <= cnt + 1'b1 ; end end 2: begin STATE <= WRITE_BYTE ; WRITE_LOW_CNT <= 0 ; end default : begin WRITE_LOW_CNT <= 0 ; end endcase end
temp <= dq ; if (cnt == 17'd580) begin
temp <= dq ;
end cnt <= cnt + 1'b1 ; STATE <= RESET ; end else if (cnt >= 17'd750) begin cnt <= 17'd0 ; STATE <= CMD_CC ; end end CMD_CC : begin
STATE <= RESET ; write_temp <= 8'b00000000; WRITE_BYTE_CNT <= 0; WRITE_LOW_CNT <= 0; WRITE_HIGH_CNT <= 0; READ_BIT_CNT <= 0; GET_TMP_CNT <= 0; cnt <= 17'd0; WRITE_BYTE_FLAG <= 0; TMP <= 0;
end CMD_BE :
begin write_temp <= 8'b10111110 ; STATE <= WRITE_BYTE ;
end READ_BIT :
begin case (READ_BIT_CNT) 0: begin dq <= 1'b0 ; if (cnt == 17'd4) begin READ_BIT_CNT <= 1 ; cnt <= 17'd0 ; end else begin cnt <= cnt + 1'b1 ; end end
parameter[3:0] CMD_BE = 7;
// parameter[3:0] WAIT800MS = 8;
parameter[3:0] GET_TMP = 9;
parameter[3:0] WAIT4MS = 10;
reg[3:0] STATE; reg[7:0] write_temp; reg[15:0] TMP; reg tmp_bit; reg[3:0] WRITE_BYTE_CNT; reg[1:0] WRITE_LOW_CNT; reg[1:0] WRITE_HIGH_CNT; reg[1:0] READ_BIT_CNT;
end endcase end
1'b1 ; 1'b1 ;
GET_TMP : begin case (GET_TMP_CNT) 0: begin STATE <= READ_BIT ; GET_TMP_CNT <= GET_TMP_CNT +
end 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 :
WRITE_BYTE_FLAG <= 1 ; end else if (WRITE_BYTE_FLAG == 1) begin
STATE <= RESET ; WRITE_BYTE_FLAG <= 2 ; end else if (WRITE_BYTE_FLAG == 2) begin STATE <= CMD_BE ; WRITE_BYTE_FLAG <= 3 ; end else if (WRITE_BYTE_FLAG == 3) begin STATE <= GET_TMP ; WRITE_BYTE_FLAG <= 0 ; end WRITE_BYTE_CNT <= 0 ; end default : begin STATE <= RESET ;
DS_rx_int1 <= DS_rx_int0; DS_rx_int2 <= DS_rx_int1; end end
assign DS_fifo_wr = ~DS_rx_int1 & DS_rx_int2; // 捕 捉 到 下 降 沿 后 ， DS_fifo_wr 拉高保持一个主时钟周期
endmodule
end endcase end WRITE_LOW : begin
case (WRITE_LOW_CNT) 0: begin dq <= 1'b0 ; if (cnt == 17'd70) begin cnt <= 17'd0 ; WRITE_LOW_CNT <= 1 ; end else begin cnt <= cnt + 1'b1 ; end end 1: begin