Compactly supported tight affine spline frames in L2(Rd
orca最佳互相避免碰撞 python代码
orca最佳互相避免碰撞python代码如何使用Python 编写最佳的Orca 互相避免碰撞算法？随着机器人技术的快速发展，人们对自主移动机器人的需求也越来越大。
在众多自主移动机器人中，Orca (Optimal Reciprocal Collision Avoidance) 算法是一种有效的互相避免碰撞方式。
本文将向你展示如何使用Python 编写最佳的Orca 互相避免碰撞算法。
Orca 算法的核心思想是通过计算机移动机器人的速度和方向，与周围机器人的速度进行优化，以避免碰撞。
它采用了一种递归计算的方法，以获得最佳的机器人移动方向。
首先，我们需要定义几个重要的变量。
每个机器人都有一个位置和速度的向量表示。
我们可以使用Python 的numpy 库来处理向量。
我们还需要定义机器人的预期速度、最大速度和最大加速度等参数。
接下来，我们需要编写一个函数来计算每个机器人的预期速度。
这个函数会根据当前机器人的位置和速度，和周围机器人的位置和速度来计算预期速度。
我们可以使用numpy 提供的函数来计算向量的长度和夹角。
具体代码如下：pythonimport numpy as npdef computeDesiredVelocity(robot, others):# 计算机器人和其他机器人的相对位置relativePositions = others[:, 0:2] - robot[0:2]# 计算机器人和其他机器人的相对速度relativeVelocities = others[:, 2:4] - robot[2:4]# 计算机器人和其他机器人的相对距离distances = np.linalg.norm(relativePositions, axis=1)# 计算机器人和其他机器人的相对速度的夹角angles = np.arctan2(relativeVelocities[:, 1], relativeVelocities[:, 0]) - np.arctan2(relativePositions[:, 1], relativePositions[:, 0])# 根据相对位置和速度计算预期速度desiredVelocities = np.zeros((len(others), 2))for i in range(len(others)):# 通过距离和夹角计算预期速度desiredSpeed = distances[i] / 0.1if np.abs(angles[i]) < np.pi / 4:desiredVelocities[i] = desiredSpeed *np.array([np.cos(angles[i]), np.sin(angles[i])])return desiredVelocities在上述代码中，我们首先计算每个机器人与其他机器人的相对位置和相对速度。
16-100A 16-100电流重型，600V三极配置说明书
Technical information
OT16E3C
UL General Purpose Amp Rating IEC AC21 amp rating Approvals
Maximum Operating Voltage Technical Ratings - UL
Maximum Horsepower Ratings Three Phase
Defeatable
Yes Yes
Padlockable
Yes Yes
Weight (lbs)
0.29 0.29
Catalog Number
OHB65J5E011 OHB65L5E011
OT16, 25, 32E3C & E4C – Transfer switches
1.38 35
0.18 DIA. 4.5
On-Load Switching
Electrical Characteristics of the OT transfer switch line allows on-load switching between two power supplies, adding value to and enhancing the performance of the transfer switch and its applications.
Clear Position Indication
ABB Manual Transfer Switches are equipped with three definite positions (I-O-II). Isolation between two power supplies is guaranteed by the contact mechanisms, designed as a positive opening construction with mechanically operated contacts.
ULPI_v1_1
UTMI+ Low Pin Interface (ULPI)SpecificationRevision 1.1October 20, 2004Revision HistoryDate CommentRevision Issue0.9 November 12, 2003 Pre-release.1.0rc1 January 3, 2004 Introduce PHY interface “modes”.Update interface timings. Clarify 4-bit data clocking.Clarify sending of RX CMD’s and interrupts.Introduce AutoResume feature.Route int pin to data(3) during 6-pin Serial Mode.Explain VBUS thresholds.Add T&MT diagram and updated text.Add new section to explain how PHY is aborted by Link.Various clarifications.1.0rc2 January 13, 2004 Add block diagram.Tighten interface timing.Modify suspend protocol to more closely resemble UTMI.Add SPKR_L and SPKR_MIC to signal list and T&MTconnector.Various clarifications.1.0rc3 January 19, 2004 Specify that PHY must send RX CMD after Reset.Link + PHY clock startup time of no more than 5.6ms for aperipheral is now mandatory.PHY output delay reduced from 10ns to 9ns.Added link decision time numbers for low speed.Various Clarifications.1.0 February 2, 2004 1.0rc3 adopted as 1.0 release.1.1rc1 September 1, 2004 Various clarifications and fixes to hold time numbers, sendingRXCMDs, FsLsSerialMode, Vbus control and monitoring,Test_J and Tesk_K signalling, Low Power Mode,Hostdisconnect, ID detection, HS SOF packets, interrupts,Carkit Mode, interface protection, No SYNC/EOP mode,linestate filtering, and AutoResume.1.1rc2 October 4, 2004 Re-arranged text in section 3.8.7.3. Updated contributors list.1.1 October 20, 2004 1.1rc2 adopted as 1.1 release.The present Specification has been circulated for the sole benefit of legally-recognized Promoters, Adopters and Contributors of the Specification. All rights are expressly reserved, including but not limited to intellectual property rights under patents, trademarks, copyrights and trade secrets. The respective Promoter's, Adopter's or Contributor's agreement entered into by Promoters, Adopters and Contributors sets forth their conditions of use of the Specification.iiPromotersARC International Inc.Conexant Systems, Inc.Mentor Graphics CorporationPhilipsSMSCTransDimension, Inc.ContributorsVertenten PhilipsBartOkur PhilipsBatuhanBillAnderson MotorolaMcInerney TransDimensionBillBooker CypressBrianARCBelangerChrisKolb ARCChrisChrisSchell PhilipsChung Wing Yan PhilipsSrokaPhilipsDaveWang PhilipsDavidWooten TransDimensionDavidSMSCEricKawamotoPhilipsMackayFarranFrazier ConexantFrankFredRoberts SynopsysFarooqConexantHassanLee TransDimensionHyunParr MentorIanStandiford TransDimensionJayPhilipsTjiaJeromeMentorSaundersMarkMohamed Benromdhane ConexantSMSCMorganMonksISINabilTaklaTengstrand ARCPeterRamanand Mandayam ConexantDouglas MentorRobSaleemMohamed Synopsys(Author)ShaunReemeyer PhilipsCypressSimonNguyenSubramanyam Sankaran PhilipsTexasInstrumentsViningSueRemple QualcommTerryChen ConexantTimothyConexantChangVincentQuestions should be emailed to lpcwg@.iiiTable of Contents1.Introduction (1)1.1General (1)1.2Naming Convention (1)1.3Acronyms and Terms (1)1.4References (1)2.Generic Low Pin Interface (2)2.1General (2)2.2Signals (2)2.3Protocol (3)2.3.1Bus Ownership (3)2.3.2Transferring Data (3)2.3.3Aborting Data (4)3.UTMI+ Low Pin Interface (5)3.1General (5)3.2Signals (6)3.3Block Diagram (7)3.4Modes (9)3.5Power On and Reset (10)3.6Interrupt Event Notification (10)3.7Timing (11)3.7.1Clock (11)3.7.2Control and Data (13)3.8Synchronous Mode (15)3.8.1ULPI Command Bytes (15)3.8.2USB Packets (18)3.8.3Register Operations (30)3.8.4Aborting ULPI Transfers (37)3.8.5USB Operations (39)3.8.6Vbus Power Control (internal and external) (52)3.8.7OTG Operations (52)3.9Low Power Mode (55)3.9.1Data Line Definition For Low Power Mode (55)3.9.2Entering Low Power Mode (55)3.9.3Exiting Low Power Mode (56)3.9.4False Resume Rejection (57)3.10Full Speed / Low Speed Serial Mode (Optional) (58)3.10.1Data Line Definition For FsLsSerialMode (58)3.10.2Entering FsLsSerialMode (59)3.10.3Exiting FsLsSerialMode (60)3.11Carkit Mode (Optional) (61)3.12Safeguarding PHY Input Signals (62)4.Registers (65)4.1Register Map (65)4.2Immediate Register Set (67)4.2.1Vendor ID and Product ID (67)4.2.2Function Control (68)4.2.3Interface Control (69)4.2.4OTG Control (71)4.2.5USB Interrupt Enable Rising (72)4.2.6USB Interrupt Enable Falling (73)4.2.7USB Interrupt Status (74)4.2.8USB Interrupt Latch (75)4.2.9Debug (76)4.2.10Scratch Register (76)4.2.11Carkit Control (77)4.2.12Carkit Interrupt Delay (77)iv4.2.13Carkit Interrupt Enable (78)4.2.14Carkit Interrupt Status (78)4.2.15Carkit Interrupt Latch (79)4.2.16Carkit Pulse Control (79)4.2.17Transmit Positive Width (80)4.2.18Transmit Negative Width (80)4.2.19Receive Polarity Recovery (80)4.2.20Reserved (81)4.2.21Access Extended Register Set (81)4.2.22Vendor-specific (81)4.3Extended Register Set (81)4.4Register Settings for all Upstream and Downstream signalling modes (81)5.T&MT Connector (83)5.1General (83)5.2Daughter-card (UUT) Specification (83)vFiguresFigure 1 – LPI generic data bus ownership (3)Figure 2 – LPI generic data transmit followed by data receive (3)Figure 3 – Link asserts stp to halt receive data (4)Figure 4 – Creating a ULPI system using wrappers (5)Figure 5 – Block diagram of ULPI PHY (7)Figure 6 – Jitter measurement planes (12)Figure 7 – ULPI timing diagram (13)Figure 8 – Clocking of 4-bit data interface compared to 8-bit interface (14)Figure 9 – Sending of RX CMD (17)Figure 10 – USB data transmit (NOPID) (18)Figure 11 – USB data transmit (PID) (19)Figure 12 – PHY drives an RX CMD to indicate EOP (FS/LS LineState timing not to scale) (20)Figure 13 – Forcing a full/low speed USB transmit error (timing not to scale) (21)Figure 14 – USB receive while dir was previously low (22)Figure 15 – USB receive while dir was previously high (23)Figure 16 – USB receive error detected mid-packet (24)Figure 17 – USB receive error during the last byte (25)Figure 18 – USB HS, FS, and LS bit lengths with respect to clock (26)Figure 19 – HS transmit-to-transmit packet timing (29)Figure 20 – HS receive-to-transmit packet timing (29)Figure 21 – Register write (30)Figure 22 – Register read (31)Figure 23 – Register read or write aborted by USB receive during TX CMD byte (31)Figure 24 – Register read turnaround cycle or Register write data cycle aborted by USB receive (32)Figure 25 – USB receive in same cycle as register read data. USB receive is delayed (33)Figure 26 – Register read followed immediately by a USB receive (33)Figure 27 – Register write followed immediately by a USB receive during stp assertion (34)Figure 28 – Register read followed by a USB receive (34)Figure 29 – Extended register write (35)Figure 30 – Extended register read (35)Figure 31 – Extended register read aborted by USB receive during extended address cycle (36)Figure 32 – PHY aborted by Link asserting stp. Link performs register write or USB transmit (37)Figure 33 – PHY aborted by Link asserting stp. Link performs register read (38)Figure 34 – Link aborts PHY. Link fails to drive a TX CMD. PHY re-asserts dir (38)Figure 35 – Hi-Speed Detection Handshake (Chirp) sequence (timing not to scale) (40)Figure 36 – Preamble sequence (D+/D- timing not to scale) (41)Figure 37 – LS Suspend and Resume (timing not to scale) (43)Figure 38 – FS Suspend and Resume (timing not to scale) (44)Figure 39 – HS Suspend and Resume (timing not to scale) (46)Figure 40 – Low Speed Remote Wake-Up from Low Power Mode (timing not to scale) (47)Figure 41 – Full Speed Remote Wake-Up from Low Power Mode (timing not to scale) (48)Figure 42 – Hi-Speed Remote Wake-Up from Low Power Mode (timing not to scale) (49)Figure 43 – Automatic resume signalling (timing not to scale) (50)Figure 44 – USB packet transmit when OpMode is set to 11b (51)Figure 45 – RX CMD V A_VBUS_VLD ≤Vbus indication source (54)Figure 46 – Entering low power mode (55)Figure 47 – Exiting low power mode when PHY provides output clock (56)Figure 48 – Exiting low power mode when Link provides input clock (56)Figure 49 – PHY stays in Low Power Mode when stp de-asserts before clock starts (57)Figure 50 – PHY re-enters Low Power Mode when stp de-asserts before dir de-asserts (57)Figure 51 – Interface behaviour when entering Serial Mode and clock is powered down (59)Figure 52 – Interface behaviour when entering Serial Mode and clock remains powered (59)Figure 53 – Interface behaviour when exiting Serial Mode and clock is not running (60)Figure 54 – Interface behaviour when exiting Serial Mode and clock is running (60)Figure 55 – PHY interface protected when the clock is running (62)Figure 56 – Power up sequence when PHY powers up before the link. Interface is protected (63)Figure 57 – PHY automatically exits Low Power Mode with interface protected (63)Figure 58 – Link resumes driving ULPI bus and asserts stp because clock is not running (64)viFigure 59 – Power up sequence when link powers up before PHY (ULPI 1.0 compliant links) (64)Figure 60 – Recommended daughter-card configuration (not to scale) (83)viiTablesTable 1 – LPI generic interface signals (2)Table 2 – PHY interface signals (6)Table 3 – Mode summary (9)Table 4 – Clock timing parameters (11)Table 5 – ULPI interface timing (13)Table 6 – Transmit Command (TX CMD) byte format (15)Table 7 – Receive Command (RX CMD) byte format (16)Table 8 – USB specification inter-packet timings (26)Table 9 – PHY pipeline delays (27)Table 10 – Link decision times (28)Table 11 – OTG Control Register power control bits (52)Table 12 – Vbus comparator thresholds (52)Table 13 – RX CMD VbusValid over-current conditions (53)Table 14 – Vbus indicators in the RX CMD required for typical applications (54)Table 15 – Interface signal mapping during Low Power Mode (55)Table 16 – Serial Mode signal mapping for 6-pin FsLsSerialMode (58)Table 17 – Serial Mode signal mapping for 3-pin FsLsSerialMode (58)Table 18 – Carkit signal mapping (61)Table 19 – Register map (66)Table 20 – Register access legend (67)Table 21 – Vendor ID and Product ID register description (67)Table 22 – Function Control register (68)Table 23 – Interface Control register (70)Table 24 – OTG Control register (71)Table 25 – USB Interrupt Enable Rising register (72)Table 26 – USB Interrupt Enable Falling register (73)Table 27 – USB Interrupt Status register (74)Table 28 – USB Interrupt Latch register (75)Table 29 – Rules for setting Interrupt Latch register bits (75)Table 30 – Debug register (76)Table 31 – Scratch register (76)Table 32 – Carkit Control Register (77)Table 33 – Carkit Interrupt Delay register (77)Table 34 – Carkit Interrupt Enable register (78)Table 35 – Carkit Interrupt Status Register (78)Table 36 – Carkit Interrupt Latch register (79)Table 37 – Carkit Pulse Control (79)Table 38 – Transmit Positive Width (80)Table 39 – Transmit Negative Width (80)Table 40 – Receive Polarity Recovery (81)Table 41 – Upstream and downstream signalling modes (82)Table 42 – T&MT connector pin view (84)Table 43 – T&MT connector pin allocation (84)Table 44 – T&MT pin description (85)viii1. Introduction1.1 GeneralThis specification defines a generic PHY interface in Chapter 2.In Chapter 3, the generic interface is applied to the UTMI+ protocol, reducing the pin count for discrete USB transceiver implementations supporting On-The-Go, host, and peripheral application spaces.Convention1.2 NamingEmphasis is placed on normal descriptive text using underlined Arial font, e.g. must.Signal names are represented using the lowercase bold Arial font, e.g. clk.Registers are represented using initial caps, bold Arial font, e.g. OTG Control.Register bits are represented using initial caps, bold italic Arial font, e.g. USB Interrupt Enable Falling. 1.3 Acronyms and TermsA-device Device with a Standard-A or Mini-A plug inserted into its receptacleB-device Device with a Standard-B or Mini-B plug inserted into its receptacleDeviceDRD Dual-RoleFPGA Field Programmable Gate ArraySpeedFS FullHNP Host Negotiation ProtocolHS Hi-SpeedLink ASIC, SIE, or FPGA that connects to an ULPI transceiverLPI Low Pin InterfaceSpeedLS LowOTG On-The-GoPHY Physical Layer (Transceiver)PLL Phase Locked LoopSE0 Single Ended ZeroSIE Serial Interface EngineSRP Session Request ProtocolT&MT Transceiver and Macrocell TesterULPI UTMI+ Low Pin InterfaceUSB Universal Serial BusUSB-IF USB Implementers ForumUTMI USB 2.0 Transceiver Macrocell InteraceUUT Unit Under Test1.4 References[Ref 1] Universal Serial Bus Specification, Revision 2.0[Ref 2] On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a[Ref 3] USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, v1.05[Ref 4] UTMI+ Specification, Revision 1.0[Ref 5] CEA-2011, OTG Transceiver Specification[Ref 6] CEA-936A, Mini-USB Analog Carkit Interface Specification[Ref 7] USB 2.0 Transceiver and Macrocell Tester (T&MT) Interface Specification, Version 1.212. Generic Low Pin Interface2.1 GeneralThis section describes a generic low pin interface (LPI) between a Link and a PHY. Interface signals are defined and the basic communication protocol is described. The generic interface can be used as a common starting point for defining multiple application-specific interfaces.Chapter 3 defines the UTMI+ Low Pin Interface (ULPI), which is based on the generic interface described here. For ULPI implementations, the definitions in chapter 3 over-ride anything defined in chapter 2.2.2 SignalsThe LPI transceiver interface signals are described in Table 1. The interface described here is generic, and can be used to transport many different data types. Depending on the application, the data stream can be used to transmit and receive packets, access a register set, generate interrupts, and even redefine the interface itself. All interface signals are synchronous when clock is toggling, and asynchronous when clock is not toggling. Data stream definition is application-specific and should be explicitly defined for each application space for inter-operability.Control signals dir, stp, and nxt are specified with the assumption that the PHY is the master of the data bus. If required, an implementation can define the Link as the master. If the Link is the master of the interface, the control signal direction and protocol must be reversed.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. Both directions are allowed. All interface signals are synchronous to clock.data I/O Bi-directional data bus, driven low by the Link during idle. Bus ownership is determined by dir. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. LPI defines interface timing for single-edge data transfers with respect to rising edge of clock. An implementation may optionally define double-edge data transfers with respect to both rising and falling edges of clock.dir OUT Direction. Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives dir high to take ownership of the bus. When the PHY has no data to transfer it drives dir low and monitors the bus for Link activity. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PHY PLL is not stable.stp IN Stop. The Link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, stp indicates the last byte of data was on the bus in the previous cycle. If the PHY is sending data to the Link, stp forces the PHY to end its transfer, de-assert dir and relinquish control of the the data bus to the Link.nxt OUT Next. The PHY asserts this signal to throttle the data. When the Link is sending data to the PHY, nxt indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle. When the PHY is sending data to the Link, nxt indicates when a new byte is available for the Link to consume.Table 1 – LPI generic interface signals22.3 ProtocolOwnership2.3.1 BusThe PHY is the master of the LPI bi-directional data bus. Ownership of the data bus is determined by the dir signal from the PHY, as shown in Figure 1. When dir is low, the Link can drive data on the bus. When dir is high, the PHY can drive data on the bus. A change in dir causes a turnaround cycle on the bus during which, neither Link nor PHY can drive the bus. Data during the turnaround cycle is undefined and must be ignored by both Link and PHY.The dir signal can be used to directly control the data output buffers of both PHY and Link.Figure 1 – LPI generic data bus ownershipData2.3.2 TransferringAs shown in the first half of Figure 2, the Link continuously drives the data bus to 00h during idle. The Link transmits data to the PHY by driving a non-zero value on the data bus. To signal the end of data transmission, the Link asserts stp in the cycle following the last data byte.In the second half of Figure 2, the Link receives data when the PHY asserts dir. The PHY asserts dir only when it has data to send to the Link, and keeps dir low at all other times. The PHY drives data to the Link after the turnaround cycle.The nxt signal can be used by the PHY to throttle the data during transmit and receive. During transmit, nxt may be asserted in the same cycle that the Link asserts stp.Figure 2 – LPI generic data transmit followed by data receive2.3.3 AbortingDataThe PHY can assert dir to interrupt any data being transmitted by the Link. If the Link needs to interrupt data being received from the PHY, it asserts stp for one clock cycle, as shown in Figure 3. This causes the PHY to unconditionally1 de-assert dir and accept a complete data transmit from the Link. The PHY may re-assert dir again only when the data transmit from the Link has completed.Figure 3 – Link asserts stp to halt receive data1 The PHY will not de-assert dir if the ULPI interface is not usable. For example, if the internal PLL is not stable.3. UTMI+ Low Pin Interface3.1 GeneralThis section describes how any UTMI+ core can be wrapped to convert it to the smaller LPI interface. The generic interface described in chapter 2 is used as a starting point. This section always over-rides anything stated in chapter 2. While this specification details support of UTMI+ Level 3, PHY implementers may choose to support any of the Levels defined in UTMI+.ULPI defines a PHY to Link interface of 8 or 12 signals that allows a lower pin count option for connecting to an external transceiver that may be based on the UTMI+ specification. The pin count reduction is achieved by having relatively static UTMI+ signals be accessed through registers and by providing a bi-directional data bus that carries USB data and provides a means of accessing register data on the ULPI transceiver.This specification relies on concepts and terminology that are defined in the UTMI+ specification [Ref 4]. Specifically, if a ULPI PHY design is based on an internal UTMI+ core, then that core must implement the following UTMI+ features.Linestate must accurately reflect D+/D- to within 2-3 clocks. It is up to individual Link designers to use Linestate to time bus events.Filtering to prevent spurious SE0/SE1 states appearing on Linestate due to skew between D+ and D-. Filtering of 14 clock cycles is required in Low Speed, and 2 clock cycles in Full Speed and Hi-Speed modes.The PHY must internally block the USB receive path during transmit. The receive path can be unblocked when the internal Squelch (HS) or SE0-to-J (FS/LS) is seen.TxReady must be used for all types of data transmitted, including Chirp.Due to noise on the USB, it is possible that RxActive asserts and then de-asserts without any valid data being received, and RxValid will not assert. The Link should operate normally with these data-less RxActive assertions.As shown in Figure 4, a PHY or Link based on this specification can be implemented as an almost transparent wrapper around existing UTMI+ IP cores, preserving the original UTMI+ packet timing, while reducing pin count and leaving all functionality intact. This should not be taken to imply that other implementations are not possible.Figure 4 – Creating a ULPI system using wrappers3.2 SignalsTable 2 describes the ULPI interface on the PHY. The PHY is always the master of the ULPI bus. USB and Miscellaneous signals may vary with each implementation and are given only as a guide to PHY designers.Signal Direction DescriptionPHY Interfaceclock I/O Interface clock. The PHY must be capable of providing a 60MHz output clock. Support for an input 60MHz clock is optional. If the PHY supports both clock directions, it must not use the ULPI control and data signals for setting the clock direction.Data bus. Driven to 00h by the Link when the ULPI bus is idle. Two bus widths are allowed:• 8-bit data timed on rising edge of clock.data I/O• (Optional) 4-bit data timed on rising and falling edges of clock.dir OUT Controls the direction of the data bus2. The PHY pulls dir high whenever the interface cannot accept data from the Link. For example, when the internal PLL is not stable. This applies whether Link or PHY is the clock source.stp IN The Link must assert stp to signal the end of a USB transmit packet or a register write operation, and optionally to stop any receive. The stp signal must be asserted in the cycle after the last data byte is presented on the bus.nxt OUT The PHY asserts nxt to throttle all data types, except register read data and the RX CMD. Identical to RxValid during USB receive, and TxReady during USB transmit. The PHY also asserts nxt and dir simultaneously to indicate USB receive activity (RxActive), if dir was previously low. The PHY is not allowed to assert nxt during the first cycle of the TX CMD driven by the Link.USB InterfaceD+ I/O D+ pin of the USB cable. Required.D- I/O D- pin of the USB cable. Required.ID IN ID pin of the USB cable. Required for OTG-capable PHY’s.VBUS I/O V BUS pin of the USB cable. Required for OTG-capable PHY’s. Required for driving V BUS and the V BUS comparators.MiscellaneousXI IN Crystal input pin. Vendors should specify supported crystal frequencies. XO OUT Crystal output pin.C+ I/O Positive terminal of charge pump capacitor.C- I/O Negative terminal of charge pump capacitor.SPKR_L IN Optional Carkit left/mono speaker input signal.SPKR_MIC I/O Optional Carkit right speaker input or microphone output signal.RBIAS I/O Bias current resistor.Table 2 – PHY interface signals2 UTMI+ wrapper developers should note that data bus control has been reversed from UTMI to ensure that USB data reception is not interrupted by the Link.3.3 BlockDiagramAn example block diagram of a ULPI PHY is shown in Figure 5. This example is based on an internal UTMI+ Level 3 core [Ref 4], which can interface to peripheral, host, and On-The-Go Link cores. A description of each major block is given below.ULPI InterfaceUSBCableChargePumpCapacitor Figure 5 – Block diagram of ULPI PHYUTMI+ Level 3 PHY coreThe ULPI PHY may contain a core that is compliant to any UTMI+ level [Ref 4]. Signals for 16-bit data buses are not supported in ULPI. While Figure 5 shows the typical blocks for a Level 3 UTMI+ core, the PHY vendor must specify the intended UTMI+ level, and provide the functionality necessary for compliance to that level.ULPI PHY WrapperThe ULPI PHY wrapper of Figure 5 reduces the UTMI+ interface to the Low Pin Interface described in this document. All signals shown on the UTMI+ Level 3 PHY core are reduced to the ULPI interface signals clock, data, dir, stp, and nxt. The Register Map stores the relatively static signals of the UTMI+ interface. Crystal Oscillator and PLLWhen a crystal is attached to the PHY, the internal clock(s) and the external 60MHz interface clock are generated from the internal PLL. When no crystal is attached, the PHY may optionally generate the internal clock(s) from an input 60MHz clock provided by the Link.General BiasingInternal analog circuits require an accurate bias current. This is typically generated using an external, accurate reference resistor.DrvVbusExternal and ExternalVbusIndicatorThe PHY may optionally control an external VBUS power source via the optional pin DrvVbusExternal. For example, the external supply could be a charge pump or 5V power supply controlled using a power switch. The external supply is controlled by the DrvVbus and the optional DrvVbusExternal bits in the OTG Control register. The polarity of the DrvVbusExternal output pin is implementation dependent.If control of an external VBUS source is provided the PHY may optionally provide for a VBUS power source feed back signal on the optional pin ExternalVbusIndicator. If this pin is provided, the use of the pin is defined by the optional control bits in the OTG Control and Interface Control registers. See Section 3.8.6.3 for further detail.Power-On-ResetA power-on-reset circuit must be provided in the PHY. When power is first applied to the PHY, the power-on-reset will reset all circuitry and leave the ULPI interface in a usable state.Carkit OptionThe PHY may optionally support Carkit Mode [Ref 6]. While in Carkit Mode, the PHY routes speaker and microphone signals between the Link and the USB cable. In carkit mono mode, SPKR_L inputs a mono speaker signal and SPKR_MIC outputs the microphone signal, MIC. In carkit stereo mode, SPKR_L inputs the left speaker signal, and SPKR_MIC inputs the right speaker signal, SPKR_R.3.4 ModesThe ULPI interface can operate in one of five independent modes listed in Table 3. The interface is in Synchronous Mode by default. Other modes are enabled by bits in the Function Control and Interface Control registers. In Synchronous Mode, the data bus carries commands and data. In other modes, the data pins are redefined with different functionality. Synchronous Mode and Low Power Mode are mandatory.Mode Name Mode DescriptionSynchronous Mode This is the normal mode of operation. The clock is running and is stablewith the characteristics defined in section 3.6. The ULPI interface carriescommands and data that are synchronous to clock.Low Power Mode The PHY is powered down with the clock stopped. The PHY keeps dirasserted, and the data bus is redefined to carry LineState and interrupts.See section 3.9 for more information.6-pin FS/LS Serial Mode (optional) The data bus is redefined to 6-pin serial mode, including 6 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. This mode is valid only for implementations with an 8-bit data bus. See section 3.10 for more information.3-pin FS/LS Serial Mode (optional) The data bus is redefined to 3-pin serial mode, including 3 pins to transmit and receive serial USB data, and 1 pin to signal interrupt events. The clock can be enabled or disabled. See section 3.10 for more information.Carkit Mode (optional) The data bus is redefined to Carkit mode [Ref 6], including 2 pins for serial UART data, and 1 pin to signal interrupt events. The clock may optionally be stopped. See section 3.11 for more information.Table 3 – Mode summary。
USB Type-C 规范1.2(中文版)
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03 ASCE Guideline for the Design of Buried Steel Pipe 2001
A public-private partnership to reduce risk to utility and transportation systems from natural hazardsA public-private partnership to reduce risk to utility and transportation systems from natural hazardsThis report was written under contract to the American LifelinesAlliance, a public-private partnership between the Federal EmergencyManagement Agency (FEMA) and the American Society of CivilEngineers (ASCE). This report was reviewed by a team representingpracticing engineers and academics.AcknowledgmentsThe following people (with their affiliations) contributed to this report.G. A. Antaki, Co-chairman WSRC, Aiken, SCJ. D. Hart, Co-chairman SSD, Inc., Reno, NVT. M. Adams Stevenson and Associates, Cleveland, OH C. Chern Bechtel, San Francisco, CAC. C. Costantino City College of New York, New York, NY R. W. Gailing Southern California Gas Co., Los Angeles, CA E. C. Goodling Parsons Energy & Chemicals, Reading, PA A. Gupta North Carolina State University, Raleigh, NC R. Haupt Pressure Piping Engineering, Foster City, CA A. P. Moser Utah State University, Logan, UTM. O’Rourke Rensselaer Polytechnic Institute, Troy, NY S. Peterson Lakehead Pipe Line Co., Bay City, MIM. Rosenfeld Kiefner & Associates, Worthington, OHJ. E. Thomas S/D Engineers, Pittsburgh, PATable of Contents1.0Introduction (1)1.1Project Objective (1)1.2Cautions (2)1.3Notations (3)2.0Internal Pressure (9)2.1 Sources of Internal Pressure (9)2.2 Example (9)3.0Vertical Earth Load (10)3.1 Applied Load (10)3.2 Deflection and Stress Under Soil Load (11)3.3 Example 1 (11)3.4 Example 2 (11)3.5 Example 3 (11)3.6 Figure (12)4.0Surface Live Loads (13)4.1 Applied Loads (13)4.2 Ovality and Stress (15)4.2.1 Ovality (15)4.2.2 Through-Wall Bending (15)4.2.3 Crushing of Side Walls (16)4.2.4 Ring Buckling (16)4.2.5 Fatigue (17)4.3 Example (17)4.4 Figures (19)5.0Surface Impact Loads (21)5.1 Maximum Impact Load (21)5.2 Penetration and PPV (21)5.3 Example (22)5.4 Figure (23)6.0Buoyancy (24)6.1 Applied Load (24)6.2 Pipe Stress (24)6.3 Example (25)6.4Figures (26)7.0Thermal Expansion (27)7.1 Expansion Loads and Stresses (27)7.2 Example (27)7.3 Figure (28)8.0Relative Pipe-Soil Displacement (29)8.1 Applied Load (29)8.2 Evaluation (29)8.3 Example (30)8.3.1 Pipeline Fault Crossing (30)8.4 Figures (32)9.0Movement at Pipe Bends (41)9.1 Pipe Movement (41)9.2 Evaluation (41)9.3 Figure (42)10.0Mine Subsidence (43)11.0Earthquake (44)11.1 Seismic Wave Propagation (44)11.2 Permanent Ground Displacement (45)11.3 Example (46)11.4 Figures (48)12.0Effects of Nearby Blasting (50)12.1 Applied Stress (50)12.2 Evaluation (52)12.3 Example (52)12.4 Figure (54)13.0Fluid Transients (55)13.1 Applied Loads (55)13.2 Evaluation (56)13.3 Example (56)14.0In-Service Relocation (58)14.1 Applied Load (58)14.2 Evaluation (59)14.3 Example (60)14.4 Figures (61)References and Bibliography (62)Appendix A: Suggested Acceptance Criteria (66)Appendix B: Soil Spring Representation (68)B.1 Axial Soil Springs (68)B.2 Lateral Soil Springs (69)B.3 Vertical Uplift Soil Springs (70)B.4 Vertical Bearing Soil Springs (71)B.5 References (71)B.6 Figures (72)Figure 3.1-1 Soil Prism Above Pipe (12)Figure 4.1-1 Surface Load and Transmitted Pressure (19)Figure 4.2-1 Ovality of Pipe Cross Section (19)Figure 4.2-2 Through-Wall Bending Stress (20)Figure 4.2-3 Crushing of Side Wall (20)Figure 4.2-4 Ring Buckling of Pipe Cross Section (20)Figure 5.1-1 Fall of a Heavy Object on Ground Surface (23)Figure 6.1-1 Resultant Buoyancy Load on Pipe (26)Figure 6.1-2 Distributed Buoyancy Load on Pipe (26)Figure 7.1-1 Bending Moment at Buried Pipe Bend Due to Constrained PipeExpansion (28)Figure 8.2-1 Pipeline Thaw Settlement Scenario (32)Figure 8.2-2 Finite Element Model of Pipeline Settlement (33)Figure 8.3-1 Buried Pipeline Subject to Vertical Fault Movement (34)Figure 8.3-2(a) Vertical Displacement Profile Along the Pipeline (35)Figure 8.3-2(b) Axial Displacement Profile Along the Pipeline (35)Figure 8.3-2(c) Axial Force Profile Along the Pipeline (36)Figure 8.3-2(d) Bending Moment Diagram Along the Pipeline (36)Figure 8.3-3(a) Top Fiber Axial Strain Diagram Along the Pipeline (37)Figure 8.3-3(b) Bottom Fiber Axial Strain Diagram Along the Pipeline (37)Figure 8.3-3(c) Pipe Curvature Diagram Along the Pipeline (38)Figure 8.3-3(d) Pipe Rotation Diagram Along the Pipeline (38)Figure 8.3-4(a) Force in Longitudinal Soil Springs Along the Pipeline (39)Figure 8.3-4(b) Displacement in Longitudinal Soil Springs Along the Pipeline (39)Figure 8.3-4(c) Force in Transverse Soil Springs Along the Pipeline (40)Figure 8.3-4(d) Displacement in Transverse Soil Springs Along the Pipeline (40)Figure 9.1-1 Model of Overbend (42)Figure 11.2-1 Direction of Ground Movement and Zones of Pipe Axial Tension and Compression for Longitudinal PGD where L is Small toModerate (48)Figure 11.2-2 Direction of Ground Movement and Zones of Pipe Axial Tension and Compression for Longitudinal PGD where the Length of thePGD Zone is Large (48)Figure 11.2-3 Transverse PGD With Spatial Extend W and Amount of (49)Figure 14.1-1 Pipeline Lowering with Transition Lengths L1 (61)Figure 14.1-2 Pipeline Lowering with Transition Lengths L1 and ObstructionLength L2 (61)Figure B.1 Pipeline Modeling Approach (72)Figure B.2 Plotted Values for the Adhesion Factor, (73)Figure B.3 Values of Nqh and Nch of Hansen 1961 (74)Figure B.4 Ranges for Values of Nqv and Ncv (from Trautman and O’Rourke, 1983) (75)Figure B.5 Plotted Values of Bearing Capacity Factors (Nq, Nc, and N ) (76)Table 4.1-1 Live Loads (13)Table 4.1-2 Impact Factor (F ) versus Height of Cover (14)Table 8.3-1 Soil Resistance Properties for Example Problem (31)Table 11.1-1 Peak Ground Velocity (45)Table 12.1 Empirical Coefficients for Estimating Velocity and Stress (51)Table 12.2 Normalization Factors for Common Types of Explosives (51)Table B.1 Friction factor f for Various External Coatings (69)1.0 IntroductionThe American Lifelines Alliance (ALA) was formed in 1998 under a cooperative agreement between the American Society of Civil Engineers (ASCE) and the Federal Emergency Management Agency (FEMA). In 1999, ALA requested a group of civil and mechanical engineers, listed in the Acknowledgements, to prepare a guide for the design of buried steel pipe. The group prepared the guidelines presented in this report, with an emphasis on the fundamental design equations suitable for hand calculations, and where necessary, guidance for finite element analysis.Objective1.1 ProjectThe purpose of this guide is to develop design provisions to evaluate the integrity of buried pipe for a range of applied loads. The provisions contained in this guide apply to the following kinds of buried pipe:New or existing buried pipe, made of carbon or alloy steel, fabricated to ASTM or API material specifications.Welded pipe, joined by welding techniques permitted by the ASME code or the API standards.Piping designed, fabricated, inspected and tested in accordance with an ASME B31 pressure piping code. These codes are: B31.1 power piping, B31.3 process piping, B31.4 liquid hydrocarbon pipelines, B31.5 refrigeration piping, B31.8 gas transmission anddistribution piping, B31.9 building services piping, B31.11 slurry piping, and ASMEBoiler and Pressure Vessel Code, Section III, Division 1 nuclear power plant piping.Buried pipe and its interface with buildings and equipment.Each section in the guide addresses a different form of applied load:2.0 Internal Pressure3.0 Vertical Earth Loads4.0 Surface Live Loads5.0 Surface Impact Loads6.0 Buoyancy7.0 Thermal Expansion8.0 Relative Pipe-Soil Displacement9.0 Movement at Pipe Bends10.0 Mine Subsidence11.0 Earthquake12.0 Effects of Nearby Blasting13.0 Fluid Transients14.0 In-Service RelocationA dimensionally consistent set of units is used throughout, unless units are specifically called out. For typical pressure piping applications, the pipe demand calculations for some of these load conditions can lead to inconsequential stress levels. Nevertheless, the procedures for estimating pipe stress demands due to these loads are presented for completeness. As designers gain experience using these calculations, they will more efficiently identify which load conditions are relevant to their particular application. Examples of calculations for computing various measures of demand on buried pipes are presented at the end of each section, whenever possible.The designer should appropriately combine the effects of concurrent loads when evaluating the adequacy of the buried pipe. Appendix A: Suggested Acceptance Criteria contains guidance for the evaluation of the buried pipe capacity. The equations used to calculate soil resistance are common to several loading conditions and are provided in Appendix B: Soil Spring Representation.The provisions of this document have been written in permissive language and offer the user a series of options or instructions but do not prescribe a specific course of action. Significant judgment must be applied by the user.1.2 CautionsThe guide does not address the effects of material degradation, such as corrosion and cracks, or damage incurred during transport and installation or by third parties, such as dents or gouges. The guide does not address regulatory compliance, which may impose additional requirements or restrictions on the design. The guide does not address company-specific practices such as right-of-way or minimum spacing for limiting collateral damage.1.3 Notations(EI)eq= equivalent pipe wall stiffness per inch of pipe lengthA = metal cross-section area of pipeA = distance to nearest explosive chargeA f= pipe flow areaB = empirical coefficient of elastic supportC = soil cohesionC = depth of soil cover above pipec L= sonic velocity in liquidC p= seismic compression wave velocity in soilC s= apparent propagation velocity of seismic wavesD = outside diameterD = offset distance between a concentrated surface load and thecenterline of the pipeDMF = dynamic magnification factor of impulsive load from water hammerdP = pressure rise due to rapid valve closure in a pipeline carrying fluidD l= deflection-lag factor for computing pipe ovalityE = modulus of elasticity of pipeE = modulus of soil reactionE C= modulus of pipeline coating elasticityE L= modulus of pipeline lining elasticityF = unbalanced impulsive load along each straight section ofpipeF b= upward force due to buoyancy per unit length of pipeFS = factor of safetyG = gravitational constantG = soil shear modulusH = depth of cover to pipe centerlineH f= drop heighth w= distance between the top of the pipe and the ground watertable (zero if the water table is below the top of the pipe) I = moment of inertia of pipe wallI C= moment of inertia of pipe coatingI L= moment of inertia of pipe liningK = bedding constantK1= coefficient for achieving specific level of conservatism in estimating pipe stresses from blastingK i= empirical coefficients for estimating blast loads (i = 1 to 6) K o= coefficient of earth pressure at restk = coefficient of penetrationL = length of pipe spanL1= transition length for in-service pipeline relocationL b= length of pipe span in the buoyancy zoneL s= support span for in-service pipeline relocationL T= total length of trench for in-service pipeline relocationL v= distance from a valve to an upstream pressure sourceN = factor to normalize explosives to ANFO (94/6) explosive N1 = number of explosive charges in a rowN2 = number of rows of explosive chargesN c= vertical downward soil bearing capacity factorN ch= horizontal soil bearing capacity factor for clayN cv= vertical upward soil bearing capacity factor for clayN q= vertical downward soil bearing capacity factorN qh= horizontal soil bearing capacity factor for sandN qv= vertical upward soil bearing capacity factor for sandN = vertical downward soil bearing capacity factorP = total vertical pressure load on pipep = internal pipe pressureP a= pressure from weight of a falling object distributed over the impact areaPGA = peak ground accelerationPGV = peak ground velocityP max= maximum impact load at the ground surfacep o= atmospheric pressureP p= vertical pressure transmitted to pipe from a concentrated load PPV = peak particle velocity from surface impactP s= concentrated load at the ground surfaceP u= maximum horizontal soil bearing capacityP v= vertical soil trench pressure acting on the top of the pipeP vu= vertical earth load pressure for undisturbed placementconditionsQ u = maximum vertical upward soil bearing capacityR = pipe radiusr = charge standoff distanceR c= radius of curvature associated with pipeline deformation imposed by in-service pipeline relocationR gcg= distance to geometric center of a grid of explosive chargesR gcl= distance to geometric center of a line of explosive chargesr o= equivalent radius of impact objectR s= standoff distanceR w= water buoyancy factors = in-line spacing of explosive chargesS = ASME allowable hoop stressS A= F(1.25S c + 0.25S h)S allow= allowable stress for in-service pipeline relocationS c= allowable stress at ambient temperatureS h= allowable stress at operating temperatureSMYS = specified minimum yield stresst = pipe wall thicknessT1= installation temperatureT2= maximum operating temperaturet c= valve closing timeT u= peak friction force at pipe-soil interfaceU = peak radial ground velocity produced by blastingV = impact velocityV g= peak ground velocityV s= shear wave velocity of near-surface soilsw = total unit weight of pipe with contents, force/lengthW = weight of falling objectW act= actual explosive weightW c= weight of pipe contents per unit lengthW eff= effective explosive weightW p= weight of pipe per unit lengthW s= scaled explosive weightW w= weight of water displaced by pipeX = elevation difference between original pipeline and lowered pipelinex p= penetration depth of falling objecty = deflection at midpoint of pipe due to buoyancyY = ASME B31.1 time-dependent factorZ = elastic modulus of pipe cross-sectionp= horizontal displacement to develop P uqd = vertical displacement to develop Q dqu = vertical displacement to develop Q ut= axial displacement to develop T uv= change in liquid velocity from initial flow rate to zeroy= vertical deflection of pipe from vertical loads= coefficient of thermal expansion= adhesion factor for clay= factor applied to C s in estimating ground strain from wave propagation= angle between the pipeline and a row of explosive charges = interface friction angle for cohesionless soils15 = allowable longitudinal compressive strain associated with15% ovalization of pipe cross sectiona = pipeline axial strainb = pipeline bending strainc= allowable longitudinal (axial or bending) compression strain = total dry unit weight of fill= effective unit weight of soild = dry unit weight of soilw = unit weight of water= wavelength= soil mass densityf= density of fluid carried by the pipe= pipeline stress from blastinga= pipeline axial stressb= through-wall bending stressb= pipeline bending stressbe= factored pipeline bending stress from blastingbf= stress caused by buoyancybs= pipeline bending stress associated with the pipeline spanning between lift or support pointsbt= maximum bending stress due to thermal expansionbw= through-wall bending stressc= longitudinal compressive stressh= hoop stress from internal pressureLC= longitudinal compressive stress caused by a temperature differentiallp = axial stress in pipeline from internal pressurelp= longitudinal stress due to internal pressureu= ultimate strength of pipe steely= yield stress for the pipe steel2.0 Internal Pressure2.1 Sources of Internal PressureThe internal pressure to be used in designing a piping system for liquid, gas, or two-phase (liquid-gas or liquid-vapor) shall be the larger of the following:The maximum operating pressure, or design pressure of the system. Design pressure is the largest pressure achievable in the system during operation, including the pressurereached from credible faulted conditions such as accidental temperature rise, failure ofcontrol devices, operator error, and anticipated over-pressure transients such aswaterhammer in liquid lines.The system hydrostatic or pneumatic test pressure.Any in-service pressure leak test.The internal pressure design of a buried pipe and its corresponding above-ground pipe derive from the same equation.2.2 ExampleA 6-inch seamless carbon steel pipe, ASTM A106 GradeB material, is buried at a chemical process plant. The pipe is designed to the ASME B31.3 Code, with a design pressure of 500 psi and a maximum design temperature of 100o F. The ASME B31.3 allowable stress for the ASTM A106 Grade B at 100o F is S = 20,000 psi. The minimum wall thickness of the buried pipe is:(2-1)t =pD2(SE + pY)where:t= minimum wall thickness required by ASME B31.3, inD= pipe outside diameter = 6.625 inS= ASME B31.3 allowable stress at the design temperature = 20,000 psiE= quality factor = 1.0 for seamless pipep= design pressure, psiY= ASME B31.3 temperature dependent factor = 0.4The calculated thickness t is 0.08 inches. Then add a corrosion allowance and a fabrication tolerance allowance (12.5% for ASTM A106 material) to obtain the minimum required pipe wall thickness. Note that this process for calculating the pipe wall thickness is identical to the design of a corresponding above-ground piping.3.0 Vertical Earth Load3.1 Applied LoadVertical earth load is primarily a consideration for non-operating conditions of buried steel pipe when the pipeline is under no internal pressure. Under most operating conditions, the external earth pressure can be neglected since it is insignificant in comparison to the internal pipepressure. Vertical earth load is an important consideration when designing piping casings used for rail and road crossings.For the purpose of calculating earth loads on a buried pipe, a steel pipe is considered flexible and design procedures for flexible pipes apply. For flexible pipes placed in a trench and covered with backfill, the earth dead load applied to the pipe is the weight of a prism of soil with a width equal to that of the pipe and a height equal to the depth of fill over the pipe, as shown in Figure 3.1-1. This approach is followed for both trench and embankment conditions.For conditions where the pipeline is above the water table, an upper-bound estimate of the pipe pressure resulting from earth dead load can be obtained using Equation 3-1.v P C(3-1)where:P v= earth dead load pressure on the conduit = t otal dry unit weight of fill C= height of fill above top of pipeFor conditions where the pipe is located below the water table, the effect of soil grain buoyancy can be included in the earth load pressure using Equation 3-2. v w w w d P h R C (3-2)where:P v= earth dead load pressure on the conduit d = dry unit weight of backfill C = height of fill above top of pipe h w = height of water above pipe w = unit weight of waterR w= w ater buoyancy factor = 1- 0.33(h w /C )If the pipe is jacked into undisturbed and unsaturated soil instead of being placed in a trench and covered with backfill, then soil friction and cohesion combine to greatly reduce the earth load on the pipe when compared to the prism load. A conservative estimate of the earth load on pipe jacked in undisturbed soil is given as follows [Moser]:2vu v C P P cD(3-3)where:P vu= vertical earth load pressure for undisturbed placement conditionsc = soil cohesion (ranges from 0 psf for loose, dry sand to 1,500 psf for hard clay) D = pipe outer diameter3.2Deflection and Stress Under Soil LoadThe effects of soil loads on pipe stresses and pipe ovality in cross-sections are evaluated in conjunction with surface loads in Section 4.2.3.3 Example 1The earth load pressure on a pipeline buried 10 feet underground, with a total unit weight of 120 lb/ft 3 is:3lb 120(10ft)1,200psf ft v P3.4 Example 2For a pipe buried 10 feet underground with a dry unit weight of 100 lb/ft 3, the earth load pressureis:psf ft ftlbP v 000,1)10)(100(3 If the soil is saturated with the water table reaching the surface, the water pressure alone is:psf ft ftlbP v 624)10)(4.62(3 If soil and water were to act together, the sum of pressure loads would be 1624 lb/ft 2; however, because of the buoyancy of the soil in water, the actual total pressure load is:psf ft ftlbft ft lb P v 1294)10()100()33.01()10)(4.62(333.5 Example 3A 30-inch diameter pipe is jacked 10 feet underground into undisturbed medium clay with a total unit weight of 120 pounds per cubic foot. The cohesion coefficient c is estimated to be 500 psf. Check the vertical earth load pressure using Equations 3-1 and 3.3:3lb 120(10ft)1,200psf ft v P222lb lb 10 ft 12 in lb 12002(500)2800030 in 1 ft ft ft ft vu PSince the vertical earth load pressure must be greater than or equal to zero, there is no verticalearth load on the pipe.3.6 FigureFigure 3.1-1 Soil Prism Above Pipe4.0 Surface Live Loads4.1 AppliedLoadsIn addition to supporting dead loads imposed by earth cover, buried pipes can also be exposed to superimposed concentrated or distributed live loads. Large concentrated loads, such as those caused by truck-wheel loads, railway car, locomotive loads, and aircraft loads at airports are of most practical interest.Depending on the requirements of the design specification, the live-load effect may be based on AASHTO HS-20 truck loads, Cooper E-80 railroad loads or a 180 kip airplane gear assembly load, as indicated in Table 4.1-1. The values of the live load pressure P P are given in psi and include an impact factor F’ = 1.5 to account for bumps and irregularities in the travel surface. Other impact factors are listed in Table 4.1-2.Note: Live-load depends on the depth of cover over the pipe and becomes negligible for HS-20 loads when the earth cover exceeds 8 feet; for E-80 loads when the earth cover exceeds 30 feet; and for airport loads when the earth cover exceeds 24 feet.Live load transferred to pipe, lb/in2Live load transferred to pipe, lb/in2Height of cover, ft HighwayH20*RailwayE80†Airport‡Height ofcover, ftHighwayH20*RailwayE80†Airport‡1 12.50 -- -- 14 § 4.173.062 5.5626.3913.14 16 § 3.472.293 4.1723.6112.28 18 § 2.781.914 2.7818.4011.27 20 § 2.081.535 1.7416.6710.09 22 § 1.911.146 1.3915.638.79 24 § 1.741.057 1.2212.157.85 26 § 1.39 §8 0.6911.116.93 28 § 1.04 §10 §7.646.0930 §0.69§12 §5.564.7635 § § §40§§§ Notes:* Simulates a 20-ton truck traffic load, with impact† Simulates an 80,000 lb/ft railway load, with impact‡ 180,000-pound dual-tandem gear assembly, 26-inch spacing between tires and 66-inch center-to center spacing between fore and aft tires under a rigid pavement 12 inches thick, with impact§ Negligible influence of live load on buried pipeTable 4.1-1 Live LoadsInstallation Surface ConditionHeight of cover, ft HighwaysRailwaysRunways Taxiways, aprons, hardstands, run-up pads0 to 1 1.50 1.75 1.00 1.50 1 to 2 1.35 1.50 1.00 1.35 2 to 3 1.15 1.50 1.00 1.35 Over 3' 1.001.35*1.001.15†Notes:* Refer to data available from American Railway Engineering Association (AREA) † Refer to data available from Federal Aviation Administration (FAA)Table 4.1-2. Impact Factor (F ) versus Height of CoverFor live-loads other than the AASHTO truck, the Cooper rail and the 180 kips aircraft gear assembly loads, the pressure P p applied to the buried pipe by a concentrated surface load P s , without impact, as shown in Figure 4.1-1, can be calculated using Boussinesq’s equation:5.222123C d C P P SP (4-1)where:P p = pressure transmitted to the pipeP s = concentrated load at the surface, above pipe C = depth of soil cover above piped= offset distance from pipe to line of application of surface loadThe pressure P p must be increased for the fluctuating nature of surface line loads by multiplyingby the impact factor F given in Table 4.1-2.When a surcharge load is distributed over the ground surface area near a pipeline, it is possible that the external surcharge may cause lateral or vertical displacement of the soil surrounding the buried pipeline. In this case, additional information, such as a specialized geotechnicalinvestigation, may be needed to determine if the pipeline could be subjected to soil displacement. A detailed investigation may be in order if the distributed surcharge load over an area larger than 10 square feet exceeds the values tabulated below for the weight of material placed or height of soil fill added over the pipeline.500 psf or 5 feet of fill – for pre-1941 pipelines1,000 psf or 10 feet of fill – for pipelines with 12-inch diameters or larger 1,500 psf or 15 feet of fill – for pipelines smaller than 12 inches in diameter4.2 Ovality and Stress4.2.1 OvalityA buried pipe tends to ovalize under the effects of earth and live loads, as illustrated in Figure 4.2-1. The modified Iowa deflection formula may be used to calculate the pipe ovality under earth and live loads:130.061eq D KPy D EI E R(4-2) where:D = pipe outside diameter, inches y = vertical deflection of pipe, inches D l = deflection lag factor (~1.0-1.5)K = bedding constant (~0.1)P = pressure on pipe due to soil load P V plus live load P P , psi R= pipe radius, inches(EI)eq = equivalent pipe wall stiffness per inch of pipe length, in./lb. E ' = modulus of soil reaction, psiThe pipe wall stiffness, (EI)eq , is the sum of the stiffness of the bare pipe, lining (subscript L) andcoating (subscript C). L L C C eq EI EI E I E I (4-3)where:I = 312t t = wall thickness of pipe, lining, or coatingThe modulus of soil reaction E' is a measure of the stiffness of the embedment materialsurrounding the pipe. E' is actually a hybrid modulus, being the product of the modulus of the passive resistance of the soil and the radius of the pipe. Values of E’ vary from close to zero for dumped, loose, fine-grained soil to 3000 psi for highly compacted, coarse-grained soil. Recent studies show that the confined compression modulus can be used in place of E'.4.2.2 Through-Wall BendingUnder the effect of earth and surface loads, the through-wall bending stress in the buried pipe, distributed as shown in Figure 4.2-2, is estimated according to (4-4):。
MATLAB中的数据的压缩与稀疏重建技术解析
MATLAB中的数据的压缩与稀疏重建技术解析引言随着数据量的快速增长和存储需求的提高，数据压缩和稀疏重建成为了一种非常重要的技术。
在MATLAB中，有许多强大的工具和技术可用于数据的压缩和稀疏重建。
本文将对MATLAB中的这些技术进行详细解析。
一、数据压缩1. 无损压缩无损压缩是指压缩后的数据可以完全恢复成原始数据，无任何失真。
MATLAB 中提供了多种无损压缩的方法，如Huffman编码、LZW压缩等。
这些方法通过统计数据中的频率分布来减少数据的冗余性，从而实现数据的压缩。
2. 有损压缩有损压缩是指在压缩数据的同时，对数据进行一定的损失，以减小数据的存储空间。
有损压缩在某些应用中具有重要的作用，如图像和音频压缩等。
在MATLAB中，我们可以使用一些经典的有损压缩算法，例如JPEG、MPEG等。
二、稀疏重建稀疏重建是指利用已知的部分采样数据，通过一定的算法或数学模型来估计原始信号的全部或部分。
在MATLAB中，有许多强大的稀疏重建技术可供使用。
1. 压缩感知压缩感知是一种新兴的稀疏重建技术，它基于信号的稀疏性假设，通过少量的测量来重建信号。
MATLAB中提供了一些方法来实现压缩感知，例如基于稀疏表示的信号重建算法。
2. 压缩采样匹配追踪压缩采样匹配追踪是另一种常用的稀疏重建方法。
它通过将信号表示为稀疏线性组合的方式，从而实现信号的重建。
在MATLAB中，我们可以使用OMP算法等方法来实现压缩采样匹配追踪。
3. 压缩感知重建的优化为了进一步提高压缩感知重建的性能，MATLAB中的优化方法也可以应用于该领域。
例如，我们可以使用凸优化算法，如最小二乘法、半正定规划等，来改进压缩感知重建的精度和速度。
三、案例研究为了进一步说明MATLAB中数据压缩与稀疏重建技术的应用，我们可以通过一个案例研究来进行分析。
假设我们有一个音频文件，需要对其进行压缩和稀疏重建。
我们可以使用MATLAB中的压缩感知算法来实现此目标。
pcl 法向夹角特征点提取 -回复
pcl 法向夹角特征点提取-回复如何使用PCL提取法向夹角特征点。
PCL（Point Cloud Library）是一个开源的点云处理库，它提供了一系列用于点云处理的算法和工具。
在这篇文章中，我们将重点介绍如何使用PCL 来提取法向夹角特征点。
这一步骤通常用于点云的配准和识别，对于许多计算机视觉和机器人应用来说非常重要。
1.点云数据的加载和预处理首先，我们需要加载点云数据并对其进行预处理。
PCL提供了各种API和工具，可以方便地加载和处理点云数据。
我们可以使用PCL的PointCloud 类来表示点云数据，并使用IO库加载各种点云格式，如PCD、PLY等。
加载数据后，我们可以对其进行滤波、降采样等预处理操作，以减少噪声和冗余数据。
2.估计法线在提取法向夹角特征点之前，我们首先需要估计每个点的法线。
法线可以用于描述点云表面上的方向信息，是许多点云处理算法的基础。
PCL提供了多种估计法线的方法，包括基于最小二乘拟合的法线估计方法。
我们可以使用NormalEstimation类来计算每个点的法线，并选择合适的参数来控制估计的精度和计算效率。
3.法向夹角的计算一旦我们估计出每个点的法线，我们就可以开始计算法向夹角。
法向夹角是描述两个法线之间的夹角，用于衡量点云表面的变化和形状特征。
PCL 提供了计算法向夹角的工具，我们可以使用NormalEstimation类的setKSearch方法指定邻域搜索的参数，然后调用computeFeature方法来计算每个点的法向夹角。
4.法向夹角特征点的提取有了计算好的法向夹角，我们就可以开始提取特征点了。
特征点是具有显著法向夹角的点，通常表示点云表面的突变或者关键点。
PCL提供了多种特征点提取的方法，可以根据不同的需求选择合适的算法。
我们可以使用pcl::BuiltinKernel类来指定特征点的搜索半径，并使用pcl::RegionGrowing类来执行特征点提取操作。
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FOREWORD
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The IEC (International Electrotechnical Commission) is a worldwide organization for standardization comprising all
national electrotechnical committees (IEC National Committees). The object of the IEC is to promote international co-
National Committees.
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The documents produced have the form of recommendations for international use and are published in the form of
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matlab 统计孔隙形状 -回复
matlab 统计孔隙形状-回复Matlab是一种强大的计算软件，可用于处理各种统计问题。
在本文中，我们将重点讨论如何使用Matlab进行孔隙形状的统计分析。
首先，我们需要了解什么是孔隙形状。
孔隙形状是指材料或介质中的空间结构，它可以通过多种形状参数来描述。
这些形状参数可以用来评估孔隙的几何特征，如圆度、形状因子、等效直径等。
在Matlab中，有许多函数和工具箱可以帮助我们进行统计分析。
其中一种常用的函数是imfill函数，它可以在图像中填充或关闭物体的孔隙。
该函数可用于处理二值图像，因此在使用之前，我们需要将原始图像转换为二值图像。
首先，让我们加载所需的图像。
可以使用imread函数来读取图像文件，然后使用im2bw函数将图像转换为二值图像。
以下是一些示例代码：读取图像文件image = imread('image.jpg');将图像转换为二值图像binary_image = im2bw(image);接下来，我们可以使用imfill函数填充或关闭图像中的孔隙。
以下是一些示例代码：填充孔隙filled_image = imfill(binary_image, 'holes');填充孔隙后，我们可以使用regionprops函数获取孔隙的形状参数。
此函数可以计算图像中连通对象的相关属性，例如面积、周长、中心位置等。
以下是一些示例代码：获取孔隙的属性props = regionprops(filled_image, 'all');显示孔隙形状参数for i = 1:length(props)fprintf('孔隙d 的面积为 .2f，周长为 .2f，中心位置为(.2f, .2f)\n', i, props(i).Area, props(i).Perimeter, props(i).Centroid);end此外，Matlab还提供了其他功能强大的工具箱，如Image Processing Toolbox、Statistics Toolbox等，可以帮助我们进行更详细的统计分析。
索尼 Alpha 6100 数字单反相机说明书
Key Features24.2MP 2 and incredible image qualityThe Alpha 6100 boasts an impressive APS-C image sensor with approximately 24.2 effective megapixels, the latest BIONZ X™ image processing engine and the same front end LSI as used on Sony’s acclaimed full-frame cameras to deliver outstanding image quality with rich detail and true-to-life color reproduction. Area specific noise reduction results in low noise even at high ISO which ranges from 100 – 32,000 (Expandable up to ISO – 51,200). The design significantly increases readout speed, enabling functionality including 11fps continuous shooting 5, 4K recording 3 with full pixel readout without pixel binning and Full HD 120fps high-speed shooting.Superior autofocus with 4D FOCUS™The Alpha 6100 incorporates Sony’s unrivaled 4D FOCUS™ system for unsurpassed fast autofocus (AF) acquisition time that can lock focus on even the fastest moving subject in as little as 0.02 seconds 1. It also boasts an incredible 425 phase detection and 425 contrast detection AF points that are densely positioned over 84% of the image area, effectively tracking subjects as they move across the frame. Moreover, the Alpha 6600 takes full advantage of its enhanced fast hybrid AF for movies in both HD and 4K 3. Both AF detection accuracy and tracking performance have been boosted.Advanced Real-time Eye AF, humans and animals 6Advanced “Real-time Eye AF 6” employs (Ai) artificial intelligence, including machine learning , to detect and process eye data in real time, resulting in improved accuracy, speed and tracking performance of Eye AF. Eye AF can be employed for humans, animals 6 and when recording movie. With a half press of the shutter button, the camera can automatically detect the eyes of the subject and activate Eye AF in all autofocus modes. When in either AF-C or AF-A mode, eye capture is continuously maintained. Additionally, the preferred eye (right or left) of your subject can be selected as the focus point. Choices include Auto/Right Eye/Left Eye, and a Switch Right/Left Eye function is assignable to a custom function or the touchscreen panel.Real-time Tracking Autofocus“Real-time Tracking” is a state-of-the-art feature that utilizes a special object recognition algorithm that processes color, subject distance (depth), brightness (pattern) as spatial information, plus AI (Artificial Intelligence with machine learning) information including face and eye location, ensuring that all subjects can be captured with extreme accuracy and precision. This can be activated by a simple half press of the shutter button, or can be assigned to a custom function as well. The subject to be tracked can also be specified by touching it on the monitor when the Touch Tracking function is engaged.Real-time Eye AF for animals 6Advanced AI-based subject recognition technology now allows fast, precise, automatic detection and tracking of animal 6 eyes. This new capability can vastly increase success rates when photographing animals in a variety of settings or pets at home. Real-time Eye AF animal mode can be initiated either by pressing an assigned custom button or by half-pressing the shutter button.16-bit processing and 14-bit RAW outputImage sensor output is processed in 16-bit form by the front-end LSI and BIONZ X image processing engine before being output as compressed or uncompressed 14-bit RAW files that have smoother, more natural gradations for higher overall image quality. 14-bit RAW output is available even when shooting in silent or continuous mode.Up to 11fps 5 at 24.2MP with AE/AF trackingILCE-6100/BAlpha 6100 APS-C Mirrorless Interchangeable-LensCameraThe Alpha 6100 include a 24.2MP 2 Exmor™ CMOS image sensor, the latest BIONZ X™ image processor and a front-end LSI as implemented in Sony’s full-frame cameras, which combine to deliver all-round enhancements in image quality and performance across all areas of photo and video capture.The Alpha 6100 has been designed to allow for high resolution, continuous shooting at high frame rates. It features a front-end LSI that works with the image sensor, BIONZ X image processing engine and a newly designed shutter mechanism with ‘braking feature’ to enable continuous shooting at impressive speeds up to 11fps5 with continuous autofocus and auto-exposure tracking at full 24.2MP resolution while utilizing the mechanical shutter, and up to 8 fps5 with full AF/AE tracking while silent shooting.4K movie3 w/ full pixel readout, no pixel binningThe Alpha 6100 offers internal 4K (QFHD: 3840 x 2160) recording3 in Super 35mm format with full pixel readout and no pixel binning at 2.4x oversampling4 (6K equivalent) for the ultimate 4K footage with exceptional detail and depth. Additional the Alpha 6100 has the ability to record Full HD at 120 fps for up to 5x slow motion HD video7 and a mic jack with XLR compatibility via the MI shoe, focus peaking, clean HDMI output and much more.Touch Tracking for moviesTouch Tracking is beneficial for movie recording. Touch the subject to be tracked on the monitor, and the Real-time Tracking function will then process color, pattern (brightness), distance (depth), and face information to precisely and smoothly track the selected subject at the specified sensitivity and speed. It is also possible to half-press the shutter button or press the AF ON button while shooting to achieve fast focus (AF-S). This can be an advantage for weddingsor documentaries, where there is only one chance to capture a scene. In such cases the focus area selected in advance is applied.180-degree tiltable LCD touch screen for self-recordingThe fully tiltable (180-degree), 3” (3.0-type) LCD flip screen with 921k-dots of high-resolution allows for simple and effective selfie-style shooting for both still image and video capture. Utilizing this capability, vloggers will be able to check and monitor composition throughout their entire creative process. The LCD screen is also equipped with touch functionality, with options for Touch Pad, Touch Focus, Touch Shutter and new Touch Tracking which quickly activates “Real-time Tracking” through the touch screen.Wi-Fi®/NFC™/QR code for easy file transfer and remote control8Easily connect with NFC or QR code (for non-NFC devices) to smartphones or tablets with the built-in Wi-Fi® and Sony’s PlayMemories Mobile™ application available for free on the Android™ and iOS platforms8. Control your camera or transfer files to your device for fast and easy sharing without the need of a computer. It also supports Sony’s growing range of PlayMemories Camera Apps™, which add a variety of creative capabilities to the camera. Then when you’re done, you can use the free software to sort and manage your stills and video with PlayMemories Home™ or edit your RAW file with either Sony’s Image Data Converter or Capture One Express (for Sony). Make it your own with easy button and dial customizationMake operation more intuitive, quick and easy. You can assign any of 89 functions to any of 8 custom buttons. Independent function sets can be assigned for stills, movies, and playback. “My Dial” allows for frequently-used functions to be assigned to the control dial and control wheel. The My Menu function allows up to 30 frequently-used menu items to be registered. They can be re-ordered by frequency of use, and little-used items can be deleted, allowing the user to create a menu that reflects their usage patterns.Interval Recording7 for time-lapseInterval shooting7 (continuous shooting with a set interval) is possible to create time-lapse movies, without requiring an app or external interferometer. Shooting interval can be set to anywhere between 1 second and 60 seconds, and the number of shots to anywhere from 1 to 9999. AE tracking sensitivity can be set to ”High”, “Mid” or “Low” during interval shooting to control your exposure and silent shooting can be activated to reduce shutter vibration. To extend shooting periods, a mobile battery can be used while the internal battery remains in the camera. Still images shot can be edited into a time-lapse movie on a computer with the latest version of Imaging Edge software (Remote/Viewer/Edit) and PlayMemories Home.Slow and quick motion7Slow and quick motion7 offers an almost endless variety of creative ways to express the passage of time. Frame rates from 1 fps to 120fps (100fps) can be selected in eight steps for full HD up to 50 Mbps; 60x quick motion/5x slow in NTSC and 50x quick motion/4x slow in PAL.4K movie transfer to smartphone8By using the newly introduced smartphone app Imaging Edge Mobile, high-bitrate movies including 4K can be transferred to smartphones (Probability of transfer / playback depends on the performance of the smartphone). Refer to the product information for Imaging Edge Mobile for detailsImaging Edge desktop applicationsTo support an efficient, high speed, connected professional workflow, Sony provides “Imaging Edge” desktop applications. Use "Remote" to control and monitor shooting live on your PC screen; "Viewer" to quickly preview, rate, and select photos from large image libraries; and "Edit" to develop RAW data into high-quality photos for delivery. Get the best from Sony RAW files, and manage your productions more efficiently. To maximize convenience in image transfer, when utilizing the latest version of Sony’s Imaging Edge Mobile™ application, the camera can now transfer images to a connected smartphone even if the camera’s power is set to OFF. Refer to the download page for details: /disoft/d/Specifications1. Based on Sony research, CIPA-guideline-compliant internal measurement with an E 18-135mm F3.5-5.6 OSS lens mounted, Pre-AF off and viewfinder in use.2. Approximately, effective megapixels3. 3840×2160 pixels. A Class 10 or higher SDHC/SDXC memory card is required to record movies in the XAVC S format. UHS-I (U3) SDHC/SDXC card is required for 100Mbps4. Standard ISO 100 up to ISO 32000 expandable to ISO 100 to ISO 51200for still images5. High-speed continuous shooting is available at up to approx. 11fps in “Hi+” continuous shooting mode and up to approx. 8fps in “Hi” continuous shooting mode. Maximum fps will depend on camera settings.6. Accurate focus may not be achieved with certain subjects in certain situations.. Real-time Eye AF for Animals supports still images only and cannot be used in combination with tracking. Does not work with some types of animal.7. Wi-Fi does not work during interval shooting8. Imaging Edge Mobile Ver. 7.2 or later is required© 2019 Sony Electronics Inc. All rights reserved. Reproduction in whole or in part without written permission is prohibited. Sony is not responsible for typographical and photographic errors. Features and specifications are subject to change without notice. Sony, G Master, the Alpha logo and the Sony logo are trademark of Sony Corporation. All other trademarks are trademarks of their respective owners.。
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X := fDk E
:
2
k 2 ZZ
2 ZZd g
E : f 7! f ( + )
Dk : f 7! j det sjk=2f (sk ) is the dilation operator. A system X L2 (IRd ) is a fundamental tight frame with frame bound 1 if the map T : L2(IRd ) ! `2(X ) : f 7! (hf xi)x2X is unitary (but not necessarily onto: a tight frame with frame bound 1 whose corresponding T is onto is necessarily orthonormal). In what follows, all systems that we treat are a ne and fundamental, and all tight frames that are considered have frame bound 1, hence \a tight frame" should always be understood as \a fundamental tight a ne frame with frame bound 1". A tight frame can be used for the atomic decompositions of functions exactly in the same way orthonormal bases are used, i.e., T : f 7! T f
amos@
Zuowei Shen
Department of Mathematics National University of Singapore 10 Kent Ridge Crescent Singapore 119260
matzuows@leonis.nus.sg
February 1996 ABSTRACT The theory of RS2] is applied to yield compactly supported tight a ne frames (wavelets) in L2(IRd ) from box splines. The wavelets obtained are smooth piecewisepolynomials on a simple mesh furthermore, they exhibit a wealth of symmetries, and have a relatively small support. The number of \mother wavelets", however, increases with the increase of the required smoothness. Two bivariate constructions, of potential practical value, are highlighted. In both, the wavelets are derived from four-direction mesh box splines that are re nable with respect 1 to the dilation matrix 1 ;1 . 1 AMS (MOS) Subject Classi cations: Primary 42C15 41A15 41A63, Secondary 42C30 Key Words: a ne systems, box splines, four-direction mesh, frames, tight frames, multiresolution analysis, wavelets.
Compactly supported tiБайду номын сангаасht a ne spline frames in L2 (IRd )
Amos Ron and Zuowei Shen
1. Introduction
Given a nite set L2 (IRd ), and a dilation matrix s, the a ne system generated by is de ned as the collection (1:1) where is the shift operator and
Compactly supported tight a ne spline frames in L2 (IRd ) Amos Ron
Computer Science Department University of Wisconsin-Madison 1210 West Dayton Street Madison, Wisconsin 53706, USA
Let L2 := L2 (IR2 ). Let h be the re nement mask of a Daubechies' scaling function , D3] (whose shifts are known to be orthonormal), and let be the corresponding wavelet. De ne the bivariate mask (!1 !2) := h(!1): Given a dilation matrix s, a bivariate scaling function (or distribution) can then be de ned by 1 b : ! 7! Y (s ;j !): Cohen and Daubechies employed in CD] two di erent dilation matrices: 1 (1:2) s := 1 ;1 s1 := 1 ;1 1 1 1 and obtained therefore two di erent scaling functions, say and 1 , respectively. They observed essential di erences between the two so-obtained functions. The matrix s satis es s2 = 2I , and therefore the resulted is clearly the tensor product (referred to as \separable" in CD]) (x) = (x2) (x1 ; x2) and therefore the shifts of are necessarily orthonormal. Furthermore, the standard wavelet construction then yields the wavelet (x) = (x2) (x1 ; x2 ): While the re nable function is separable, the re nable function 1 and the wavelet constructed from it are not separable in any sense. Nonetheless, it is proved in CD] that the shifts of 1 are orthonormal. It is further proved in CD] that, unfortunately, 1 cannot be C 1 , regardless of the order of the univariate scaling function which is used. Therefore, it is necessary to develop some other algorithms to construct nonseparable compactly supported tight frames with high smoothness. It will not be entirely correct to say that the CD] constructions and tensor product constructions comprise all known multivariate a ne tight frames: according to CS], tight frames can be constructed by appending to some of their translates (=:oversampling) that, of course, only increases the number of elements in each of the above constructions, while preserving any de ciences (such as lack of symmetries and low smoothness in the non-separable case, and parallelogram supports in the separable case) that the orthonormal system may have had. The theory established in RS2], however, makes the construction of useful simple nonseparable compactly supported tight frames with high smoothness and a variety of symmetries an easy task. In fact, one can essentially construct tight frames with the aid of the shifts of any re nable function, and therefore it is possible to impose a simple structure on the wavelets by selecting a re nable function with such desired structure. Indeed, we constructed in RS2], for every positive integer m, a tight frame for L2(IR) that is generated by m wavelets, each of which is a spline of degree m ; 1, support 0 m], and smoothness C m;2 . Further, all knots of the spline-wavelets are half-integers, and each spline is either symmetric or anti-symmetric. (The case m = 4 of this construction is discussed in x4). 2