超大规模集成电路第八次作业2016秋,段成华

Assignment 81.Access relevant reference books or technical data books and give accuratedefinitions for the following timing parameters:(1)design entity,(2)signal driver,(3)transaction,(4)event,(5)time queue,(6)delta delay,(7)simulation time,(8)simulation cycle,(9)inertial time,(10)transport time.(1)design entity: In VHDL a given logic circuit represented as a design entity. Adesign entity, in return , consists of two different types of description: the interface description and one or more architectural bodies. The interface description declares the entity and describes its inputs and outputs.(2)signal driver: If a process contains one or more signal assignment statementthat schedule future values for some signal X, the VHDL simulator creates a single value holder called a signal driver.(3)transaction:A pair consisting of a value and time. The value part represents afuture value of the driver; the time part represents the time at which the value part becomes the current value of driver.(4)event: It’s a kind of signal property and presents signal jump. Such asif(clk'event and clk='1).(5)time queue: It’s used to keep some signal transactions in the simulator. Timequeue entries are represented as a two-tuple of the form(SN,V), where SN is a signal name and V is the value the signal is scheduled to assume at the scheduled time. Each time queue entry is called a signal transaction.(6)delta delay: A period of time greater than 0, but less than any standard time unitno number of delta delay added together can cause simulation time to advance.(7)simulation time: The elapsed time in standard time units during simulation.(8)simulation cycle: Every time simulation time advances, a simulation cycleoccurs, which we now define more formally. The execution of a model consists of an initialization phase followed by the repetitive execution of processes in the process network. Each repetition is said to be a simulation cycle.(9)inertial time: Example: Z <= I after 10ns; The signal propagation will takeplace if and only if input I persists at a given level for 10ns-the amount of time specified in the after clause.(10)transport time: Z <= transport I after 10ns; All changes on I will propagate toZ, regardless of how long the value of I stays at the new level.2.Construct VHDL models for 74-139 dual 2-to-4-line decoders using threedescription types, i.e., behavioral, dataflow and structural descriptions. Synthesize and simulate these models respectively in the environment of Xilinx ISE with the ModelSim simulator integrated. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.Logic schematic of 74-139:Function table of one decoder of 74-139:（1-- Company:-- Engineer:-- Create Date: 21:14:09 12/02/2016-- Design Name:-- Module Name: deceoder_beh - Behavioral -- Project Name:-- Target Devices:-- Tool versions:-- Description:-- Dependencies:-- Revision:-- Revision 0.01 - File Created-- Additional Comments:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity deceoder_beh isPort ( G1,G2 : in std_logic;A : in std_logic_vector(1 downto 0);B : in std_logic_vector(1 downto 0);Y1 : out std_logic_vector(3 downto 0);Y2 : out std_logic_vector(3 downto 0));end deceoder_beh;architecture Behavioral of deceoder_beh isbeginde1: process (A, G1)beginif G1 = '1' theny1 <= "1111"; -- sequential statementelsecase A iswhen "00" => Y1 <= "1110";when "01" => Y1 <= "1101";when "10" => Y1 <= "1011";when "11" => Y1 <= "0111";when others => Y1 <= "1111";end case;end if;end process;de2: process (B, G2)beginif G2 = '1' thenY2 <= "1111"; -- sequential statementelsecase B iswhen "00" => Y2 <= "1110";when "01" => Y2 <= "1101";when "10" => Y2 <= "1011";when "11" => Y2 <= "0111";when others => Y2 <= "1111";end case;end if;end process;end Behavioral;TestBench代码如下：-- Company:-- Engineer:-- Create Date: 22:25:59 12/02/2016-- Design Name:-- Module Name: D:/ISE11.1_example/decoder/deconder_beh_tb.vhd-- Project Name: decoder-- Target Device:-- Tool versions:-- Description:-- VHDL Test Bench Created by ISE for module: deceoder_beh-- Dependencies:-- Revision:-- Revision 0.01 - File Created-- Additional Comments:-- Notes:-- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends-- that these types always be used for the top-level I/O of a design in order-- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model.LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY deconder_beh_tb ISEND deconder_beh_tb;ARCHITECTURE behavior OF deconder_beh_tb IS-- Component Declaration for the Unit Under Test (UUT)COMPONENT deceoder_behPORT(G1 : IN std_logic;G2 : IN std_logic;A : IN std_logic_vector(1 downto 0);B : IN std_logic_vector(1 downto 0);Y1 : OUT std_logic_vector(3 downto 0);Y2 : OUT std_logic_vector(3 downto 0));END COMPONENT;--Inputssignal G1 : std_logic := '0';signal G2 : std_logic := '0';signal A : std_logic_vector(1 downto 0) := (others => '0');signal B : std_logic_vector(1 downto 0) := (others => '0');--Outputssignal Y1 : std_logic_vector(3 downto 0);signal Y2 : std_logic_vector(3 downto 0);BEGIN-- Instantiate the Unit Under Test (UUT)uut: deceoder_beh PORT MAP (G1 => G1,G2 => G2,A => A,B => B,Y1 => Y1,Y2 => Y2);-- Stimulus processstim_proc: processbegin-- insert stimulus hereG1 <='1';WAIT FOR 100 ns;G1 <='0';A <= "00";B <= "00";-- --------------------------------------- ------------- Current Time: 200nsWAIT FOR 100 ns;G1 <='0';A <= "01";B <= "01";-- --------------------------------------- ------------- Current Time: 300nsWAIT FOR 100 ns;G1 <='0';A <= "10";B <= "10";-- --------------------------------------- ------------- Current Time: 400nsWAIT FOR 100 ns;G1 <='0';a <= "11";b <= "11";WAIT FOR 100 ns;end process;END;测试波形如下：可以看到当G1=0和G2=0可以正常的译码，当G1=1和G2=1，则Y1和Y2都输出”1111”。