8255特性

8255 Characteristics

(1) a parallel input / output of the LSI chip, multi-purpose I / O devices, can be used as the CPU and peripheral bus interfaces.

, A group including the A I and C I (H 4, PC4 ~ PC7), B group including B I and C I (low 4, PC0 ~ PC3). A group can be set to the basic I / O port, flash control (STROBE) of I / O flash controlled, two-way I/O3 models; B group can only be set to the basic I / O or

flash-control I / O in two modes, which are controlled entirely by the operating mode control register the word decision.

8255 pin function

RESET: Reset input line, when the external input to the high, all internal registers (including the control register) are clear, all I / O port are input into the way home.

CS: Chip Select signal line, when the input pin is low, that is, when / CS = 0 indicates that the chip is selected, 8255 to allow CPU to communicate with; / CS = 1, the 8255 can not be done with the CPU data .

RD: Reading signal line, when the input pin is low, that is, / RD = 0 and / CS = 0 when the 8255 data bus allows the CPU to send data or status information, that is, to read CPU information from the 8255 or data.

WR: write signal, when the input pin is low, that is, when / WR = 0 and / CS = 0 when the data allow the CPU to write 8255 words or control.

D0 ~ D7: three-state bi-directional data bus 8255 and the CPU data transmission channel, when the CPU implementation of input and output directions, through its data to achieve 8-bit read / write operation, the control word and status information is also transmitted through the data bus .

PA0 ~ PA7: port A input and output lines, an 8-bit data output latch / buffer and one 8-bit data input latch.

PB0 ~ PB7: Port B input and output lines, an 8-bit I / O latch, an 8-bit input and output buffers.

PC0 ~ PC7: port C input and output lines, an 8-bit data output latch / buffer and one 8-bit data input buffer. Port C can be set through the work and is divided into two 4-bit ports, each of the four-port contains a 4-bit latch, respectively, with the port A and port B use as a control signal or status signal output input port. '

A0, A1: address select lines used to select 8255 of the PA population, PB I, PC I and the control register.

When A1 = 0, A0 = 0 when, PA I was chosen;

When A1 = 0, A0 = 1 when, PB I been chosen;

When A1 = 1, A0 = 0 when, PC I was chosen;

When A1 = 1.A0 = 1 when the selected control register.

8255特性

(1)一个并行输入/输出的LSI芯片,多功能的I/O器件,可作为CPU总线与外围的接口.

(2)具有24个可编程设置的I/O口,即使3组8位的I/O口为PA口,PB口和PC口.它们又可分为两组12位的I/O口,A组包括A口及C口(高4位,PC4~PC7),B组包括B口及C口(低4位,PC0~PC3).A组可设置为基本的I/O口,闪控(STROBE)的I/O闪控式,双向I/O3种模式;B