超簿氧化层的击穿

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栅氧化层临界击穿电场

栅氧化层临界击穿电场
栅氧化层临界击穿电场的数值是由多种因素决定的，包括栅氧
化层的厚度、材料特性、温度等。

下面我将从不同角度对这些因素
进行分析。

首先，栅氧化层的厚度对临界击穿电场有影响。

一般来说，栅
氧化层越薄，临界击穿电场越低。

这是因为薄的栅氧化层更容易形
成电场集中，增加击穿的可能性。

其次，栅氧化层的材料特性也是影响临界击穿电场的重要因素。

不同材料的栅氧化层具有不同的击穿特性。

例如，硅二氧化物
（SiO2）是常用的栅氧化层材料，具有较高的击穿电场强度。

而硅
氮化物（Si3N4）等其他材料则具有更高的击穿电场强度。

此外，温度也会对栅氧化层临界击穿电场产生影响。

一般来说，随着温度升高，栅氧化层的击穿电场强度会降低。

这是因为温度升
高会增加材料的载流子浓度，导致击穿更容易发生。

除了上述因素，栅氧化层的制备工艺、氧化层的质量等也会对
临界击穿电场产生影响。

制备工艺的不同可能导致栅氧化层中的缺
陷数量和分布不同，从而影响击穿电场强度。

总结来说，栅氧化层临界击穿电场是由栅氧化层厚度、材料特性、温度以及制备工艺等多种因素综合作用的结果。

了解和控制这些因素对于保证栅氧化层的可靠性和稳定性非常重要。

栅氧化层中的隧穿机制

栅氧化层中的隧穿机制
栅氧化层中的隧穿机制是指在栅氧化层中，电子可以通过隧穿效应穿越栅氧化层的现象。

在MOS（金属-氧化物-半导体）结构中，栅氧化层位于金属
栅和半导体衬底之间，起着电子绝缘层的作用。

栅氧化层的厚度通常在几纳米到十几纳米范围内，非常薄。

当施加正向偏压于金属栅时，栅氧化层中会形成电场，这个电场会引起半导体衬底中的电子受到吸引，靠近栅氧化层。

当电场变得足够强时，电子具有足够的能量，可以通过隧穿效应穿越栅氧化层进入金属栅中。

隧穿机制是一种量子力学现象，栅氧化层中的隧穿概率与栅氧化层的厚度、电场强度、电子能量等因素有关。

隧穿概率通常是指单位时间内穿越栅氧化层的电子数目。

栅氧化层中的隧穿机制在MOS器件的工作中起着重要的作用。

通过控制栅氧化层的厚度和电场强度，可以调节隧穿效应的程度，从而影响器件的电流特性和性能。

隧穿电流的大小和特性决定了MOS器件的可靠性和功耗等方面的表现。

不同工艺超薄栅氧化层的抗击穿特性

＠２００２中国电子学台
维普资讯
１期
韩德栋等：不同工艺超薄措氧化层的抗击穿特性
对应的
电压）．
即为击穿电压（理论上是，，一蓝线当
小．这是因为衬底中的电子能量较低，通过隧道贯穿
量实验研究了注Ｆ、Ｎ、注Ｎ后注Ｆ超薄橱氧注先
化层的击穿特性以及它们之间的关系．结果表明，在栅介质中引入适量的Ｆ或Ｎ都可以改善橱介质的质量，高器件的抗击穿能力．提通过比较发现，Ｎ注薄橱介质的抗击穿能力比注Ｆ薄橱介质强．对进这
橱氧化层的击穿问题已经成为阻碍集成电路进一步本实验所采用的样品为ＡｌＮ型ＭＯＳ电容，栅
制作在１７．Ｎ・ｃｎ型（０）ｉ底上．．～２３ｍ，１０Ｓ衬经
９００ ℃干氧栅氧化，氧化后在９０Ｎ气氛中进行退０℃ 火，容面积分别为１８４１～、．０ × １～、电．２ × ０８３２０５０ ×１Ｉｃ．介质中Ｆ的引入是通过橱干氧过．６０３ｍ。栅程中同时加ＮＦ氧化而实现的，氧化后在９０ｓ栅０℃
近几年来，关薄橱氧化层击穿特性以及含Ｆ、有Ｎ等橱介质ＭＯＳ器件的研究国内外已有很多报
道＿，有关注Ｆ、Ｎ、注Ｎ后注Ｆ超薄橱氧ｌ但］注先
化层的抗击穿特性的研究却很少报道．文通过大本

Flash存储器的技术和发展

湘潭大学论文题目：关于Flash存储器的技术和发展学院：材料与光电物理学院专业：微电子学学号：***********名：***完成日期：2014.2.24目录1引言 (4)2Flash 存储器的基本工作原理 (4)3 Flash存储器的编程机制 (5)3.1 沟道热电子注入(CHE) (5)3.2 F-N隧穿效应(F-NTunneling) (6)4 Flash存储器的单元结构 (6)5 Flash存储器的可靠性 (7)5.1 CHE编程条件下的可靠性机制 (8)5.2 隧道氧化层高场应力下的可靠性机制 (8)6 Flash存储器的发展现状和未来趋势 (9)参考文献: (10)关于Flash存储器的技术和发展摘要:Flash 存储器是在20世纪80年代末逐渐发展起来的一种新型半导体不挥发性存储器,它具有结构简单、高密度、低成本、高可靠性和在系统的电可擦除性等优点, 是当今半导体存储器市场中发展最为迅速的一种存储器。

文章对F lash 存储器的发展历史和工作机理、单元结构与阵列结构、可靠性、世界发展的现状和未来趋势等进行了深入的探讨。

关键词:半导体存储器;不挥发性存储器; Flash存储器; ETOX结构About Flash Memory Technology and Its DevelopmentAbstract: As a new non -volatile semiconductor memory introduced by Masuoka in 1984, flash memory has a number of advantages, such as simple structure, high integration density, low cost, and high reliability, and it is widely used in mobile phone, digital camer a, PCBIOS, DVD player, and soon. Its evolution, programming mechanism, cell structure, array structure, reliability are described, and its developing trend in the future is dis cussed.Key words: Semico nduct or memory; Flash memor y; Non-volatile memory ; ETOX1引言随着微电子技术和计算机技术的迅速发展, 我们正迈向一个信息社会。

超薄栅氧化层击穿：缺陷产生的物理模型和寿命预测

超薄栅氧化层击穿：缺陷产生的物理模型和寿命预测
今天的内容不少，不过有过去重复的内容，比如超薄氧化层击穿的几种模型，前面也有提到过，这次角度不同，大家可以进一步深化理解。

缺陷产生的物理模型：氢释放模型，阳极空穴注入模型，热化学模型
氢释放模型发展过程：
氢释放模型示意图：即热载流子作用到Si-O键上，打破弱键，使
硅多余一个电子没有原子与之发生公假配对，同时氧与氢结合，导致氧出现多余电子，两者都相当于SIO2的缺陷。

氢释放模型也可以用如下图表示
阳极空穴注入（AHI）模型--1/E模型
阳极空穴注入模型示意图：高能空穴注入导致SIO2键断裂，形成缺陷
阳极空穴注入模型有很多缺点和不足:
“热化学”模型-E-模型
热化学模型示意图：Si-Si键的存在，以及Si-O键的极性
Si-O键有极性，在外电场下键能改变
其它几种模型简要说明：
E-模型与1/E模型比较：高低场下各自有符合较好的地方
氧化层击穿标准：
临界陷阱密度：
寿命预测模型：
几种Qbd对比：
超薄氧化层击穿的渐进过程：
应力条件对击穿时间的影响：应力越低，击穿时间越长，这个是可以预见的。

击穿后的图片：
软击穿对Gm和VT变化量影响比较小
低应力对Ids影响也比较小
好了，今天的内容到这里就差不多了，内容不少，不过看的多，定性认知是主要，不太需要定量计算，容易理解，也容易明白，有个概念就可以了，以后有机会用的时候再拿出来翻翻也就差不多了。

氧化层击穿原理ppt课件

在未进行温度偏压（BT）处理前， Na+大多数集中在SiO2与金属界面靠近金属的陷阱内，对硅表面性质影响不大。
在正BT处理后（温度一般为150~200℃），这些Na+可以被激活而离开陷阱，在SiO2网络的孔洞之间向Si-SiO2界面运动，绝大多数集中在SiSiO2界面在靠近硅一侧的SiO2层中，将在Si表面感应出负电荷，使双极型器件出现表面沟道或引起击穿电压的蠕变，使MOS器件的阈值电压不稳定。此外，还会导致SiO2的过早击穿，降低SiO2层的介电强度。
26 2005-4
3. 氧化硅的击穿模型
（4）空穴电流的产生
电子到达阳极时将能量释放给界面的晶格，破坏Si-O键，产生界面态。部分电子将获得的能量释放给阳极界面一侧硅中价带的电子，使其激发到导带底，因此产生的“热”空穴在电场作用下又隧穿进入氧化层。
（5）陷阱对载流子的俘获和释放
在氧化硅中输运的电子和空穴被不断产生的陷阱和已有的陷阱俘获，形成陷阱电荷。而陷阱内的电子或空穴也可能被输运载流子碰撞而释放出来。
任娜-weekly-report-20121110 氧化层击穿原理研究
1
Outline
1. 氧化硅的结构和性质 2. Si-SiO2系统 3. 氧化硅的击穿模型 4. 检测氧化硅质量的方法
2 2005-4
1. 氧化硅的结构和性质
（1）二氧化硅的结构
二氧化硅薄膜具有无定形玻璃状结构，基本单元是一个由Si-O原子组成的正四面体，硅原子位于正四面体的中心，氧原子位于四个角顶，两个相邻的四面体通过一个桥键氧原子连接起来构成无规则排列的二维网络结构。
且为简单起见暂时忽略ms20精选编辑ppt氧化硅的击穿模型图12an衬底积累bn衬底反型cp衬底反型dp衬底积累21精选编辑ppt氧化硅的击穿模型2氧化硅中电子的遂穿以npolysio2si结构为例硅与氧化硅之间形成的势垒高度b325v在一定栅压vg下当加在mos电容氧化层上的电压voxb时电子穿过三角形势垒注入到sio2的导带中形成可测量的fowlernordheim隧穿电流voxb时由阴极发射的电子穿过梯形势垒直接隧穿如果氧化层厚度5nm隧穿几率很小直接隧穿电流可以忽略不计

超薄氧化层制备及其可靠性研究

Ａｂｔａｔｎｔｓｐａｒｈｒｎｉｅｏｔａｔｉｓｒｃ：Ｉｈｉｐｅ，ｔｅｐｉｃｐｌｆｕｌｒｈｎｏｘｉｅｓｂｅａｄ ’ ｒｋｄｏｎｗａｉｐｙｉｔｏｗｓｓｍｌｎｒｄｕｃｄｈｅ，ｔｅ
８０、Ｏ，ＤＣＥ、Ｎ火条件下，可制备５ｍ氧化层，其可靠性能为：最大击穿电压４．Ｖ，平０℃ ／退ｎ９１
均击穿电压７１．ｖ，击穿电场ｌ．２６６ＭＶ・ｍ一ｃ，早期失效率３８％，击穿电荷量ＱＤ１ｃ‘ｍ一点可．５Ｂ＞ｃ５
ｔｎ￣５ｈｅ４ｍｎｍｉｅｗｉｈｌｓｈｎ２０ｕｎｆｒｉｙａｅｐｒｐａｅ／Ｄｒｘｉａｉｎｔｅｐｒ — ｏｘｄｔｅｓｔａ．％ｉｏｍｔｒｅｒｄｂｙＮＯｙｏｄｔｏｎｉｈｅｔｍｅａｔｒｆ８５ｕｅｏ０℃ ａｄ９０ｎ０℃ ；ｎｔｅｐｏｅｓｏＩｈｒｃｓｆＲＣＡａｈｉｇ，ｘｃｓｉｅｙｈｉｈｃｎｔｎｆＮＨＨ，ｉｈｗｓｎｅｅｓｖｌｇｏｅｔｏ ’ ＯｎｔｅＡＰＭａｓｈｍａｅａｄｒｕｇｎｅｓｏｉｉｏｎｓｆｃａｈｅｅｕｌｎｉｔａ —ｎｌｄａｉｎｄｃｕｅｔｅｄａｇｎｏｈｓｆｓｌｃｕｒａｅ．ｎｄｔｎｒｓｔｉｎｉｉｌｉｖａｉｔｏｎａ
第１ｉ卷，３期第
Ｖｏｌ１１ＮＯ３
电
子

超薄HfO2高K栅介质中电场依赖的时变击穿(TDDB)特性

Stress Electric-Field Dependent TDDBCharacteristics of Ultra-Thin HfN/HfO2 GateStack with 0.9 nm EOTHong Yang, Ning Sa, Jinfeng Kang*Institute of Microelectronics, Peking University, Beijing 100871, P. R. China*Email: kangjf@AbstractIn this paper, ultra thin CVD HfO2-gated nMOS capacitors (nMOSCs) withEOT~0.9 nm were fabricated. The time-dependent dielectric breakdown (TDDB)characteristics of the 0.9 nm HfO2 gate stack were studied under constant voltagestress (CVS). Area scaling consistent with Weibull statistics as in SiO2 was observedin the gate stack, demonstrating that intrinsic effects dominate time-dependentdielectric breakdown (TDDB) characteristics of the ultra thin HfN/HfO2 gate stack.For the first time, different TDDB characteristics under gate injection with low andhigh CVS were demonstrated in the sub-1 nm EOT HfO2 gated devices. The resultsshow that interfacial layer initiated breakdown dominates the TDDB under low CVSand HfO2 bulk initiated breakdown under high CVS. A new breakdown model isproposed to explain the new demonstrated TDDB characteristics.Keywords: High K Gate Dielectric, Reliability, Time-Dependent DielectricBreakdown (TDDB), Constant Voltage Stress (CVS).1IntroductionHigh-K gate dielectric will be required in the advanced CMOS devices to provide sufficient gate control with scaled equivalent oxide thickness (EOT) [1-6]. The reliability issues such as time-dependent dielectric breakdown (TDDB) under both gate injection and substrate injection need to be addressed when high K gate dielectrics are implemented in Si-CMOS technology [1-5]. It has been shown that there is an unavoidable interfacial layer (IL) between high-K bulk and Si substrates [6] and two possible breakdown mechanisms such as bulk initiated and IL initiated breakdown have been proposed [2-4]. However, there are few papers to address the reliability of sub-1 nm EOT high K gate dielectrics [3]. Meanwhile, there are inconsistent pictures for the breakdown of high K gate stack such as IL initiated [2,7] or bulk initiated [4] breakdown having reported under gate injection. In this paper, nMOS capacitors with 0.9 nm EOT HfN/HfO2 gate stack were fabricated. The TDDB characteristics of theHfO2 gate stack of the 0.9 nm EOT devices were studied under gate injection in order to understand the breakdown mechanism of the high K gate stack. For gate injection IL initiated breakdown under low CVS and bulk initiated breakdown under high CVS were reported for the first time. A new breakdown model is proposed to elucidate the TDDB characteristics measured in the sub-1 nm HfO2 gated devices under gate injection CVS.2 ExperimentsThe nMOS capacitors (nMOSC) were fabricated on p-Si (100) substrates with 4~8 Ω-cm resistivity. After pre-gate cleaning, the HfO2 films were deposited by a MOCVD cluster tool without surface nitridation prior to HfO2 deposition [6]. After an in-situ post-deposition annealing (PDA) at 700°C in N2 for 1 minute, TaN/HfN metal gate stacks were ex-situ deposited on HfO2 layer by reactive sputtering pure Hf or Ta target in Ar+N2 mixed gas ambient. The thickness of the HfO2 film after PDA was about 3 nm measured by ellipsometry. After patterning gate, MOSC samples were then rapid thermal annealed (RTA) in N2 at 1000°C for 20sec. An interfacial layer of 0.7~0.8 nm was formed between HfO2 layer and Si substrate [6]. Finally, the MOSC devices were subjected to back side Al metallization and the forming-gas annealing (FGA) at 420°C for 30min.Capacitance-voltage (C-V) and leakage current (I-V) characteristics were measured by a HP4194A LCR meter and a HP 4156 semiconductor parameter analyzer, respectively. Constant voltage stress was applied to evaluate the reliability. EOT of 0.9 nm and flat band voltage (V FB) of -0.45V were extracted by fitting the C-V measurements at 100 kHz with simulated C-V curves by UC Berkeley C-V simulation program [8], taking into account the quantum mechanical correction.3Result and discussionThe area dependent TDDB characteristics of the HfN/HfO2 gated nMOSC were firstly studied.Figure 1 shows the Weibull distributions of time-to-breakdown (t BD ) for 50×50 μm 2 and 100×100 μm 2 areas devices under negative CVS (Vg=-3.1V). The extracted slope (β) is 2.11 and 2.15 for 50×50 μm 2 and 100×100 μm 2 devices, respectively. The measured near constant slopes for the devices with different areas indicates that the intrinsic effects, not manufacturing-induced defects, dominate TDDB characteristics of the devices [1,9].101001000-3-2-101L n (-L n (1-F ))Time(s)Fig.1 Weibull distributions of time-to-breakdown (t BD ) for the HfN/HfO 2 gated nMOSC with 50×50μm 2 and 100×100 μm 2 areas under -3.1V CVS gate injection.Figure 2(a) shows TDDB characteristics of the nMOSC devices under different negative CVS. Under a low CVS (Vg=-2.0V) a smaller gate leakage jump was observed in sample A when the first breakdown event occurred. Compared to this, a larger gate leakage jump was observed in sample B when the first breakdown event occurred under a high CVS (CVS=-3.3V). After the first breakdown events had occurred under negative CVS, Time-Zero Dependent Breakdown (TZDB) measurements were then performed on the sample A and sample B, respectively. A larger gate leakage jump for sample A and lower gate leakage jump sample B were observed during TZDB measurements (as shown in Fig. 2(b)). The results shown in Fig. 2(a) and Fig. 2(b) suggest that two different breakdown processes, corresponding to the larger gate leakage jump and a lower gate leakage jump, respectively, occurred in both sample A and sample B. We could infer that the larger gate leakage jump is related to the bulk breakdown of HfO 2 layer and the lower gate leakage jump is related the IL breakdown. It is should be noted that hole trapping under high negative CVS and electron trapping under low negative CVS, similar to the results reported in Ref. [4], are also observed in the experiments (no shown herein).-0.40.00.40.81.21.62.02.4101010L n (|J |/V 2)V g -1(V )ΔJ g /J g (%)T im e (S )Fig. 2 (a) TDDB characteristics of HfN/HfO 2 gated nMOSCs under low CVS (Vg=-2V) for sample A and high CVS (Vg=-3.3 V) for sample B; (b) TZDB characteristics of the samples A and B after thefirst breakdown events occur under low and high CVS.101102103104105-2-101101001000-3-2-101L n (-L n (1-F ))Tim e(s) L n (-L n (1-F ))Tim e(s)Fig. 3 Weibull distributions of time-to-breakdown (t BD ) for the HfN/HfO 2 gated nMOSC with50×50 μm 2 areas under various CVS: (a) high CVS; (b) low CVSIn order to confirm this assumption, the Weibull distributions of time-to-breakdown (t BD) under both high CVS (Vg=-3.1V and Vg=-3.3V) and low CVS (Vg=-2.0V and Vg=-2.2V) were measured. Under high CVS, the obvious electric-field dependent Weibull slopes (β~2.97 for Vg=-3.1V and β~3.41 for Vg=-3.3V) were obtained in the sub-1 nm EOT HfO2 gate stack as shown in Fig. 3(a). These CVS dependent Weibull distribution slopes of t BD are the typical characteristics of bulk initiated TDDB [7]. In contrast to this, no electric-field dependent Weibull slopes (β~0.94 for both Vg=-2.0V and Vg=-2.2V) were obtained under low CVS as shown in Fig. 3(b), which suggest IL initiated breakdown will dominate the breakdown of HfO2 gate stack under a low CVS [4].Based on above results, a new breakdown model as shown in Fig. 4 is proposed to elucidate the different TDDB characteristics of the ultra-thin HfO2 gate stack with sub-1 nm EOT under high and low negative CVS. In general, the dielectric breakdown is associated with the generation of traps and the charge trapping [10]. Under a high CVS, as shown in Fig. 4(a), the holes trapping injected from substrate is dominant but occurs near to the HfO2/IL interface [4]. The electrons injected from gate electrode (HfN) go through HfO2 bulk layer by Fowler-Nordheim (FN) tunneling into conduction of HfO2 (process A to B) then go through IL layer by direct tunneling (process B to C). When the thickness of IL layer is only less than 1 nm, the injected electrons from conduction band of HfO2 easily go through the ultra thin IL layer by direct tunneling without causing charge traps. Thus, the electron trapping occurs in HfO2 bulk layer. In this case, electron and holes trapping at different spatial sites will lead to distortion in the energy band of the high-K dielectrics that enhance the HfO2 bulk internal electric field and induce the HfO2 bulk initiated breakdown [4]. Whereas, under a low CVS, as shown in Fig. 4(b), electrons trapping is dominant and electrons injected from gate electrode (HfN) go through continuously HfO2 bulk (~3nm) and IL (~0.7nm) layers by direct tunneling or trap assisted tunneling. In this case, the generation of electron traps both in HfO2 bulk and IL layers will be possible to occur. However, the electric field strength E IL in IL layer is significantly larger than one (E Bulk) in HfO2 bulk layer based on the Gauss law εIL E IL=εBulk E Bulk, where εIL(~7-9) andεBulk (~24) [6] are the dielectric constants of IL and HfO2 layer. Thus, the electron trapping in IL layer is much easier than the bulk breakdown of HfO2 layer due to the higher electric field stress in IL. In this case, the IL initiated breakdown will dominate the reliability, similar to the case reported in Ref [1, 2].These results indicate that IL initiated and HfO2 bulk initiated breakdown processes will occur under low CVS and high CVS respectively when the IL layer is less than 1 nm.Fig. 4 Band diagram structures of the HfN/HfO2 gate stack under CVS gate injection for (a) under highCVS; (b) under low CVS.4ConclusionIn this paper, the TDDB characteristics of HfN/HfO2 gate stack with sub-1 nm EOT were demonstrated under gate injection. The IL initiated breakdown under low CVS and HfO2 bulk initiated breakdown under high CVS were observed, respectively. A new breakdown model is proposed to explain the different TDDB characteristics under low and high CVS. These different TDDB characteristics imply that the conventional projection model of lifetime applied in single SiO2 gate oxide layer cannot be implemented to the high K gate stack.ACKNOWLEDGMENTThis work is supported partly by NSFC (90407015), 973 Program (2006CB302700), and RFDP (20040001026).References[1] A. S. Oates, “Reliability Issues for High-K Gate Dielectrics,” in IEDM Tech. Dig., p.923-926, 2003.[2] R. Degraeve, B. Kaczer, M. Houssa, G. Groeseneken, M. Heyns, J. S. Jeon, A. Halliyal, “Analysis of highvoltage TDDB measurements on Ta2O5/SiO2 stack,” in IEDM Tech. Dig., p.327-330, 1999.[3] S. J. Lee, S. J. Rhee, R. Clark, D. L. Kwong,“Reliability Projection and Polarity Dependence of TDDB forUltra Thin CVD HfO2 Gate Dielectrics,” in Proc. Symp. VLSI Technol., p.78-79, 2002.[4] Wei Yip Loh, Byung Jin Cho, Moon Sig Joo, M.F. Li, Daniel SH Chan, Shajan Mathew, Dim-Lee Kwong, “Analysis of Charge Trapping and Breakdown Mechanism in High-K Dielectrics with Metal Gate Electrode using Carrier Separation,” in IEDM Tech. Dig., p. 927-930, 2003.[5] R. Degraeve, A. Kerber, P. Roussell, E. Cartier, T. Kauerauf, L. Pantisano, G. Groeseneken, “Effect of bulktrap density on HfO2 reliability and yield.” in IEDM Tech. Dig., p. 935-938, 2003.[6] H. Y. Yu, J. F. Kang, J. D. Chen, C. Ren, Y. T. Hou, S. J. Whang, M. -F. Li, D. S. H. Chan, K. L. Bera, C. H.Tung, A. Du, D. L. Kwong, “Thermally Robust High Quality HfN/HfO2 Gate Stack for Advanced CMOS Devices,” in IEDM Tech. Dig., p.99-102, 2003.[7] R. Degraeve, T. Kauerauf, A. Kerber, E. Cartier, B. Govoreanu, Ph. Roussel, L. Pantisano, P. Blomme, B.Kaczer, G. Groeseneken, “Stress polarity dependence of degradation and breakdown of SiO2/High-K stacks,”in Proc. IRPS, p.23-28, 2003.[8] K. Yang, Y-C King, and C. Hu, “Quantum Effect in Oxide Thickness Determination From CapacitanceMeasurement,” in Proc. Symp. VLSI Technol. p. 77-78, 1999.[9] T. Nigam, R. Degraeve, G. Groeseneken, M. M. Heyns, H.E. Maes, “Constant Current Charge-to-breakdown:still a valid tool to study the reliability of MOS structures,” in Proc. IRPS, p.62-69, 1998.[10] Y. H. Kim, K. Onishi, C. S. Kang, H-J. Cho, R. Nieh, S. Gopalan, R. Choi, J. Han, S. Krishnan, and J. C. Lee,“Area Dependence of TDDB Characteristics for HfO2 Gate Dielectrics”, IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 10, pp.594-596, 2002Author Brief Introduction: Jinfeng Kang , Ph. D, Professor. He received his B.S. degree in physics from Dalian University of Technology in 1984, and M.S. and Ph.D degrees in solid-state electronics from Peking University in 1992 and 1995 respectively. Next, he joined Institute of Microelectronics in Peking University as a post-doctoral fellow. In 1997 he joined the faculty first as an associate professor and then professor in 2001. In 2002 he ever worked in National University of Singapore as a visiting professor for a year. He is a Professor of Microelectronics Departments in Peking University. Currently his research interests are in the areas of metal/high K gate dielectric stack, sub-100nm MOS device physics and process technology, novel memory device and technology. He has published a book and more than 100 conference and journal papers.。

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微电子器件的可靠性
复旦大学材料科学系
12
超薄氧化层直接隧道的偏置温度不稳定性
1999年N. Kimizuka 等首先在氧化层厚度 tox=2.0 ~ 4.0nm 的N 及P－MOSFET中观察到隧道超薄氧化层的偏置温度不稳定性。 PMOSFET的最大应力为－3.0V（在－3.5V会因碰撞电离产生电子、空穴对). 试验温度高温为 100℃和150℃。试验进行了105秒（27.7小时）试验发现： 1 器件的VT和GM随栅极发生漂移。 2 PMOSFET比NMOSFET的漂移要大一个数量级。
微电子器件的可靠性
复旦大学材料科学系
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软击穿
软击穿的漏电流比 SILC大2-3个数量级，但比击穿电流小4-6 个数量级。软击穿漏电流不随着器件面积的减小而减小。这说明它是一种局部失效。
微电子器件的可靠性
复旦大学材料科学系
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软击穿模式
软击穿可分为两种模式： 1）模拟信号模式（analog-mode soft breakdown）， 2）数字信号模式（digital-mode soft breakdown）。数字信号模式的栅电流的波动有大于模拟信号模式，并且在高的栅压下，数字信号模式将产生更大的漏电流
微电子器件的可靠性复旦大学材料科学系 3
应力漏电的性质
应力漏电流的大小是随时间而衰减的，它可以分为两部分： a.瞬时电流Jtr ;随时间而衰减的； b.直流电流Jss :大小恒定的。
微电子器件的可靠性
复旦大学材料科学系
4
应力漏电的性质
SILC与氧化层电容面积的关系:SILC与氧化层电容的面积成正比。这说明SILC的导电沟道均匀分布于整个氧化层的表面，而不是存在于个别的点中。
微电子器件的可靠性
复旦大学材料科学系
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PMOS NBTI的特性
VT与偏置时的温度、电压有强烈的关系。 VT与时间的n次方成正比，即VT ～t1/4.
微电子器件的可靠性
复旦大学材料科学系
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PMOS NBTI的特性
当氧化层的厚度越薄，同样条件下 VT的漂移越大 . 氧化层厚度不同的器件的漂移曲线相互平行 . 。试验结果表明，VT的漂移随着PMOSFET沟道长度的减小而增加
微电子器件的可靠性复旦大学材料科学系 16
PMOS NBTI的来源
VT的漂移与氧化层界面陷阱电荷的增加成正比关系
微电子器件的可靠性
复旦大学材料科学系
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NBTI缺陷产生机理
微电子器件的可靠性
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NBTI与HC
与NMOSFET热载流子效应相比，PMOSFET NBTI 对器件工作寿命的限制更为重要，VD 低于3V时，NBTI比热载流子的寿命更短。
微电子器件的可靠性复旦大学材料科学系
非弹性陷阱辅助隧道模型
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SILC对器件可靠性的影响
SILC影响氧化层漏电流因而对EEPROM、Flash Memory影响较明显：它使浮栅阈值电压的漂移和数据保持的性能退化。 SILC造成浮栅上电荷丢失，使得浮栅的阈值电压产生漂移。
经擦/写后，浮栅漏电流与电压的典型曲线
微电子器件的可靠性
复旦大学材料科学系
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超薄氧化层的几种现象
1。正常特性 2。应力漏电 Stress Induced leakage Current 3。软击穿 Soft Breakdown 4。硬击穿
微电子器件的可靠性
复旦大学材料科学系
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超薄氧化层的应力漏电(SILC)
应力漏电（SILC）是1982年在加了恒定电应力(6.3V）的5nm超薄氧化层中发现的。在一个n+Poly Si/SiO2/n+Si 的电容 (10-4cm2)两端施加高压，经正、负电应力前其电场达到12MV/cm，测得如图（1）所示的电流后的I－V曲线和栅压关系曲线。
超薄氧化层的可靠性
近年在超薄氧化层可靠性方面的两个新问题 1。超薄氧化层的应力漏电 (Stress Induced Leakage Current, SILC), 软击穿（SBD, Soft BreakDown）。 2.PMOS器件的负偏不稳定性(Negative Bias Temperature Instability, NBTI)
微电子器件的可靠性
复旦大学材料科学系
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NBTI与HC
与NMOSFET热载流子效应相比，PMOSFET 的 NBTI 对器件工作寿命的限制更为重要，VD低于3V时，NBTI比热载流子的寿命更短。器件参数与CHC、NBTI
微电子器件的可靠性
复旦大学材料科学系
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NBTI对晶体管性能的影响
由于阈值电压的漂移，使得漏极电流同时发生漂移，随着VDD增加，IDS的漂移也增加
微电子器件的可靠性
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NBTI对电路性能的影响
CMOS反向器中的VT漂移
微电子器件的可靠性
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微电子器件的可靠性
复旦大学材料科学系
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应力漏电的性质
SILC的温度特性：SILC是随着温度的升高而增加，但其热激活能很小 , 所以它的变化仍是微弱的 . SILC与测量电压的关系 SILC随测量时电场的增强而增加。
微电子器件的可靠性
复旦大学材料科学系
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应力漏电的来源
起源于在氧化层电流应力产生的陷阱。瞬时电流这些缺陷与SiO2 界面靠得很近，在外加电场的作用下，缺陷中的电荷发生充电或放电过程，因而产生瞬时电流。直流电流在电场下弹性或非弹性陷阱辅助隧道电流
PMOS FET (TOX＝1.3nm) NBTI 应力试验，阈值电压漂移与时间的关系.应力条件：温度T＝100℃，VG＝2.7V
微电子器件的可靠性
复旦大学材料科学系
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PMOS NBTI的来源
VT的漂移与氧化层界面陷阱电荷的增加成正比关系
NBTI应力试验中 PMOS FET (TOX＝ 1.3nm) ，阈值电压漂移与DCIV电流的关系曲线。
微电子器件的可靠性
复旦大学材料科学系
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应力漏电的性质
SILC与氧化层厚度的关系 TOX>5nm，SILC随氧化层厚度的减小而增加 TOX<5nm，SILC随氧化层厚度的学材料科学系
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应力漏电的性质
JSILC 与Jstress 、TOX 的关系 (a)Ig(Vg) characteristics for Jstress=10 mA/cm2 after various stress doses. (b) SILC density evolution during the stress for 5.5, 7 and 10 nm oxides (Jstress=10 mA/cm2).