MAX1772充电管理IC引脚定义

16
CELLS
Trilevel Input for Setting Number of Cells. GND = 2 cells, LDO/2 = 3 cells, LDO = 4 cells.
三种输入设定电池节数。GND=2节，LDO/2=3节，LDO=4节。
17
BATT
BatteryVoltage Input.
驱动供电。由DCIN给内部线性稳压器输出5.4V提供，接1UF旁路电容。
3
CSL
Source Current Limit Input. Voltage input for setting the current limit of the input source.
电流源限流输入。输入电压用于输入源的限流设定。
输出电流检测正相端输入。
20
PGND
Power Ground.
电源地。
21
DLO
Low-Side Power MOSFET Driver Output. Connect to low-side NMOS gate.
低边功率MOSFET驱动输出。连接到低边NMOS栅极。
22
DLOV
Low-Side Driver Supply.
最大输出电流设定输入。范围REFI/32到REFIN，低于REFIN/55（典型）驱动强制关断该引脚。注：调整其设定值即可改变充电电流大小。
15
VCTL
Input for Setting Maximum Output Voltage. Range is 0 to REFIN.
设定最大输出电压输入。范围从0到REFIN。
充电电流检测（正相端输入）。连接一个检流电阻从CSSP到CSSN。
28
IINP
IINP is a scaled - down replica of the input current being sensed . It is used to monitor the total system current. The transconductance of ( CSSP - CSSN ) to IINP is 1m S . Connect IINP pin to GND if it is unused .
电源连接到高边功率MOSFET驱动器。连接0.1UF电容器从LX到BST。
26
CSSN
Input Current-Sense for Charger (negative input)
充电电流输入检测（反相端输入）
27
CSSP
Input Current-Sense for Charger (positive input). Connect a current-sense resistor from CSSP to CSSN.
AC检测输入。当AC适配器电压可用于充电时检测。
12
ACOK
AC Detect Output. Open-drain output is high when ACIN is less than REF/2.
AC检测输出。当ACIN低于REF/2（内部比较器正相端设定值）时开漏输出为高。
注意：ACIN（内部比较器反相端输入）高于REF/2必然输出低。因此利用ACOK控制开启PMOS或P型三极管可用于对适配器隔离电路的控制逻辑。广达设计开启隔离思路。
电池电压输入。
18
CSIN
Output Current-Sense Negative Input.
输出电流检测反相端输入。
19
CSIP
Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN.
电压（充电电压）调整环路补偿点。连接1K欧电阻串联0.1UF电容至地。
8
GND
Analog Ground
模拟地。
9
GND
Analog Ground
模拟地。
10
ICHG
ICHG is a scaled-down replica of the battery output current being sensed. It is used to monitor the charging current and indicates when the chip changes from voltage mode to current mode. The transconductance of (CSIP - CSIN) to ICHG is 1μS. Connect ICHG pin to GND if it is unused.
MAX1772充电管理IC引脚定义
PIN
NAME
FUNCTION
1
DCIN
Charging Voltage Input
充电电压输入。
2
LDO
Device Power Supply. Output of the 5.4V linear regulator supplied from DCIN . Bypass with a 1μF capacitor .
IINP是输入电流检测的比例复制。它用于监视整个系统电流。CSSP-CSSN到IINP跨导是1MS。如果不使用连接IINP引脚至地。
注：IINP就是系统电流检测输出，如系统电流过高，可用于控制低功耗模式。
MAX1772内部框架原理图一
MAX1772内部框架原理图二
电源连接为高边功率MOSFET驱动器。连接至高边NMOS源极。
24
DHI
High-Side Power MOSFET Driver Output. Connect to high-side NMOS gate.
高边功率MOSFET驱动输出。连接至高边NMOS栅极。
25
BST
Power Connection for the High-Side Power MOSFET Driver. Connect a 0.1μF capacitor from LX to BST.
ICHG是用于电池电流电流并提示。CSIP-CSIN到ICHG的跨导是1US。如果不使用连接ICHG引脚至地。
注：ICHG就是充电电流检测后输出引脚，DV1000上拉至REF，接地或接电源屏蔽。
11
ACIN
AC Detect Input. Detects when the AC adapter voltage is available for charging.
低边驱动器供电。
注：外接阻容延时振荡，决定低边MOS驱动频率。公式：f = 1/2∏RC
如：1 / (2∏✕33欧✕0.1μF) = 48kHz，频率计算需欧姆和微法单位统一。
23
LX
Power Connection for the High-Side Power MOSFET Driver. Connect to source of high-side NMOS.
6
CCI
Output Current Regulation Loop Compensation Point. Connect 0.01μF to GND.
输出电流（充电电流）调整环补偿点。使用0.01UF电容至地。
7
CCV
Voltage Regulation Loop Compensation Point. Connect 1kΩ in series with 0.1μF to GND.
4
REF
4.096V Voltage Reference. Bypass with 1μF to GND.
4/096V基准参考电压。旁路1UF电容至地。
5
CCS
Input Current Regulation Loop Compensation Point. Use 0.01μF to GND.
输入电流（系统电流）调整环补偿点。使用0.01UF电容至地。
13
REFIN
Reference Input. Allows the ICTL and VCTL pins to have ratiometric ranges for increased DAC accuracy.
参考基准输入。允许ICTL和VCTL引脚有比例范围用于增加数模精准度。
14
ICTL
Input for Setting Maximum Output Current. Range is REFIN/32 to REFIN. The device shuts down if this pin is forced below REFIN/55 (typ).