STA328 完美数字音频功放集成块

May 2008 Rev 41/57STA3282.1-channel high-efficiency digital audio systemFeatures!Wide supply voltage range (10 V - 36V)!Three power output configurations –2x 40W + 1x 80W –2x 80W –1x 160W !PowerSO-36 package ! 2.1 channels of 24-bit DDX ®!100-dB SNR and dynamic range !32kHz to 192kHz input sample rates !Digital gain/attenuation +48dB to -80dB in 0.5-dB steps!Four 28-bit user programmable biquads (EQ) per channel !I 2C control!2-channel I 2S input data interface!Individual channel and master gain/attenuation !Individual channel and master soft/hard mute !Individual channel volume and EQ bypass !Bass/treble tone control!Dual independent programmable limiters/compressors!AutoModes–32 preset EQ curves–15 preset crossover settings –Auto volume controlled loudness – 3 preset volume curves– 2 preset anti-clipping modes –Preset night-time listening mode –Preset TV AGC!Input and output channel mapping !AM noise-reduction and PWM frequency-shifting modes!Software volume update and muting !Auto zero detect and invalid input detect muting!Selectable DDX ® ternary or binary PWM output + variable PWM speeds !Selectable de-emphasis!Post-EQ user programmable mix with default 2.1 bass-management settings!Variable max power correction for lower full-power THD!Four output routing configurations !Selectable clock input ratio!96kHz internal processing sample rate, 24 to 28-bit precision!Video application supports 576 * fs input mode.Table 1.Device summaryOrder codePackagePackagingST A328PowerSO-36Tube ST A32813TRPowerSO-36Tape and reelContents STA328Contents1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2EQ processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3Output configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1Package pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.2Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.3Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1General interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2DC electrical specifications (3.3V buffers) . . . . . . . . . . . . . . . . . . . . . . . . 123.3Power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.1Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.2Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.3Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.4Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196.1Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206.2Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236.3Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.3.1DDX® power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266.3.2DDX® variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 266.4Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276.5Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/57STA328Contents6.6Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.7Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.7.1Master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.7.2Channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.7.3Volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.8AutoMode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356.8.1AutoModes EQ, volume, GC (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . 356.8.2AutoMode AM/pre-scale/bass management scale (addr 0x0C) . . . . . . 366.8.3Preset EQ settings (addr 0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.9Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.9.1Channel 1 configuration (addr 0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.9.2Channel 2 configuration (addr 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.9.3Channel 3 configuration (addr 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.10Tone control (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.11Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.11.1Limiter 1 attack/release threshold (addr 0x12) . . . . . . . . . . . . . . . . . . . . 416.11.2Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . . 416.11.3Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 416.11.4Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . . 416.11.5Dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.11.6Anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436.11.7Dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447User programmable processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457.1EQ - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457.2Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457.3Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457.4Mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467.5Calculating 24-bit signed fractional numbers from a dB value . . . . . . . . . 477.6User defined coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.6.1Coefficient address register 1 (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . 477.6.2Coefficient b1data register bits 23:16 (addr 0x17) . . . . . . . . . . . . . . . . . 477.6.3Coefficient b1data register bits 15:8 (addr 0x18) . . . . . . . . . . . . . . . . . . 477.6.4Coefficient b1data register bits 7:0 (addr 0x19) . . . . . . . . . . . . . . . . . . . 477.6.5Coefficient b2 data register bits 23:16 (addr 0x1A) . . . . . . . . . . . . . . . . 477.6.6Coefficient b2 data register bits 15:8 (addr 0x1B) . . . . . . . . . . . . . . . . . 483/57Contents STA3284/577.6.7Coefficient b2 data register bits 7:0 (addr 0x1C) . . . . . . . . . . . . . . . . . . 487.6.8Coefficient a1 data register bits 23:16 (addr 0x1D) . . . . . . . . . . . . . . . . 487.6.9Coefficient a1 data register bits 15:8 (addr 0x1E) . . . . . . . . . . . . . . . . . 487.6.10Coefficient a1 data register bits 7:0 (addr 0x1F) . . . . . . . . . . . . . . . . . . 487.6.11Coefficient a2 data register bits 23:16 (addr 0x20) . . . . . . . . . . . . . . . . 487.6.12Coefficient a2 data register bits 15:8 (addr 0x21) . . . . . . . . . . . . . . . . . 487.6.13Coefficient a2 data register bits 7:0 (addr 0x22) . . . . . . . . . . . . . . . . . . 487.6.14Coefficient b0 data register bits 23:16 (addr 0x23) . . . . . . . . . . . . . . . . 497.6.15Coefficient b0 data register bits 15:8 (addr 0x24) . . . . . . . . . . . . . . . . . 497.6.16Coefficient b0 data register bits 7:0 (addr 0x25) . . . . . . . . . . . . . . . . . . 497.6.17Coefficient write control register (addr 0x26) . . . . . . . . . . . . . . . . . . . . . 49 7.7Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.8Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.9Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.10Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.11Variable max power correction (addr 0x27, 0x28) . . . . . . . . . . . . . . . . . . 53 7.12Fault detect recovery (addr 0x2B, 0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . 538Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56STA328Description 1 Description1.1 OverviewThe STA328 comprises digital audio processing, digital amplifier control and DDX® poweroutput stage to create a high-power single-chip DDX® solution for high-quality,high-efficiency, all digital amplification.The STA328 power section consists of four independent half-bridges. These can beconfigured via digital control to operate in different modes. 2.1 channels can be provided bytwo half-bridges and a single full-bridge to give up to 2x40W plus 1x80 W of poweroutput. Two channels can be provided by two full-bridges to give up to 2x80W of power.The IC can also be configured as a single parallel full-bridge capable of high-currentoperation and 1x160W output.Also provided in the ST A328 is a full assortment of digital processing features. This includesup to four programmable 28-bit biquads (EQ) per channel and bass/treble tone control.AutoModes enable a time-to-market advantage by substantially reducing the amount ofsoftware development needed for certain functions. This includes auto volume loudness,preset volume curves, preset EQ settings. New advanced AM radio-interference reductionmodes.The serial audio data input interface accepts all possible formats, including the popular I2Sformat.Three channels of DDX® processing are provided. This high-quality conversion from PCMaudio to patented DDX® 3-state PWM switching provides over 100dB of SNR and dynamicrange.5/57Description STA3286/571.2 EQ processingTwo channels of input data (re-sampled if necessary) at 96kHz are provided to the EQprocessing block. In this block, up to four user-defined biquads can be applied to each of the two channels.Pre-scaling, DC-blocking, high-pass, de-emphasis, bass, and tone control filters can also be applied based on various configuration parameter settings.The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. And the CxEQBP bits can be used to bypass the EQ function on a per channel basis. Figure 3 shows the internal signal flow through the EQ block.1.3 Output configurationsSTA328Description 1.4 Applications7/57Pin out STA3288/572 Pin out2.1 Package pinsFigure 6.Pin connections2.2 Pin listVCC_SIGNVSS VDD GND BICKI LRCKI SDI VDDA GNDA XTIPLL_FILTER RESERVEDSDA SCL RESET CONFIGVLVDD_REG SUB_GND N.C.OUT2B VCC2B N.C.GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C.VCC1A OUT1AGND_CLEAN GND_REG363534333231302928272625242322212019123456789101112131415161718Table 2.Pin listNumber TypeNameDescription1I/O SUB_GND Ground 2N.C.N.C.Not connected 3O OUT2B Output half bridge 2B 4I/O VCC2B Positive supply 5N.C.N.C.Not connected 6I/O GND2B Negative supply 7I/O GND2A Negative supply 8I/O VCC2A Positive supply 9O OUT2A Output half bridge 2A 10O OUT1B Output half bridge 1B 11I/O VCC1B Positive supply 12I/O GND1B Negative supply 13I/O.GND1A Negative supply 14N.C.N.C.Not connectedSTA328Pin out9/572.3 Pin descriptionOUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3)Output half bridge PWM outputs 1A, 1B, 2A and 2B provide the input signals to thespeakers.RESET (pin 22)Driving RESET low sets all outputs low and returns all register settings to their default (reset) values. The reset is asynchronous to the internal clock.15I/O VCC1A Positive supply 16O OUT1A Output half bridge 1A 17I/O GND_CLEAN Logical ground 18I/O GND_REG Substrate ground 19I/O VDD_REG Logic supply 20I/O VL Logic supply 21I CONFIG Logic levels 22I RESET Reset23I SCL I 2C serial clock 24I/O SDA I 2C serial data25-RESERVED This pin must be connected to GND 26I PLL_FILTER Connection to PLL filter 27I XTI PLL input clock 28I/O GNDA Analog ground29I/O VDDA Analog supply, nominally 3.3 V 30I SDI I 2S serial data channels 1 & 231I/O LRCKI I 2S left/right clock, 32I BICKI I 2S serial clock 33I/O GND Digital ground34I/O VDD Digital supply, nominally 3.3V 35I/O VSS 5V regulator referred to +V CC 36I/OVCC_SIGN5V regulator referred to groundTable 2.Pin listNumber TypeNameDescriptionPin out STA32810/57I2C signals (pins 23 and 24)The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification (Chapter5 on page16 gives more information). Fast-mode (400kB/s) I2C communication is supported.GNDA and VDDA (pins 28 and 29)This is the 3.3 V analog supply for the phase locked loop. It must be well decoupled and filtered for good noise immunity since the audio performance of the device depends upon the PLL circuit.CLK (pin 27)This is the master clock in used by the digital core. The master clock must be an integer multiple of the LR clock frequency. Typically, the master clock frequency is 12.288MHz (256*fs) for a 48kHz sample rate; it is the default setting at power-up. Care must be taken to provide the device with the nominal system clock frequency; over-clocking the device may result in anomalous operation, such as inability to communicate.FILTER_PLL (pin 26)This is the connection for external filter components for the PLL loop compensation. The schematic diagram in Figure5 on page7 shows the recommended circuit.BICKI (pin 32)The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64*fs using I2S serial format.SDI_12 (pin 30)This is the serial data input where PCM audio information enters the device. Six format choices are available including I2S, left or right justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits.LRCKI (pin 31)The left/right clock input is for data word framing. The clock frequency is at the input sample rate, fs.11/573 Electrical specificationsTable 3.Absolute maximum ratingsTable 4.Thermal dataTable 5.Recommended operating conditions3.1 General interface specificationsOperating conditions V DD33 = 3.3V ±0.3V , T amb = 25°C unless otherwise specifiedSymbol ParameterValueUnit V DD33 3.3V I/O power supply (pins VDDA, VDD)-0.5 to 4V V i Voltage on input pins -0.5 to (V DD33+0.5)V V o Voltage on output pins -0.5 to (V DD33+0.5)V T stg Storage temperature-40 to +150°C T amb Ambient operating temperature-20 to +85°C V CC DC supply voltage (pins VCCnA, VCCnB)40V V MAXMaximum voltage on VL (pin 20)5.5VSymbol ParameterMinTypMax Unit R thj-case Thermal resistance junction to case (thermal pad) 2.5°C/W T j-SD Thermal shut-down junction temperature 150°C T WARN Thermal warning temperature 130°C T h-SDThermal shut-down hysteresis25°CSymbol ParameterValueUnit V DD33 I/O power supply3.0 to 3.6V T jOperating junction temperature-20 to +125°CTable 6.General interface electrical characteristicsSymbol ParameterTest Condition Min.Typ.Max.Unit I il Low level input no pull-up V i = 0V (1)1.The leakage currents are generally very small (< 1 nA). The values given here are the maximum valuesafter an electrostatic stress on the pin.1µA I ih High level input no pull-downV i = V DD33 (1)2µA I OZ 3-state output leakage withoutpull-up/downV i = V DD33 (1)2µA V esdElectrostatic protection (human-body model)Leakage current < 1µA2000V12/573.2 DC electrical specifications (3.3V buffers)Operating conditions V DD33 = 3.3V ±0.3V , T amb = 25°C unless otherwise specified3.3 Power electrical specificationsOperating conditions V DD33 = 3.3V ±0.3V , V L =3.3V , V CC =30V ,T amb = 25°C unless otherwise specified.Table 7.DC electrical specificationsSymbol ParameterTest conditionMin.Typ.Max.Unit V IL Low level input voltage 0.8V V IH High level input voltage 2.0V V hyst Schmitt trigger hysteresis 0.4V V ol Low level output IoI = 2mA 0.15V V ohHigh level outputIoh = -2mAV DD33- 0.15VTable 8.Power electrical characteristicsSymbol ParameterTest conditions Min.Typ.Max.Unit R dsON Power Pchannel/Nchannel MOSFET RdsON Id =1A 200270m Ω I dss Power Pchannel/Nchannel leakage IdssV CC = 35V 50µA g N Power Pchannel RdsON matchingId =1A 95%g P Power Nchannel RdsON matchingId =1A95%Dt_s Low current dead time (static)See test circuits, Figure 7 and Figure 81020ns t d ON Turn-on delay time Resistive load 100ns t d OFF Turn-off delay time Resistive load100ns t r Rise time Resistive load, Figure 7 and Figure 825ns t f Fall time Resistive load, Figure 7 and Figure 825ns V CC Supply voltage1036V V L Low logical state voltage VL V L = 3.3V 0.8V V H High logical state voltage VH V L = 3.3V 1.7V I VCC-PWRDNSupply current from V CC in PWRDNPin PWRDN = 0 V 3mA I VCC-hizSupply current from V CC in 3-stateV CC =30V , 3-state22mA13/57Figure 7.Test circuit 1I VCCSupply current from V CC in operation(both channel switching)Input pulse width = 50% duty,switchingfrequency =384kHz,no LC filters80mAI out-sh Overcurrent protectionthreshold (short circuit current limit)4.56AV UV Undervoltage protection threshold7V t pw-min Output minimum pulse width No load70150ns P oOutput power (refer to test circuitTHD = 10%R L = 4Ω, V CC = 21V R L = 8Ω, V CC = 36V 5080W W P oOutput power (refer to test circuitTHD = 1%R L = 4Ω, V CC = 21V R L = 8Ω, V CC = 36V4062W WTable 8.Power electrical characteristics (continued)SymbolParameterTest conditions Min.Typ.Max.UnitDT rDTfVcc (3/4)Vcc(1/2)Vcc (1/4)VcctOUTxYLow current dead time = MAX(DT r, DTf)+VccDuty cycle = 50%INxYM58M57OUTxYgndvdc = Vcc/2V67R 8W+-4 Electrical characteristics curves14/5715/57I 2C bus specificationSTA32816/575 I 2C bus specificationThe STA328 supports the I 2C protocol. This protocol defines any device that sends data on to the I 2C bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA328 is always a slave device in all of its communications.5.1 Communication protocolData transition or changeData changes on the SDA line must only occur when the SCL clock is low. SDA transitionwhile the clock is high is used to identify a START or STOP condition.Start conditionSTART is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer.Stop conditionSTOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA328 and the bus master.Data inputDuring the data input the STA328 samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low.5.2 Device addressingTo start communication between the master and the STA328, the master must initiate with astart condition. Following this, the master sends 8 bits (MSB first) onto the SDA line corresponding to the device select address and read or write mode.The 7 MSBs are the device address identifiers, corresponding to the I 2C bus definition. The STA328 device address is decimal 34 (binary 00100010).The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write mode. After a START condition the STA328 identifies the device address on the bus. If a match is found, it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address.STA328I 2C bus specification17/575.3 Write operationFollowing the START condition the master sends a device select code with the RW bit setto 0. The ST A328 acknowledges this and then the master writes the internal address byte. After receiving the internal byte address the STA328 again responds with an acknowledgement.2Byte writeIn the byte write mode the master sends one data byte. This is acknowledged by the STA328. The master then terminates the transfer by generating a STOP condition.Multi-byte writeThe multi-byte write modes can start from any internal address. Sequential data byte writes will be written to sequential addresses within the STA328. The master generating a STOP condition terminates the transfer.5.4 Read operation2Current address byte readFollowing the START condition the master sends a device select code with the RW bit set to 1. The STA328 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.I2C bus specification STA32818/57Current address multi-byte readThe multi-byte read modes can start from any internal address. Sequential data bytes will be read from sequential addresses within the STA328. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.Random address byte readFollowing the START condition the master sends a device select code with the RW bit set to0. The ST A328 acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA328 again responds with an acknowledgement. The master then initiates another ST ART condition and sends the device select code with the RW bit set to 1. The ST A328 acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition.Random address multi-byte readThe multi-byte read modes could start from any internal address. Sequential data bytes will be read from sequential addresses within the ST A328. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer.STA328Register description19/576 Register descriptionY ou must not reprogram the register bits marked “Reserved”. It is important that these bitskeep their default reset values.Table 9.Register summaryAddress Name D7D6D5D4D3D2D1D00x00ConfA FDRB TWAB TWRB IR1IR0MCS2MCS1MCS00x01ConfB C2IMC1IMDSCKE SAIFB SAI3SAI2SAI1SAI00x02ConfC Reserved CSZ4CSZ3CSZ2CSZ1CSZ0OM1OM00x03ConfD MME ZDE DRCBQLPSL DSPBDEMPHPB 0x04ConfE SVE ZCEReserved PWMS AMEReserved MPC MPCV 0x05ConfF E APDPWDN E CL E Reserved BCL EIDE OCFG1OCFG00x06Mmute Reserved Reserved Reserved Reserved Reserved Reserved Reserved MMute 0x07Mvol MV7MV6MV5MV4MV3MV2MV1MV00x08C1Vol C1V7C1V6C1V5C1V4C1V3C1V2C1V1C1V00x09C2Vol C2V7C2V6C2V5C2V4C2V3C2V2C2V1C2V00x0A C3Vol C3V7C3V6C3V5C3V4C3V3C3V2C3V1C3V00x0B Auto1AMPS Reserved AMGC1AMGC0AMV1AMV0AMEQ1AMEQ00x0C Auto2XO3XO2XO1XO1AMAM2AMAM1AMAM0AMAME 0x0D Auto3Reserved Reserved Reserved PEQ4PEQ3PEQ2PEQ1PEQ00x0E C1Cfg C1OM1C1OM0C1LS1C1LS0C1BO C1VBP C1EQBP C1TCB 0x1F C2Cfg C2OM1C2OM0C2LS1C2LS0C2BO C2VBP C2EQBP C2TCB 0x10C3Cfg C3OM1C3OM0C3LS1C3LS0C3BO C3VBP Reserved Reserved 0x11Tone TTC3TTC2TTC1TTC0BTC3BTC2BTC1BTC00x12L1ar L1A3L1A2L1A1L1A0L1R3L1R2L1R1L1R00x13L1atrt L1A T3L1A T2L1A T1L1A T0L1RT3L1RT2L1RT1L1RT00x14L2ar L2A3L2A2L2A1L2A0L2R3L2R2L2R1L2R00x15L2atrt L2A T3L2A T2L2A T1L2A T0L2RT3L2RT2L2RT1L2RT00x16Cfaddr2CFA7CFA6CFA5CFA4CFA3CFA2CFA1CFA00x17B1cf1C1B23C1B22C1B21C1B20C1B19C1B18C1B17C1B160x18B1cf2C1B15C1B14C1B13C1B12C1B11C1B10C1B9C1B80x19B1cf3C1B7C1B6C1B5C1B4C1B3C1B2C1B1C1B00x1A B2cf1C2B23C2B22C2B21C2B20C2B19C2B18C2B17C2B160x1B B2cf2C2B15C2B14C2B13C2B12C2B11C2B10C2B9C2B80x1C B2cf3C2B7C2B6C2B5C2B4C2B3C2B2C2B1C2B00x1DA1cf1C3B23C3B22C3B21C3B20C3B19C3B18C3B17C3B16Register description STA32820/576.1 Configuration register A (addr 0x00)The STA328 will support sample rates of 32kHz, 44.1kHz, 48kHz, 88.2kHz, and 96kHz. Therefore the internal clock will be:"32.768MHz for 32kHz"45.1584MHz for 44.1kHz, 88.2kHz, and 176.4kHz "49.152MHz for 48kHz, 96kHz, and 192kHzThe external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The correlation between the input clock and the input sample rate isdetermined by the status of the MCSx bits and the IR (input rate) register bits. The MCSx0x1E A1cf2C3B15C3B14C3B13C3B12C3B11C3B10C3B9C3B80x1F A1cf3C3B7C3B6C3B5C3B4C3B3C3B2C3B1C3B00x20A2cf1C4B23C4B22C4B21C4B20C4B19C4B18C4B17C4B160x21A2cf2C4B15C4B14C4B13C4B12C4B11C4B10C4B9C4B80x22A2cf3C4B7C4B6C4B5C4B4C4B3C4B2C4B1C4B00x23B0cf1C5B23C5B22C5B21C5B20C5B19C5B18C5B17C5B160x24B0cf2C5B15C5B14C5B13C5B12C5B11C5B10C5B9C5B80x25B0cf3C5B7C5B6C5B5C5B4C5B3C5B2C5B1C5B00x26Cfud Reserved Reserved Reserved Reserved RA R1WAW10x27MPCC1MPCC15MPCC14MPCC13MPCC12MPCC11MPCC10MPCC9MPCC80x28MPCC2MPCC7MPCC6MPCC5MPCC4MPCC3MPCC2MPCC1MPCC00x29Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x2B FDRC1FDRC15FDRC14FDRC13FDRC12FDRC11FDRC10FDRC9FDRC80x2C FDRC2FDRC7FDRC6FDRC5FDRC4FDRC3FDRC2FDRC1FDRC00x2DReserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedReservedD7D6D5D4D3D2D1D0FDRB TWAB TWRB IR1IR0MCS2MCS1MCS001111Table 9.Register summaryAddress Name D7D6D5D4D3D2D1D0Table 10.Master clock selectBit R/W RST Name Description0RW 1MCS0Master clock select: Selects the ratio between the input I 2S sample frequency and the input clock.1RW 1MCS12RWMCS2。