半导体工艺-复旦大学-蒋玉龙-Chapter12
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复旦课件-半导体器件-L03-MOSFET的基本特性
kT N B ln q ni
NB 增加 2 个数量级， VB 增加 0.12 V
VTn NMOS
VT / V
3.2 MOSFET的阈值电压8
3.2.3 影响 VT 的因素
3. 界面固定电荷 QSS 的影响 n 沟 MOS （NMOS） p 沟 MOS （PMOS）
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3.1 MOSFET的结构和工作原理4
3.1.2 MOSFET的结构
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3.1 MOSFET的结构和工作原理5
3.1.3 MOSFET的基本工作原理
ID 当 VG > VT 时 ID : 0
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B
3.1 MOSFET的结构和工作原理6
3.1.4 MOSFET 的分类和符号
NMOS
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3.2 MOSFET的阈值电压13
3.2.3 影响 VT 的因素
6. 衬底偏置效应 (衬偏效应，Body effect)
(2) MOSFET 的 VT
0 n+ VGS n+ EC EC EV EV VGS = VFB, VBS = 0 2qVB EC EC EV VGS = VT, VBS = 0 EV VGS = VT(VBS), VBS > 0 q |VBS| VGS = VFB, VBS > 0 q(2VB+ |VBS|)
接触电势差
功函数差
3.2 MOSFET的阈值电压3
3.2.2 阈值电压的表达式
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n 沟 MOS （NMOS）
VTn ms
Qss qN Ad max 2kT N A ln Cox Cox q ni
p 沟 MOS （PMOS）
蒋玉龙教授-半导体物理复习大纲
-Xp
nn0 n(x) p n0
Xn X
pp0 np0
-Xp Xn
nn0 pn0
X
pp0 np0
-Xp Xn
nn0 pn0
X 8/13
重要物理图象
p-n结中的电场和电势分布
Ε(x)
四种电流的动态平衡
-Xp
Xn
x
-x p
-
-
E
Εmax
++ ++ ++ ++
xn
中性区 P型
扩 耗 扩 散 尽 散 区 区 区
⎛ x − xn ⎞ ⎟ Δp( x) = Δp( xn ) exp⎜ − ⎜ L ⎟ p ⎠ ⎝
⎡ ⎛ qV ⎞ ⎤ Δp( xn ) = pn 0 ⎢exp⎜ ⎟ − 1⎥ ⎣ ⎝ kT ⎠ ⎦
n p0 ni2 = NA
n i2 ⎛ qDp ni2 qDn ni2 ⎞ ⎟ pn0 = + Js = ⎜ ⎜L N ND Ln N A ⎟ ⎝ p D ⎠
+ n p0 p p0 ⎡ ⎤⎫ ⎪ ⎛ qVs ⎞ qVs exp 1 − − ⎜ ⎟ ⎢ ⎥⎬ kT kT ⎝ ⎠ ⎣ ⎦⎪ ⎭
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欧姆 接触
11/13
重要物理图象
MIS电容的C－V特性
C C
i
V
’
C
C
i
V
12/13
重要物理图象
异质结的能带图
真空能级
χ1 W 1
E c1 EF 1 E g1 Ev1 ΔEc W2 χ 2 E c1 EF 2
C=
ε 0ε r
d
玻尔兹曼统计 耗尽近似
nn0 n(x) p n0
Xn X
pp0 np0
-Xp Xn
nn0 pn0
X
pp0 np0
-Xp Xn
nn0 pn0
X 8/13
重要物理图象
p-n结中的电场和电势分布
Ε(x)
四种电流的动态平衡
-Xp
Xn
x
-x p
-
-
E
Εmax
++ ++ ++ ++
xn
中性区 P型
扩 耗 扩 散 尽 散 区 区 区
⎛ x − xn ⎞ ⎟ Δp( x) = Δp( xn ) exp⎜ − ⎜ L ⎟ p ⎠ ⎝
⎡ ⎛ qV ⎞ ⎤ Δp( xn ) = pn 0 ⎢exp⎜ ⎟ − 1⎥ ⎣ ⎝ kT ⎠ ⎦
n p0 ni2 = NA
n i2 ⎛ qDp ni2 qDn ni2 ⎞ ⎟ pn0 = + Js = ⎜ ⎜L N ND Ln N A ⎟ ⎝ p D ⎠
+ n p0 p p0 ⎡ ⎤⎫ ⎪ ⎛ qVs ⎞ qVs exp 1 − − ⎜ ⎟ ⎢ ⎥⎬ kT kT ⎝ ⎠ ⎣ ⎦⎪ ⎭
1/ 2
欧姆 接触
11/13
重要物理图象
MIS电容的C－V特性
C C
i
V
’
C
C
i
V
12/13
重要物理图象
异质结的能带图
真空能级
χ1 W 1
E c1 EF 1 E g1 Ev1 ΔEc W2 χ 2 E c1 EF 2
C=
ε 0ε r
d
玻尔兹曼统计 耗尽近似
蒋玉龙教授-半导体物理ppt-10
在热平衡状态下的载流子浓度 n0, p0
⎛ Eg ⎞ 2 n0 p0 = Nc Nv exp⎜ ⎜ − kT ⎟ ⎟ = ni ⎝ ⎠
n=n0+Δn • Ec hν
⎞ ⎛ E f − Ev ⎞ ⎟ ⎟ p0 = Nv exp⎜ ⎜ − kT ⎟ ⎟ ⎠ ⎝ ⎠
外界作用（光、电等）破坏平衡态，产生 非平衡载流子
6.4 强电场下的输运2
6.4.1 欧姆定律的偏离和热载流子
强场下载流子的平均动能明显高于热平衡时的值 ⎯⎯ 热载流子 1o 热载流子受电离杂质散射弱，但声子散射（特别 是光学声子）可以很强； 2o 热载流子可以在等价或不等价能谷间转移.
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半导体物理
主讲人：蒋玉龙
微电子学楼312室，65643768 Email: yljiang@ http://10.14.3.121
22/24
6.4 强电场下的输运1
6.4.1 欧姆定律的偏离和热载流子
现象： 1－低场下 vd ∝ E 线性关系 2－中等强度电场 vd ∝ E1/2 亚线性关系 3－强场下 vd 饱和
q T=300K μ τ = 解释： m* 1o 低场下 vd <<v T ~ 107 cm/s， τ 决定于 v T ，与vd 无关，与 E 无关. 2o 中场下（E ≥ 103~4 V/cm）vd ~ v T τ 决定于 v T 和 vd， E↑ τ↓ μ↓ 3o 强场下，发射光学声子成为动量驰豫和能量驰豫的主要机制， 23/24 速度可以饱和
n = n0 + Δ n p = p0 + Δp Δ n = Δ p
小注入 n型 p型 p0 << Δn << n0 ⇒ n ≈ n0 p = Δp
复旦大学半导体器件原理讲义L04-小尺寸MOSFET的特性
DIBL 因子
4.1 MOSFET的短沟道效应和窄沟道效应15
4.1.5 漏感应势垒降低
2. 原因 (1) 电荷分享
18/74
2ε s (Vbi + VBS ) yS = qN A 2ε s (Vbi + VDS + VBS ) yD = qN A
⎧ x ⎡⎛ 2 y ⎞1 / 2 ⎤ Q ⎪ = 1 − ⎨ j ⎢⎜1 + S ⎟ − 1⎥ F= 2 L ⎢⎜ QB xj ⎟ ⎥ ⎪ ⎣⎝ ⎠ ⎦ ⎩ ⎡⎛ 2 y ⎞1 / 2 ⎤ ⎫ xj ⎪ + ⎢⎜1 + D ⎟ − 1⎥ ⎬ 2 L ⎢⎜ xj ⎟ ⎥⎪ ⎠ ⎣⎝ ⎦⎭ 1 yS + yD ≡ 1−α L 2
' B
ΔVT =
α ( y S + y D ) qε s N A (VB + 0.5VBS )
LCox
F↓ VT ↓
VDS ↑
4.1 MOSFET的短沟道效应和窄沟道效应16
4.1.5 漏感应势垒降低
2. 原因 (2) 电势的二维分布
19/74
导带边 Ec
特征长度
l=
ε s d max tox ηε ox
4.1.7 热载流子效应抑制-新型漏结构
1. 最大漏电场 Eymax 饱和时
1 E y max = (VDS − VDSsat ) 0.22tox/ 3 x1j / 3 tox 和 xj 均以 cm 为单位
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tox ↑ 降低 Eymax 措施
xj ↑
VDS ↓ VDD ↓ 新型漏结构 ⎯⎯ Graded pn junction
表面势
ΔVT =
sinh ( y l ) sinh[(L − y ) l ] Vs ( y ) = VsL + (Vbi + VDS − VsL ) + (Vbi − VsL ) sinh (L l ) sinh (L l ) [2(Vbi − 2VB ) + VDS ][exp(− L 2l ) + 2 exp(− L l )] VDS 很小
4.1 MOSFET的短沟道效应和窄沟道效应15
4.1.5 漏感应势垒降低
2. 原因 (1) 电荷分享
18/74
2ε s (Vbi + VBS ) yS = qN A 2ε s (Vbi + VDS + VBS ) yD = qN A
⎧ x ⎡⎛ 2 y ⎞1 / 2 ⎤ Q ⎪ = 1 − ⎨ j ⎢⎜1 + S ⎟ − 1⎥ F= 2 L ⎢⎜ QB xj ⎟ ⎥ ⎪ ⎣⎝ ⎠ ⎦ ⎩ ⎡⎛ 2 y ⎞1 / 2 ⎤ ⎫ xj ⎪ + ⎢⎜1 + D ⎟ − 1⎥ ⎬ 2 L ⎢⎜ xj ⎟ ⎥⎪ ⎠ ⎣⎝ ⎦⎭ 1 yS + yD ≡ 1−α L 2
' B
ΔVT =
α ( y S + y D ) qε s N A (VB + 0.5VBS )
LCox
F↓ VT ↓
VDS ↑
4.1 MOSFET的短沟道效应和窄沟道效应16
4.1.5 漏感应势垒降低
2. 原因 (2) 电势的二维分布
19/74
导带边 Ec
特征长度
l=
ε s d max tox ηε ox
4.1.7 热载流子效应抑制-新型漏结构
1. 最大漏电场 Eymax 饱和时
1 E y max = (VDS − VDSsat ) 0.22tox/ 3 x1j / 3 tox 和 xj 均以 cm 为单位
27/74
tox ↑ 降低 Eymax 措施
xj ↑
VDS ↓ VDD ↓ 新型漏结构 ⎯⎯ Graded pn junction
表面势
ΔVT =
sinh ( y l ) sinh[(L − y ) l ] Vs ( y ) = VsL + (Vbi + VDS − VsL ) + (Vbi − VsL ) sinh (L l ) sinh (L l ) [2(Vbi − 2VB ) + VDS ][exp(− L 2l ) + 2 exp(− L l )] VDS 很小
半导体工艺-复旦大学-蒋玉龙-Chapter 3
Discovery of MOS transistor (1928-1960)
Idea of J. Lilienfeld and his patent: “Device for controlling electric current” (Filed-March 25, 1928; patent issued-march 7,1933) MISFET structure of Lilienfeld: Al/Al2O3/CuS Substrate: CuS (semiconductor) CuS -4 mm) S D Dielectric gate: Al2O3 (10 Gate electrode: Al (100V) Al2O3 -4mm=107V/cm Electric field: 100V/10 Al (Close to the present Si MOSFET!) G
Low power dissipation
No current at static state ‘1’ or ‘0’ During VI: ‘1’→‘0’ PMOS Tr. turns on and provides a low impedance path to charge CL NMOS Tr. turns off and has a very high impedance *During VI: ‘0’→ ‘1’ NMOS Tr. turns on and provide a low impedance path to discharge CL PMOS Tr. turns off and very little supply current is added to the discharge current
Self-aligned twin well CMOS process
Idea of J. Lilienfeld and his patent: “Device for controlling electric current” (Filed-March 25, 1928; patent issued-march 7,1933) MISFET structure of Lilienfeld: Al/Al2O3/CuS Substrate: CuS (semiconductor) CuS -4 mm) S D Dielectric gate: Al2O3 (10 Gate electrode: Al (100V) Al2O3 -4mm=107V/cm Electric field: 100V/10 Al (Close to the present Si MOSFET!) G
Low power dissipation
No current at static state ‘1’ or ‘0’ During VI: ‘1’→‘0’ PMOS Tr. turns on and provides a low impedance path to charge CL NMOS Tr. turns off and has a very high impedance *During VI: ‘0’→ ‘1’ NMOS Tr. turns on and provide a low impedance path to discharge CL PMOS Tr. turns off and very little supply current is added to the discharge current
Self-aligned twin well CMOS process
蒋玉龙教授-半导体物理ppt-8
χ >> 1
n0 = N D
⎡ ⎤ 2χ n0 = N D ⎢ ⎥ 2 ⎢ ⎦ ⎣ χ +4 +χ⎥
⎛ χ2 + 4 − χ ⎞ ⎟ E f = ED + kT ln⎜ ⎟ ⎜ 4χ ⎠ ⎝
(3) 过渡区 （强电离区 → 本征激发） 需要考虑本征激发部分 n0 = p0 + N D ⎯⎯ 电中性条件 n0 p0 = ni2
n0 = p0 + N D
⎛ E f − Ei ⎞ N D = n0 − p0 = 2ni sinh⎜ ⎟ ⎜ kT ⎟ ⎠ ⎝
双曲正弦函数
⎛ ND ⎞ E f = Ei + kT sinh ⎜ ⎜ 2n ⎟ ⎟ ⎝ i⎠
−1
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5.4 杂质半导体中的载流子统计8
5.4.1 非补偿情形（单一杂质） －例子：n型半导体中的载流子浓度（不同温区的讨论）
n i = 4 . 82 × 10
15
⎛ m dn m dp ⎜ ⎜ m2 0 ⎝
⎞ ⎟ ⎟ ⎠
3 4
T
3/2
Eg ⎛ exp ⎜ ⎜ − 2 kT ⎝
⎞ ⎟ ⎟ ⎠
25/54
5.3 本征半导体中的载流子统计2
5.3.1 本征载流子浓度ni
n i = 4 . 82 × 10
15
⎛ m dn m dp ⎜ ⎜ m2 0 ⎝
⎛ EC − E f N C exp⎜ ⎜ − kT ⎝ ⎞ ND = ⎟ ⎟ ED − E f ⎞ ⎠ 1 + 2 exp⎛ − ⎜ ⎟ kT ⎝ ⎠
+ n0 = n D + p0
⎛ ED − E f NC ⎛ ΔE D ⎞ − exp⎜ − ⎟ ⋅ 2 exp⎜ ⎜ 2ND kT ⎝ kT ⎠ ⎝
复旦大学半导体物理课件1
课程简介2
参考书
1. Charles Kittel,《固体物理导论》，化学工业出版社 （2005） 2. 刘恩科，朱秉升，《半导体物理学》，国防工业出版社 （2003）. 3. 叶良修，《半导体物理学》，高等教育出版社（1987）. 4. R. M. Warner, B. L. Grung，《Semiconductor-Device Electronics》，电子工业出版社（2002）. 5. K. Seeger，《Physics of Semiconductor: An Introduction》，4th Ed. Springer-Verlag (2004). 6. 茹国平，《半导体物理讲义》（2007） 7. 陆昉，《半导体物理讲义》（2007）
K. Von Klitzing ：发现量子霍耳效应 Robert B. Laughlin, Daniel C. Tsui, Horst L. Stormer: 发现分数化量子 霍耳效应
Von Klitzing, Klaus 诺贝尔 诺贝尔
1998
1985
诺贝尔物理奖得主Klaus von Klitzing 受聘我校名誉教授
半 导 体
10 -4～ 10 10
L S
绝缘体
>10 10
10-6～ 10-4
L R=ρ S
ρ
二、半导体的主要特征: 电阻率可在很大范围内变化
例子：杂质对半导体电阻率的影响
硼 / 1百 万 0.2 磷 / 1百 万
硅
Ω cm
2x105
2x10 5
硅的纯度仍高达99.9999%
温度对半导体的影响
纯硅: T=300K ρ=2x 105 Ω cm T=320K ρ=2 x 104 Ω cm
蒋玉龙教授-半导体物理ppt-5
r r r = −q[(vyBγ − vzBβ)i +(vzBα − vxBγ ) j +(vxBβ −vyBα)k]
* x
* , , , , dv x * dv x i ω m v + qB γ v − qB β v v = v exp( i ω t ) x x y z =0 mx + qB ( v yγ − v z β ) = 0 x fx = m x dt dt , * , , , * dv y * dv y v = v exp( i ω t ) i ω m v + qB α v − qB γ v y y y z x =0 my f y = my + qB ( v zα − v xγ ) = 0 y dt dt * , , , , * dv z * dv z i ω m v + qB β v − qB α v v = v exp( i ω t ) z z x y =0 mz + qB ( v x β − v yα ) = 0 z fz = mz z dt dt
E
Bc =
ωm *
q
B Bc
23/32
3.3 回旋共振和等能面7
3.3.2 回旋共振
kz, k γ α kx，i B β ky, j
r r r r 各向异性晶体 B = B α i + B β j + B γ k
群速
r r r r v = vxi + vy j + vzk
r r r r r F = −qv × B = f xi + f y j + f zk
*
−1 2 1 dE ⎛ 1 d E⎞ * vg= ⎟ mn = ⎜ 2 2 ⎟ ⎜ h dk ⎝ h dk ⎠
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Ion Enhanced Etching
Mechanism of ion enhanced etching
(4) Importance of radicals:
Radical－atomic or molecular specie which is neutral but incompletely bonded, very reactive Example: Etching SiO2 by CF4 plasma e + CF4 → CF3 + F + e F, CF3－radicals
Ion induced etching:
Ion bombardment initiates chemical etching No etching without ions
Sidewall passivation: Stable films formed on sidewall due to lack of bombardment
2) SiO2 etching:
By F-based etchants (etching product---SiF4): CHF3 , CF4 + H2 , C2F6, C3F8，mixtures To get good selectivity over Si, need F-deficient plasma CF4 + H2 → F/C ratio↓ → Si etch rate ↓
Chapter 12 Dry Etching by Plasma Processing
Outline
I. Dry etching---one of the key technologies for VLSI/ULSI II. Plasma etching mechanisms III. Various plasma-etching reactors IV. Etching Anisotropy V. Dry etching for different materials VI. Contamination during Plasma Etching VII. Radiation Damage VIII.Endpoint Detection
V Dry etching for different materials
1) General etching process requirements: Feature profile Selectivity (SAB = EA/EB) Uniformity and Reproducibility Throughout Low contamination and damage
Patterning feature profile control－ Vital importance for VLSI/ULSI The degree of anisotropy of an etch process: RL A =1− RV
RL: lateral etch rate RV: vertical etch rate.
Sidewall film prevents etching by other isotropic etchant Sidewall film deposition: *By deposition of polymeric material from C-containing plasmas: －CF2－polymers
(3) Possible mechanisms of ion bombardment in etching process
Ions create damage/defects which catalyses chemical reaction
(See Fig.(a) below)
Ion bombardment directly dissociates reactant molecules Ion bombardment removes involatile residues that could inhibit etching (See Fig.(b) below)
2. Complex physical and chemical process during plasma/RIE 4 fundamentally different etching mechanisms:
Sputtering Chemical etching via plasma species →Isotropic etching Chemical/physical etching via reactive ion bombardment → Anisotropic etching Ion assisted or ion induced: Ion bombardment + chemical specie → Effective etching Usually no reaction of the etching gas or gas mixture without the presence of the plasma
Various reactors different in configurations, etching modes and power sources:
Barrel vs. Parallel Plate vs. Hexode Batch vs. Single Wafer Plasma vs. RIE Direct vs. Downstream RF vs. Microwave •High density plasma etcher--by Inductive coupled plasma (ICP)
3) Si3N4 etching:
Similar etchants with SiO2 +NF3 －better selectivity over SiO2 ( 9-10)
4) Si etching
Various etchants: (etching products:SiCl2 ,SiCl4, SiF2 , ) Cl2, CCl4, BCl3+Cl2, CFCl3,CF4+O2, SF6, NF3 or other Cl-containing mixture High selectivity required (for poly-Si gate): Cl-based plasma－very selective High anisotropy required: for trench isolation, DRAM capacitors
Components of plasma etching systems:
Etching chamber with electrodes Pumping system for establishing & maintaining processing gas pressure Pressure gauges to monitor pressure in the chamber Variable conductance between the pump and chamber for independent controlling pressure and flow rate Gas handling capability to test and control the flow of reactant gas Power source Process monitor and endpoint detector
IV Etching Anisotropy
Pure chemical reaction: Isotropic etching Ionic bombardment: Anisotropic etching
RIE and Plasma etching
Plasma etch: Wafer on grounded electrode ---less anisotropic RIE: Wafer on powered electrode ---more anisotropic
Perfect anisotropic etching not always desired (because metal continuity failure at steps, contacts, non-removal of residues…)
Non-vertical etch profiபைடு நூலகம்es: by using more isotropic etch (P↑→V↓) …
I Dry etching---one of the key technologies for VLSI/ULSI
Predominant dry etching technology—Plasma and Reaction Ion Etching (RIE) Etching process in gas plasma discharge (at 10-3-100 torr) Gaseous reactants Gaseous products Advantages: Anisotropic etching Formation of small-geometry device structure High density of reactive species available Environmentally less hazardous Other dry etching techniques: Ion beam enhanced etching Electron－beam enhanced etching Photon assisted etching Gas－phase etching: Anhydrous HF vapor
e + CF4 → CF3+ + F + 2e