基于Cadence的信号完整性仿真步骤
cadence信号完整性仿真步骤
IntroductionConsider the proverb, “It takes a village to raise a child.” Similarly, multiple design team members participate in assuring PCB power integrity (PI) as a design moves from the early concept phase to becoming a mature product. On the front end, there’s the electrical design engineer who is responsible for the schematic. On the back end, the layout designer handles physical implemen-tation. Typically, a PI analysis expert is responsible for overall PCB PI and steps in early on to guide the contributions of others. How quickly a team can assure PCB PI relates to the effectiveness of that team. In this paper, we will take a look at currently popular analysis approaches to PCB PI. We will also introduce a team-based approach to PCB PI that yieldsadvantages in resource utilization and analysis results.Common Power Integrity Analysis MethodsThere are two distinct facets of PCB PI – DC and AC. DC PI guarantees thatadequate DC voltage is delivered to all active devices mounted on a PCB (oftenusing IR drop analysis). This helps to assure that constraints are met for currentdensity in planar metals and total current of vias and also that temperatureconstraints are met for metals and substrate materials. AC PI concerns thedelivery of AC current to mounted devices to support their switching activitywhile meeting constraints for transient noise voltage levels within the powerdelivery network (PDN). The PDN noise margin (variation from nominalvoltage) is a sum of both DC IR drop and AC noise.DC PI is governed by resistance of the metals and the current pulled from thePDN by each mounted device. Engineers have, for many years, applied resistivenetwork models for approximate DC PI analysis. Now that computer speedsare faster and larger addressable memory is available, the industry is seeingmuch more application of layout-driven detailed numerical analysis techniquesfor DC PI. Approximation occurs less, accuracy is higher, and automation ofHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsBy Brad Brim, Sr. Staff Product Engineer, Cadence Design SystemsAssuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process.ContentsIntroduction (1)Common Power IntegrityAnalysis Methods (1)Applying a Team-Based Approachto Power Integrity Analysis (3)Summary (6)For Further Information (7)whole-design analysis and postprocessing results are commonly available commercially. In fact, DC PI analysis for PCB designs has become a “signoff” requirement for many OEMs. See Figure 1 (left) for typical results for current density.Since metal conductivity is temperature-dependent, DC IR drop is a nonlinear analysis. IR drop results can vary by more than 20% when temperature effects are considered, according to case studies for high-power designs. There is, however, a way to accurately characterize PCB IR drop while assuring that the PDN noise margin isn’twasted. Using a DC analysis tool that provides capabilities such as electrical/thermal co-simulation, perform a linear electrical analysis at ambient temperature; take the resulting power loss and apply it to perform a linear thermal analysis. Then, perform another linear electrical analysis with consideration of the localized temperature-dependent conductivity. This process converges in just a few iterations to yield a desired result. See Figure 1 for an illustration of this solution, as implemented in the Cadence ® Sigrity ™ PowerDC ™DC analysis tool.TemperatureLoss DensityPlane Current Surface TemperatureElectrical Analysis Thermal AnalysisFigure 1: Current density (left) and temperature distribution (right) for a PCB design due to DC powerdelivery as two linear solutions are iteratively linked to address nonlinear electro-thermal analysis.AC PI is governed by voltage regulator modules, loop inductances, decoupling capacitors (decaps), and plane capacitance. AC PI effects tend to be global in nature due to plane resonances, plane-to-plane coupling, and shared reference planes. As such, this calls for full-board analysis, as well as more resource-intensive analysis algorithms. A hybrid of circuit theory and electromagnetic (EM) analyses is the most commonly applied AC PI analysis for PCBs. This type of analysis is available in the frequency domain to extract S-parameters, using a tool such as Cadence Sigrity PowerSI ™ frequency-domain electrical analysis solution. It’s also available in the time domain to directly generate transient waveforms, using a tool such as Cadence Sigrity Speed2000™ time-domain analysis solution. With the proper tools, an engineer can, in tens of minutes, accurately characterize the PDNbehavior of even the largest and most complex PCBs from DC to multi-gigahertz using single- to low double-digit gigabytes of memory.Transient PI analysis may seem attractive because it directly yields noise waveforms; however, in reality, it is less commonly applied than frequency-domain impedance analysis. “Target impedance” profiles are applied as PIconstraints. Lower impedance corresponds to lower transient noise. Without direct vendor specification, reasonable target impedance may be estimated based on device specifications for voltage ripple and AC switching current. See Figure 2 for a comparison of frequency-domain and time-domain results. In this comparison, the Cadence Sigrity OptimizePI ™ tool was used to significantly reduce an impedance peak near 800MHz by applying an alternate set of decaps to mount for a DIMM module. This solution reduced peak-to-peak PDN noise for the optimized design by 12% and the component and manufacturing cost of the decap implementation by 21%.Figure 2: Impedance profile and transient PDN noise of a DIMM before and after thedecap implementation was optimized.Applying a Team-Based Approach to Power Integrity AnalysisTraditionally, PI experts have performed pre-layout decap selections and initial IR drop analyses. This is a substantial time investment at the front end of a design for a back-end-focused expert. By applying a more collaborative approach, a design team can make better use of its resources and expertise, and generate more impactful results.A team could set up simple analyses that yield actionable results and that could be performed by other members of the PI team. This PCB PI team would ideally consist of three key members: design engineer, layout designer, and PI analysis expert, as shown in Figure 3.Design Engineer•Can start with either BOM or schematic•Apply Power Feasibility Editor for DeCap selection and PIconstraint definitionLayout Designer•Can start as early asfloorplanning stage•First order analysis directlyon layout•Analyze, edit, re-analyze•DeCap placement guidanceand DRCPI Analysis Expert•Can start at any stage•Leverages setup and datafrom rest of team•Signoff capable detailedanalysisFigure 3: Roles and responsibilities of the PCB PI design team.There is now a tool available on the market that supports team-based PCB PI analysis. Cadence Allegro® SigrityPI is the industry’s first front-to-back, constraint-based PI approach for PCB and IC package designs. This tool differs from other solutions in the way that it accesses existing analysis algorithms and how the analysis resultsare applied. In addition, the tool also provides PI-focused infrastructure support of non-analysis tasks. As a result, design engineers and layout designers can contribute earlier and more effectively to PCB PI. The DC and AC PI analysis capabilities described in the previous section are available in the associated Power Integrity Signoff and Optimization Option.PCB design engineers are responsible for front-end tasks. They must generate an initial Bill of Materials (BOM)to set in motion cost feasibility studies and assure electrical design intent by generating circuit schematics. They typically work independently of DC PI concerns. However, to support AC PI, design engineers must add decaps and include them in the BOM and the schematic. Some device vendors provide datasheet guidance for decap selection (type and/or quantity), but many do not. Even with datasheet guidance, it is tedious for design engineers to assemble and interpret the specifications for each device, instantiate all the unique components, assure they appear logically in the schematic, etc. No mechanism has existed for physical placement guidance to be communicated for back-end application.With constraint-based design methods, engineers gain a uniform interface for design-intent information and for automating a broad class of tasks across front-to-back flows. PI [electrical] constraint sets (PI Csets) have been added to save all component-level PI information. Design engineers may apply PI Csets to quickly and completely define PI design intent for all mounted components. PI Csets also automate instantiation of components and inclusion in the BOM.Refer to Figure 4 for an example of a PI Cset in Allegro Sigrity PI. PI Csets contain information for each power rail, including decap component names, quantity of each component, package type, and physical placement guidance.Figure 4: PI constraint set contents viewed from the constraint manager.PI Cset creation is automated by the tool’s Power Feasibility Editor, which provides a mechanism to enter datasheet decap selection and physical placement guidance. Figure 5 shows a view of the tool’s Power Feasibility Editor. In addition to placement guidance, a PI Cset communicates to the layout designer component and power rail associ-ation for decaps, helping the designer perform more reliable placement.Figure 5: Single-point analysis results in the Power Feasibility Editor.The Power Feasibility Editor also provides access to approximate and detailed pre-layout analysis for selectionand placement of decaps. High-level specifications are made to generate target impedance profiles when device vendors do not provide them. An approximate PI analysis called “single-point” is provided for interactive decap selection. For more detailed pre-layout, the tool provides access to the data in the Cadence Sigrity OptimizePI tool. The engineer simply clicks a button within the Power Feasibility Editor to generate PI Csets.Figure 6: Split-screen view of layout (left) and IR drop analysis results (right).Unlike design engineers, layout designers are concerned with DC PI issues. Layout designers control metal shapes and vias and these, in turn, control PI behaviors for DC IR drop and current flow. Layout designers can intuitively understand and act upon analysis results for these DC PI effects. The Allegro Sigrity PI tool provides access within the layout environment to the setup and results display for DC IR drop and current constraint analyses. DC analysis is fast, though not conducted in real time in order to enable dynamic updating of analysis results as layout updates are made.The tool provides a split-screen view, as shown in Figure 6, to support a fixed view of analysis results as layout designers dynamically make updates to address IR drop or current constraint issues. The two views are synchro-nized for operations that affect the display, such as layer changes, zoom, and pan. Layout designers can apply this split-screen view of DC analysis results as they craft an initial layout, before the PI analysis expert gets involved.As a more effective method to communicate where PI issues exist in the design, the split-screen view can also be applied with detailed analysis results performed separately by PI analysis experts. In fact, to more quickly verify improved PI performance, the layout designer can launch the same detailed analysis performed by the PI analyst. Layout designers strongly influence AC PI success with their placement of decaps. Decaps placed close to a device generally benefit PI, but restrict routing channels due to decap mounting vias. Decaps placed too far from a device will be ineffective at providing switching current to the device and will negatively affect PI. Present design methods do not typically provide decap placement guidance, including information as simple as which device is associated with a decap. By conveying design intent, previously described PI Csets enable more effective placement of decaps by layout designers. The associated device and power rail and placement guidance are all specified in the PI Cset.A decap placement mode is implemented to support layout designers, as shown in Figure 7. Simply select a mounted component and a power rail, and then cycle through a point-and-click placement process. The selected device is highlighted and three optional visual placement guidance displays are available: device to decap distance for top layer, device to decap distance for bottom layer, and decap effective radius. The first two are defined in the PI Cset and are conceptually familiar. The decap effective radius is the maximum distance at which the decap will be maximally effective. It is a function of the stack-up and decap mounting parasitics as well as the decap value and its intrinsic parasitics. It is dynamically computed as the cursor moves due to local availability of metal shapes on the associated power and ground layers.Decap Placement GuidanceTop-sideSetbackDistance*DecapEffectiveRadiusBottom-sideSetbackDistanceFigure 7: Layout view during decap placement for device U0501 with top (yellow) and bottom (blue)setback distances and decap effective radius (white circle) displayedTo ease the setup for detailed PI analysis, design intent and analysis setup information specified by design engineers and layout designers is available to PI analysis. PI Csets serve as a convenient mechanism to communicate updated placement guidance or requirements for updates on decap selection (either type or quantity) for a specific device instance or all devices to which a PI Cset is applied. Changes to PI Csets also convey information back to the design engineer and enable automated update of the schematic and BOM.SummaryWhile current PCB PI analysis tools are continuing to serve the design community well, they are even more effective when combined with a front-to-back, constraint-based approach. Under this type of methodology, each design team member can more efficiently accomplish his or her individual tasks and communicate design intent infor-mation to colleagues for increased efficiency of the overall PCB design flow. This approach provides access toactionable analysis results where they are most impactful. It also leverages earlier defined analysis setup infor-mation for the PI expert, and eases communication of design changes from his or her back-end role to front-end colleagues.For Further InformationTo learn more about Cadence Allegro Sigrity PI solution, visit: /products/sigrity/Pages/ solution.aspxCadence Design Systems enables global electronic design innovation and plays an essential role in thecreation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to designand verify today’s mobile, cloud and connectivity applications. © 2014 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks and OptimizePI,PowerDC, PowerSI, Sigrity, and Speed2000 are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders.。
cadence信号完整性仿真步骤.
IntroductionConsider the proverb, “It takes a village to raise a child.” Similarly, multiple design team members participate in assuring PCB power integrity (PI as a design moves from the early concept phase to becoming a mature product. On the front end, there’s the electrical design engineer who is responsible for the schematic. On the back end, the layout designer handles physical implemen-tation. Typically, a PI analysis expert is responsible for overall PCB PI and steps in early on to guide the contributions of others. How quickly a team can assure PCB PI relates to the effectiveness of that team. In this paper, we will take a look at currently popular analysis approaches to PCB PI. We will also introduce a team-based approach to PCB PI that yieldsadvantages in resource utilization and analysis results.Common Power Integrity Analysis MethodsThere are two distinct facets of PCB PI – DC and AC. DC PI guarantees thatadequate DC voltage is delivered to all active devices mounted on a PCB (oftenusing IR drop analysis. This helps to assure that constraints are met for currentdensity in planar metals and total current of vias and also that temperatureconstraints are met for metals and substrate materials. AC PI concerns thedelivery of AC current to mounted devices to support their switching activitywhile meeting constraints for transient noise voltage levels within the powerdelivery network (PDN. The PDN noise margin (variation from nominalvoltage is a sum of both DC IR drop and AC noise.DC PI is governed by resistance of the metals and the current pulled from thePDN by each mounted device. Engineers have, for many years, applied resistivenetwork models for approximate DC PI analysis. Now that computer speedsare faster and larger addressable memory is available, the industry is seeingmuch more application of layout-driven detailed numerical analysis techniquesfor DC PI. Approximation occurs less, accuracy is higher, and automation ofHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsBy Brad Brim, Sr. Staff Product Engineer, Cadence Design SystemsAssuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process.ContentsIntroduction . (1)Common Power IntegrityAnalysis Methods . (1)Applying a Team-Based Approachto Power Integrity Analysis . (3)Summary (6)For Further Information . (7)whole-design analysis and postprocessing results are commonly available commercially. In fact, DC PI analysis for PCB designs has become a “signoff” requirement for many OEMs. See Figure 1 (left for typical results for current density.Since metal conductivity is temperature-dependent, DC IR drop is a nonlinear analysis. IR drop results can vary by more than 20% when temperature effects are considered, according to case studies for high-power designs. There is, however, a way to accurately characterize PCB IR drop wh ile assuring that the PDN noise margin isn’twasted. Using a DC analysis tool that provides capabilities such as electrical/thermal co-simulation, perform a linear electrical analysis at ambient temperature; take the resulting power loss and apply it to perform a linear thermal analysis. Then, perform another linear electrical analysis with consideration of the localized temperature-dependent conductivity. This process converges in just a few iterations to yield a desired result. See Figure 1 for an illustration of this solution, as implemented in the Cadence® Sigrity™ PowerDC™DC analysis tool.TemperatureLoss DensityPlane CurrentSurface TemperatureElectrical AnalysisThermal AnalysisFigure 1: Current density (left and temperature distribution (right for a PCB design due to DC powerdelivery as two linear solutions are iteratively linked to address nonlinear electro-thermal analysis.AC PI is governed by voltage regulator modules, loop inductances, decoupling capacitors (decaps, and plane capacitance. AC PI effects tend to be global in nature dueto plane resonances, plane-to-plane coupling, and shared reference planes. As such, this calls for full-board analysis, as well as more resource-intensive analysis algorithms. A hybrid of circuit theory and electromagnetic (EM analyses is the most commonly applied AC PI analysis for PCBs. This type of analysis is available in the frequency domain to extract S-parameters, using a tool such as Cadence Sigrity PowerSI™ frequency-domain electrical analysis solution. It’s also available in the time domain to directly generate transient waveforms, using a tool such as Cadence Sigrity Speed2000™ time-domain analysis solution. With the proper tools, an engineer can, in tens of minutes, accurately characterize the PDNbehavior of even the largest and most complex PCBs from DC to multi-gigahertz using single- to low double-digit gigabytes of memory.Transient PI analysis may seem attractive because it directly yields noise waveforms; however, in reality, it is less commonly applied than frequency-domain impedance analysis. “Target impedance” profiles are applied as PIconstraints. Lower impedance corresponds to lower transient noise. Without direct vendor specification, reasonable target impedance may be estimated based on device specifications for voltage ripple and AC switching current. See Figure 2 for a comparison of frequency-domain and time-domain results. In this comparison, the Cadence Sigrity OptimizePI ™ tool was used to significantly reduce an impedance peak near 800MHz by applying an alternate set of decaps to mount for a DIMM module. This solution reduced peak-to-peak PDN noise for the optimized design by 12% and the component and manufacturing cost of the decap implementation by 21%. 2How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsFigure 2: Impedance profile and transient PDN noise of a DIMM before and after thedecap implementation was optimized.Applying a Team-Based Approach to Power Integrity AnalysisTraditionally, PI experts have performed pre-layout decap selections and initial IR drop analyses. This is a substantial time investment at the front end of a design for a back-end-focused expert. By applying a more collaborativeapproach, a design team can make better use of its resources and expertise, and generate more impactful results.A team could set up simple analyses that yield actionable results and that could be performed by other members of the PI team. This PCB PI team would ideally consist ofthree key members: design engineer, layout designer, and PI analysis expert, as shown in Figure 3.Design Engineer•Can start with either BOM or schematic•Apply Power Feasibility Editor for DeCapselection and PIconstraint definitionLayout Designer•Can start as early as floorplanning stage •First order analysis directly on layout•Analyze, edit, re-analyze•DeCap placement guidanceand DRCPI Analysis Expert•Can start at any stage•Leverages setup and data from rest of team•Signoff capable detailed analysis Figure 3: Roles and responsibilities of the PCB PI design team. 3How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsThere is now a tool available on the market that supports team-based PCB PI analysis. Cadence A llegro® Sigrity PI is the industry’s first front-to-back, constraint-based PI approach for PCB and IC package designs. This tool differs from other solutions in the way that it accesses existing analysis algorithms and how the analysis results are applied. In addition, the tool also provides PI-focused infrastructure support of non-analysis tasks. As a result, design engineers and layout designers can contribute earlierand more effectively to PCB PI. The DC and AC PI analysis capabilities described in the previous section are available in the associated Power Integrity Signoff and Optimization Option.PCB design engineers are responsible for front-end tasks. They must generate an initial Bill of Materials (BOM to set in motion cost feasibility studies and assure electrical design intent by generating circuit schematics. They typically work independently of DC PI concerns. However, to support AC PI, design engineers must add decaps and include them in the BOM and the schematic. Some device vendors provide datasheet guidance for decap selection (type and/or quantity, but many do not. Even with datasheet guidance, it is tedious for design engineers toassemble and interpret the specifications for each device, instantiate all the unique components, assure they appear logically in the schematic, etc. No mechanism has existed for physical placement guidance to be communicated for back-end application.With constraint-based design methods, engineers gain a uniform interface for design-intent information and for automating a broad class of tasks across front-to-back flows. PI [electrical] constraint sets (PI Csets have been added to save all component-level PI information. Design engineers may apply PI Csets to quickly and completely define PI design intent for all mounted components. PI Csets also automate instantiation of components and inclusion in the BOM.Refer to Figure 4 for an example of a PI Cset in Allegro Sigrity PI. PI Csets contain information for each power rail,including decap component names, quantity of each component, package type, and physical placement guidance.Figure 4: PI constraint set contents viewed from the constraint manager.PI Cset creation is automated by the tool’s Power Feasibility Editor, which providesa mechanism to enter datasheet decap selection and physical placement guidance. Figure5 shows a view of the tool’s Power Feasibility Editor. In addition to placement guidance,a PI Cset communicates to the layout designer component and power rail associ-ation for decaps, helping the designer perform more reliable placement. 4How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsFigure 5: Single-point analysis results in the Power Feasibility Editor.The Power Feasibility Editor also provides access to approximate and detailed pre-layout analysis for selection and placement of decaps. High-level specifications are made to generate target impedance profiles when device vendors do not provide them. An approximate PI analysis called “single-point” is provided for interactive decap selection. For more detailed pre-layout, the tool provides access to the data in the Cadence Sigrity OptimizePI tool.The engineer simply clicks a button within the Power Feasibility Editor to generate PI Csets.Figure 6: Split-screen view of layout (left and IR drop analysis results (right.Unlike design engineers, layout designers are concerned with DC PI issues. Layout designers control metal shapes and vias and these, in turn, control PI behaviors for DC IR drop and current flow. Layout designers can intuitively understand and act upon analysis results for these DC PI effects. The Allegro Sigrity PI tool provides access within the layout environment to the setup and results display for DC IR drop and current constraint analyses. DC analysis is fast, though not conducted in real time in order to enable dynamic updating of analysis results as layout updates are made. 5How a Team-Based Approach to PCB Power Integrity Analysis Yields Better ResultsHow a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results The tool provides a split-screen view, as shown in Figure 6, to support a fixedview of analysis results as layout designers dynamically make updates to address IR drop or current constraint issues. The two views are synchronized for operations that affect the display, such as layer changes, zoom, and pan. Layout designers can apply this split-screen view of DC analysis results as they craft an initial layout, before the PI analysis expert gets involved. As a more effective method to communicate where PI issues exist in the design, the split-screen view can also be applied with detailed analysis results performed separately by PI analysis experts. In fact, to more quickly verify improved PI performance, the layout designer can launch the same detailed analysis performed by the PI analyst. Layout designers strongly influence AC PI success with their placement of decaps. Decaps placed close to a device generally benefit PI, but restrict routing channels due to decap mounting vias. Decaps placed too far from a device will be ineffective at providing switching current to the device and will negatively affect PI. Present design methods do not typically provide decap placement guidance, including information as simple as which device is associated with a decap. By conveying design intent, previously described PI Csets enable more effective placement of decaps by layout designers. The associated device and power rail and placement guidance are all specified in the PI Cset. A decap placement mode is implemented to support layout designers, as shown in Figure 7. Simply select a mounted component and a power rail, and then cycle through a point-and-click placement process. The selected device is highlighted and three optional visual placement guidance displays are available: device to decap distance for top layer, device to decap distance for bottom layer, and decap effective radius. The first two are defined in the PI Cset and are conceptually familiar. The decap effective radius is the maximum distance at which the decap will be maximally effective. It is a function of the stack-up and decap mounting parasitics as well as the decap value and its intrinsic parasitics. It is dynamically computed as the cursor moves due to local availability of metal shapes on the associated power and ground layers. Decap Placement Guidance Top-side Setback Distance * Decap Effective Radius Bottom-side Setback Distance Figure 7: Layout view during decap placement for device U0501 with top (yellow andbottom (blue setback distances and decap effective radius (white circle displayed To ease the setup for detailed PI analysis, design intent and analysis setup information specified by design engineers and layout designers is available to PI analysis. PI Csets serve as a convenient mechanism to communicate updated placement guidance or requirements for updates on decap selection (either type or quantity for a specific device instance or all devices to which a PI Cset is applied. Changes to PI Csets also convey information back to the design engineer and enable automated update of the schematic and BOM. Summary While current PCB PI analysis tools are continuing to serve the design community well, they are even more effective when combined with a front-to-back, constraint-based approach. Under this type of methodology, each design team member can more efficiently accomplish his or her individual tasks and communicate design intent information to colleagues for increased efficiency of the overall PCB design flow. This approach provides access to 6How a Team-Based Approach to PCB Power Integrity Analysis Yields Better Results actionable analysis results where they are most impactful. It also leverages earlier defined analysis setup information for the PI expert, and eases communication of design changes from his or her back-end role to front-end colleagues. For Further Information To learn more about Cadence Allegro Sigrity PI solution, visit:/products/sigrity/Pages/ solution.aspx Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today’s electronics. Customers use Cadence software, hardware, IP, and expertise to design and verify to day’s mobile, cloud and connectivity applications. © 2014 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks and OptimizePI, PowerDC, PowerSI, Sigrity, and Speed2000 are trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 1932 01/14 CY/DM/PDF。
allegro SI 信号完整性仿真介绍
基于Cadence Allegro SI 16.3的信号完整性仿真信号完整性是指信号在信号线上的质量。
信号具有良好的信号完整性是指当在需要的时候，具有所必需达到的电压电平数值。
差的信号完整性不是由某一因素导致的，而是由板级设计中多种因素共同引起的。
特别是在高速电路中，所使用的芯片的切换速度过快、端接元件布设不合理、电路的互联不合理等都会引起信号的完整性问题。
具体主要包括串扰、反射、过冲与下冲、振荡、信号延迟等。
信号完整性问题由多种因素引起，归结起来有反射、串扰、过冲和下冲、振铃、信号延迟等，其中反射和串扰是引发信号完整性问题的两大主要因素。
反射和我们所熟悉的光经过不连续的介质时都会有部分能量反射回来一样，就是信号在传输线上的回波现象。
此时信号功率没有全部传输到负载处，有一部分被反射回来了。
在高速的PCB中导线必须等效为传输线，按照传输线理论，如果源端与负载端具有相同的阻抗，反射就不会发生了。
如果二者阻抗不匹配就会引起反射，负载会将一部分电压反射回源端。
根据负载阻抗和源阻抗的关系大小不同，反射电压可能为正，也可能为负。
如果反射信号很强，叠加在原信号上，很可能改变逻辑状态，导致接收数据错误。
如果在时钟信号上可能引起时钟沿不单调，进而引起误触发。
一般布线的几何形状、不正确的线端接、经过连接器的传输及电源平面的不连续等因素均会导致此类反射。
另外常有一个输出多个接收，这时不同的布线策略产生的反射对每个接收端的影响也不相同，所以布线策略也是影响反射的一个不可忽视的因素。
串扰是相邻两条信号线之间的不必要的耦合，信号线之间的互感和互容引起线上的噪声。
因此也就把它分为感性串扰和容性串扰，分别引发耦合电流和耦合电压。
当信号的边沿速率低于1ns时，串扰问题就应该考虑了。
如果信号线上有交变的信号电流通过时，会产生交变的磁场，处于磁场中的相邻的信号线会感应出信号电压。
一般PCB板层的参数、信号线间距、驱动端和接收端的电气特性及信号线的端接方式对串扰都有一定的影响。
用Cadence进行信号完整性
用Cad ence进行信号完整性(SI)仿真流程第一章在Allegro 中准备好进行SI 仿真的PCB 板图1）在Cadence 中进行SI 分析可以通过几种方式得到结果：Allegro 的PCB 画板界面，通过处理可以直接得到结果，或者直接以*.brd 存盘。
使用SpecctreQuest 打开*.brd，进行必要设置，通过处理直接得到结果。
这实际与上述方式类似，只不过是两个独立的模块，真正的仿真软件是下面的SigXplore 程序。
直接打开SigXplore 建立拓扑进行仿真。
2）从PowerPCB 转换到Allegro 格式在PowerPCb 中对已经完成的PCB 板，作如下操作：在文件菜单，选择Export 操作，出现File Export 窗口，选择ASCII 格式*.asc 文件格式，并指定文件名称和路径（图1.1）。
图1.1 在PowerPCB 中输出通用ASC 格式文件图1.2 PowerPCB 导出格式设置窗口点击图1.1 的保存按钮后出现图1.2 ASCII 输出定制窗口，在该窗口中，点击“Select All”项、在Expand Attributes 中选中Parts 和Nets 两项，尤其注意在Format 窗口只能选择PowerPCB V3.0 以下版本格式，否则Allegro 不能正确导入。
3）在Allegro 中导入*.ascPCB 板图在文件菜单，选择Import 操作，出现一个下拉菜单，在下拉菜单中选择PADS 项，出现PADS IN 设置窗口（图1.3），在该窗口中需要设置3 个必要参数：图1.3 转换阿三次文件参数设置窗口i. 在的一栏那填入源asc 文件的目录ii. 在第二栏指定转换必须的pads_in.ini 文件所在目录（也可将此文件拷入工作目录中，此例）iii. 指定转换后的文件存放目录然后运行“Run”，将在指定的目录中生成转换成功的.brd 文件。
CADENCE仿真流程
CADENCE仿真流程1.设计准备在进行仿真之前，需要准备好设计的原理图和布局图。
原理图是电路的逻辑结构图，布局图是电路的物理结构图。
此外，还需要准备好电路的模型、方程和参数等。
2.确定仿真类型根据设计需求，确定仿真类型，包括DC仿真、AC仿真、时域仿真和优化仿真等。
DC仿真用于分析直流电路参数，AC仿真用于分析交流电路参数，而时域仿真则用于分析电路的时间响应。
3.设置仿真参数根据仿真类型，设置仿真参数。
例如，在DC仿真中，需要设置电压和电流源的数值；在AC仿真中，需要设置信号源的频率和幅度；在时域仿真中，需要设置仿真的时间步长和仿真时间等。
4.模型库选择根据设计需求，选择合适的元件模型进行仿真。
CADENCE提供了大量的元件模型，如晶体管、二极管、电感、电容等。
5.确定分析类型根据仿真目标，确定分析类型，例如传输功能分析、噪声分析、频率响应分析等。
6.仿真运行在仿真运行之前，需要对电路进行布局和连线。
使用CADENCE提供的工具对电路进行布局和连线，并生成物理设计。
7.仿真结果分析仿真运行后，CADENCE会生成仿真结果。
利用CADENCE提供的分析工具对仿真结果进行分析，观察电路的性能指标。
8.优化和修改根据仿真结果，对电路进行优化和修改。
根据需要，可以调整电路的拓扑结构、参数和模型等，以改进电路的性能。
9.再次仿真和验证根据修改后的电路，再次进行仿真和验证，以确认电路的性能指标是否得到改善。
最后需要注意的是，CADENCE仿真流程并不是一成不变的，根据具体的设计需求和仿真目标，流程可能会有所调整和修改。
此外，CADENCE还提供了许多其他的工具和功能，如电路板设计、封装设计、时序分析等，可以根据需要进行使用。
Cadence SI信号完整性仿真技术
Cadence PCB SI仿真流程——孙海峰高速高密度多层PCB板的SI/EMC(信号完整性/电磁兼容)问题长久以来一直是设计者所面对的最大挑战。
然而，随着主流的MCU、DSP和处理器大多工作在100MHz以上(有些甚至工作于GHz级以上)，以及越来越多的高速I/O埠和RF前端也都工作在GHz级以上，再加上应用系统的小型化趋势导致的PCB 空间缩小问题，使得目前的高速高密度PCB板设计已经变得越来越普遍。
许多产业分析师指出，在进入21世纪以后，80%以上的多层PCB设计都将会针对高速电路。
高速讯号会导致PCB板上的长互连走线产生传输线效应，它使得PCB设计者必须考虑传输线的延迟和阻抗搭配问题，因为接收端和驱动端的阻抗不搭配都会在传输在线产生反射讯号，而严重影响到讯号的完整性。
另一方面，高密度PCB板上的高速讯号或频率走线则会对间距越来越小的相邻走线产生很难准确量化的串扰与EMC问题。
SI和EMC的问题将会导致PCB设计过程的反复，而使得产品的开发周期一再延误。
一般来说，高速高密度PCB需要复杂的阻抗受控布线策略才能确保电路正常工作。
随着新型组件的电压越来越低、PCB板密度越来越大、边缘转换速率越来越快，以及开发周期越来越短，SI/EMC挑战便日趋严峻。
为了达到这个挑战的要求，目前的PCB设计者必须采用新的方法来确保其PCB设计的可行性与可制造性。
过去的传统设计规则已经无法满足今日的时序和讯号完整性要求，而必须采取包含仿真功能的新款工具才足以确保设计成功。
Cadence的Allegro PCB SI提供了一种弹性化且整合的信号完整性问题解决方案，它是一种完整的SI/PI(功率完整性)/EMI问题的协同解决方案，适用于高速PCB设计周期的每个阶段，并解决与电气性能相关的问题。
Allegro PCB SI信号完整性分析的操作步骤，就是接下来将要介绍的。
一、Allegro PCB SI分析前准备：1、准备需要分析的PCB，如下图；2、SI分析前的相关设置，执行T ools/Setup Advisor,进入Database Setup Advisor 对话框，进行SI分析前的设置；（1）设置PCB叠层的材料、阻抗等，点击Edit Cross section，进入叠层阻抗等设置界面。
CADENCE仿真步骤
CADENCE仿真步骤
Cadence是一款电路仿真软件，它可以帮助设计师创建、分析和仿真
电子电路。
本文将介绍Cadence仿真的步骤。
1.准备仿真结构：第一步是准备仿真结构。
我们需要编写表示电路的Verilog或VHDL代码，然后将它们编译到Cadence Integrated Circuit (IC) Design软件中。
这会生成许多文件，包括netlist和verilog等文件，这些文件将用于仿真。
2.定义仿真输入输出信号：接下来，我们需要定义仿真的输入信号和
输出信号。
输入信号可以是电压、电流、时间和其他可测量的变量。
我们
需要定义输入信号的模拟和数字值，以及输出信号的模拟和数字值。
3.定义参数：参数是仿真中用于定义仿真设计的变量，这些变量可以
是仿真中电路的物理参数，如电阻、电容、时延、输入电压等，也可以是
算法参数，如积分步长等。
4.运行仿真：在所有参数和信号都设置完成后，我们可以运行仿真。
在运行仿真之前，可以使用自动参数检查来检查参数是否正确。
然后，使
用“开始仿真”命令即可启动仿真进程。
5.结果分析：在仿真结束后，我们可以使用结果分析器来查看输出信
号的模拟和数字值，以及仿真中电路的其他特性，如暂态分析、稳态分析、功率分析等。
以上就是Cadence仿真步骤。
基于Cadence软件高速PCB设计的信号完整性仿真
基于Cadence软件高速PCB设计的信号完整性仿真
邓素辉;谭子诚;鄢秋荣;刘明萍;周辉林
【期刊名称】《实验室研究与探索》
【年(卷),期】2017(036)012
【摘要】基于Cadence软件的PCB SI工具,对高速PCB信号完整性常见问题中的反射和串扰进行了仿真分析.演示了具体的仿真步骤,给出了仿真波形.仿真结果表明,使用不同的端接匹配方式实现了信号反射问题的改善,使用改变线间距的方法减少了信号串扰.直观的展示了PCB仿真设计能够改善信号完整性问题,可用于EDA 设计的本科教学实验演示.
【总页数】5页(P116-120)
【作者】邓素辉;谭子诚;鄢秋荣;刘明萍;周辉林
【作者单位】南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031
【正文语种】中文
【中图分类】TN41
【相关文献】
1.基于信号完整性的高速PCB设计方法 [J], 王婷
2.高速PCB设计中信号完整性的仿真与分析 [J], 肖汉波
3.基于信号完整性的高速数据采集存储器PCB设计与仿真 [J], 王乐;裴东兴;崔春
生
4.基于Cadence_Allegro的高速PCB设计信号完整性分析与仿真 [J], 覃婕;阎波;林水生
5.基于信号完整性分析的高速PCB设计 [J], 梁龙
因版权原因，仅展示原文概要，查看原文内容请购买。
基于Cadence软件高速PCB设计的信号完整性仿真
基于Cadence软件高速PCB设计的信号完整性仿真邓素辉;谭子诚;鄢秋荣;刘明萍;周辉林【摘要】The common signal integrity (SI) problems of signal reflection and crosstalk in high-speed PCB were studied by using the analysis tool of PCB SI in the Cadence software.The simulation steps were given in detail and the waveforms of the simulation were shown.The results show that several methods of termination matching can be applied to solve the reflection problems.Adjusting the line spacing can effectively reduce the signal crosstalk phenomenon.The improvements of signal integrity in PCB were displayed obviously,the method is very helpful in undergraduates' teaching of the EDA design.%基于Cadence软件的PCB SI工具,对高速PCB信号完整性常见问题中的反射和串扰进行了仿真分析.演示了具体的仿真步骤,给出了仿真波形.仿真结果表明,使用不同的端接匹配方式实现了信号反射问题的改善,使用改变线间距的方法减少了信号串扰.直观的展示了PCB仿真设计能够改善信号完整性问题,可用于EDA设计的本科教学实验演示.【期刊名称】《实验室研究与探索》【年(卷),期】2017(036)012【总页数】5页(P116-120)【关键词】高速PCB;信号完整性;反射;串扰【作者】邓素辉;谭子诚;鄢秋荣;刘明萍;周辉林【作者单位】南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031;南昌大学信息工程学院,南昌330031【正文语种】中文【中图分类】TN410 引言随着电子产品朝着高速率、高密度、小体积的方向发展，电子系统设计领域已经进入GHz及以上的设计领域。
Cadence-SI-Simulation
Cadence仿真介绍第一部分：仿真流程第二部分：IBIS模型IBIS模型和SPICE模型比较：SPICE模型：（1）电压/电流/时间等关系从器件图形、材料特性得来，建立在低级数据的基础上（2）每个buffer中的器件分别描述/仿真（3）仿真速度很慢（4）包含芯片制造工艺信息IBIS模型：（1）电压/电流/时间关系建立在IV/VT数据曲线上（2）没有包括电路细节（3）仿真速度快，是SPICE模型的25倍以上（4）不包含芯片内部制造工艺信息基于上述原因，对于在系统级的设计，我们更倾向于使用IBIS模型。
目前IBIS主要使用的有V1.1，V2.1，V3.2及V4.0等版本。
模型结构如下图：C_pkg，R_pkg，L_pkg为封装参数；C_comp为晶片pad电容；Power_Clamp，GND_Clamp 为ESD结构的V/I曲线。
输出模型比输入模型多一个pull-up，pull-down的V/T曲线。
Cadence的model integrity工具负责对IBIS模型进行语法检查、编辑以及进行DML格式转换。
Cadence仿真不直接使用IBIS模型，而必须先把IBIS转换成DML。
<实例操作演示>第三部分：电路板设置电路板设置包括：（1）叠层设置；（2）DC电压设置；（3）器件设置；（4）模型分配；上述步骤可以通过setup advisor向导设置。
1，叠层设置2，DC电压设置3，器件设置4，模型分配电阻、电容、电感等无源器件的模型可以通过建立ESPICE模型来获得。
<实例操作演示>第四部分：设置仿真参数模型分配完成后，就可以进行仿真了。
在进行仿真之前，需要对仿真的参数进行设置。
Pulse cycle count：通过指定系统传输的脉冲数目来确定仿真的持续时间。
Pulse Clock Frequency：确定仿真中用来激励驱动器的脉冲电压源的频率。
Pulse Duty cycle：脉冲占空比。
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目录1.仿真前的准备工作 (2)1.1找到需要仿真的芯片的IBIS模型 (2)1.2模型转换（IBIS→DML） (2)1.3添加模型到Cadence的模型库中 (5)2. 对电路板进行设置（Setup Advisor） (7)2.1准备好要仿真的电路板 (7)2.2调用参数设置向导 (7)2.3叠层设置 (8)2.4设置DC电压值 (9)2.5器件设置（Device Setup） (10)2.6 SI模型分配 (12)2.7 SI检查（SI Audit） (16)2.8完成参数设置 (18)3.进行信号完整性仿真（反射） (19)3.1开始仿真 (19)3.2选择所要仿真的网络 (19)3.3提取网络的拓扑结构 (20)3.4给驱动端U8添加激励信号 (21)3.5设置激励信号的参数 (22)3.6执行反射仿真 (22)3.7仿真结果 (22)1.仿真前的准备工作1.1找到需要仿真的芯片的IBIS模型一般可以从芯片制造商网站上找到，如果没有，可能要通过其它途径获得如从SPICE模型中提取。
1.2模型转换 （IBIS→DML）将IBIS模型转换为DML模型，运用Cadence的Model Integrity工具将IBIS模型转化为Cadence能识别的DML模型，并验证仿真模型。
（1）单击“开始”按钮→“所有程序”→“Allegro SPB 15.5”→“Model Integrity”，如图1-1所示：图1-1 Model Integrity工具窗口（2）选择“File”→“Open”，打开一个IBIS模型如图1-2所示：图1-2 打开一个IBIS模型（3）在“Physical View”栏中，单击IBIS文件“sn74avca16245”→选择菜单栏里的“Options”→“Translation Options Editor”→弹出“Translation Options”窗口，如图1-3所示：图1-3 Translation Options窗口（4）默认选择“Make model names unique”，这个设置为每个IOCell模型名附加IBIS文件名。
单击“OK”，关闭“Translation Options”窗口。
（5）在“Physical View”栏中，单击IBIS文件“sn74avca16245”→单击鼠标右键→选择“IBIS to DML”（如图1-4所示）,系统会提示是否重写→选择“是”（如图1-5所示），重写文档。
这时在原先IBIS文件的目录下面会生成相应的DML模型（如图1-6所示）。
图1-4 IBIS→DML转换窗口图1-5 模型转换提示框图1-6 转换好的DML模型1.3添加模型到Cadence的模型库中将转换好的DML模型加载到Cadence的模型库中，在Allegro PCB SI 610中，选择“Analyze”→“SI/EMI Sim”→“Library”，如图1-7所示。
窗口分上下两个部分，上半部分是器件模型库；下半部分是互连模型库，包括传输线模型和Via模型。
当提取网络的拓扑结构时，互连模型会自动创建。
这里主要是加载器件的模型。
图1-7将DML模型加载到Cadence的模型库中在这里要完成两项工作：（1） 把所用到的模型加到模型库中。
选择“Add existing library”→“Local Library”,如图1-8所示：图1-8 添加模型（单个）选择相应的模型后，选择“打开”，这种方法只能一个一个的添加。
如果要添加的模型比较多可以选择“Add existing library”→“Local Library Path”，如图1-9所示：图1-9添加模型（批量）选择模型所在的文件夹，选择“OK”，这样整个文件夹中的模型都会添加到模型库中。
（2） 创建自己的库文件，以后本次仿真新创建的信号模型如电阻、电容的模型会自动保存到该库文件中。
选择“Create new library”，如图1-10所示：图1-10 Create new library窗口输入文件名，选择保存路径后，选择“保存”。
新建的库也会被添加到模型库中。
2.对电路板进行设置（Setup Advisor）下面以UL2项目的PCB板为例介绍，对其中的地址信号A15进行信号完整性仿真。
2.1准备好要仿真的电路板用Allegro PCB SI 610打开UL2的PCB板—BE7366MS01-11-9.brd。
如图2-1所示：图2-1 UL2的PCB板图2.2调用参数设置向导选择“Tools”→“Setup Advisor”，弹出“Database Setup Advisor”窗口，如图2-2所示：图2-2 Database Setup Advisor窗口2.3叠层设置进行叠层设置，确定电路板层面，包括每层的材料、类型、名称、厚度、线宽和阻抗信息，并确定PCB的物理和电气特性。
（1） 在图2-2中，单击“Next”弹出“Database Setup Advisor-Cross_section”窗口，如图2-3所示：图2-3 Database Setup Advisor-Cross_section窗口（2） 单击“Edit Cross-section”弹出“Layout Cross Section”窗口，如图2-4所示：图2-4 Layout Cross Section窗口在系统中，整个电路板的厚度是一个固定值，所以不要改变它。
在这里可以设置每一层的厚度，层面的类型，绝缘层的介电常数，线宽等等，并能计算出相应的特性阻抗值。
¾Mode 当“Differential Mode”被选择时，线宽、阻抗、差分阻抗、差分间距、差分耦合的模式都是相关联的。
根据改变的值，编辑器都会弹出菜单，允许进一步进行准确设置。
¾Material 从下拉菜单中选择材料。
¾Loss Tangent 根据绝缘层的功率因数补偿角的正切，指定当前选择的绝缘层的介电损失。
¾Type 层面的类型，包含SURFACE、CONDUCTOR、DIELECTRIC、PLANE等。
¾Thickness 分配给每个层的厚度。
¾Line Width 确定布线层的布线宽度。
¾Impedance 分配给每个层的阻抗。
参数设置完成后，单击“OK”，关闭“Layout Cross Section”窗口。
“Database Setup Advisor”窗口将再次显示。
2.4设置DC电压值（1）点击“Next”弹出“Data Setup Advisor -DC Nets”窗口，如图2-5所示：图2-5 Data Setup Advisor -DC Nets窗口（2）单击“Identify DC Nets”，弹出“Identify DC Nets”窗口，如图2-6所示：图2-6 Identify DC Nets窗口（3）在“Net”列表中选择网络如“GND_EARTH”，在“Voltage”栏双击“NONE”输入相应的电压值如0，并按下“Tab”键。
再如选择“VCC285”，在“Voltage”栏双击“NONE”输入相应的电压值如2.85，并按下“Tab”键。
（4）单击“OK”，关闭“Identify DC Nets”窗口。
“Database Setup Advisor”窗口将再次显示。
注意：如果有的网络与提取的网络无关，则可以不分配电压属性。
2.5器件设置（Device Setup）（1）单击“Next”，弹出“Data Setup Advisor –Device Setup”窗口，如图2-7所示：图2-7 Data Setup Advisor –Device Setup窗口（2）单击“Device Setup”，弹出“Device Setup”窗口，如图2-8所示：确定哪一个元件是连接器（Connectors），哪一个元件是分立元件（Discretes），并相应地确定器件的“Class”和“Pinuse”。
¾器件类（Device Class）IC是能分配IBIS模型的有源器件每个管脚的PINUSE必须是IN、OUT、BI、NC、GROUND、POWER、OCA、OCLDISCRETE是无源器件（电阻、电容、电导）每个管脚的PINUSE必须是UNSPECIO=INPUT/OUTPUT每个管脚的PINUSE必须是UNSPEC¾PINUSEPCB SI使用PINUSE来确定Sigxplorer/Signoise仿真的缓冲器类型Input、Output、Bidirectional、UNSPEC、Power、Ground对于IO和DISCRETE器件的PINUSE必须是UNSPEC都是无源器件图2-8 器件类设置窗口PCB SI使用Device Class来确定元件类型。
IC的类指定为有源器件，比如驱动器或接收器。
DISCRETE的类指定为无源器件，比如电阻、电容、电感。
IO的类指定为输入或者输出器件，比如连接器。
在UL2项目中，连接器都是以CN标识的，因此在Connector 栏中应输入CN*。
对于仿真，处理这些信息很重要。
当执行仿真时PCB SI使用PINUSE属性值。
例如，不小心把电阻PINUSE分配为OUT，PCB SI会假定电阻是一个驱动元件并为电阻分配一个默认的信号模型。
在电阻的Allegro器件文件创建过程中，Device Class分配不正确，就能导致上述错误。
（3）设置完成后，单击“OK”，保存修改返回“Database Setup Advisor-Device Setup”窗口，并弹出一个元件变化的状态报告，如图2-9所示：图2-9 元件变化的状态报告2.6 SI模型分配（1）单击“Next”，弹出“Data Setup Advisor –SI Models”窗口，如图2-10所示：图2-10 Data Setup Advisor –SI Models窗口（2）单击“Signal Model Assignment”→弹出提示信息（有的DC网络没有分配电压值），如图2-11所示：图2-11（3）单击“是”，弹出“Signal Model Assignment”窗口，如图2-12所示：¾Device 可以手动或自动为器件分配模型。
¾Bond Wires 定位并为Bondwire连接分配Trace模型。
¾RefDesPins 为指定管脚分配IOCell模型。
图2-12 Signal Model Assignment窗口（4）手动分配元件模型这里只对地址线A15进行仿真，该网络连接了五个器件分别是U8、U32、U38、U40、U45。