直放站和RRU应用TI方案介绍-2011-11

日程•直放站和RRU基础•TI系统方案最新器件介绍应用方案介绍•ADC/DAC模拟接口•频谱规划基础之什么是直放站?直放站是一种信号中继器(Repeater),把接收的基站下行射频信号和手机的上行射频信号进行功率放大。

直放站在下行链路中，由施主天线现有的覆盖区域中拾取信号，通过带通滤波器对带通外的信号进行极好的隔离，将滤波的信号经功放放大后再次发射到待覆盖区域。

在上行链接路径中，覆盖区域内的移动台手机的信号以同样的工作方式由上行放大链路处理后发射到相应基站，从而达到基地站与手机的信号传递。

常见的直放站通信制式有GSM, CDMA,WCDMA，以及专网等。

在TDD系统直放站应用比较少，如WiMAX, TDS, TDDLTE等，为什么？基础之什么是RRU?RRU(Remote Radio Unit)，将传统基站分割为两个部分，即基带处理单元(BBU)和远端射频单元(RRU),二者之间通过光纤连接；其接口基于开放式接口协议CPRI或者IR协议等。

理论上只要所有RRU设备遵循相同的接口协议，可以和所有的主设备厂家BBU进行连接，实现通用性。

在新架构网络中，一个BBU可以连接多个RRU单元，既节省空间又降低成本，同时提高了组网灵活性。

3G网络大量使用分布式基站架构，RRU（射频拉远模块）和BBU（基带处理单元）之间需要用光纤连接。

一个BBU可以支持多个RRU。

采用BBU+RRU多通道方案,可以很好地解决大型场馆的室内覆盖。

目前TDS,CDMA2K,WCDMA,LTE,WiMAX等主流制式都广泛采用BBU+RRU架构，在传统的GSM系统中，也有部分厂家在推广BBU+RRU架构来代替传统基站+直放站模式。

基础之数字直放站Vs RRU直接基带传输，时延小两次变频，时延大时延独立扰码和同步码与施主基站同扰码干扰高低建设成本单设备比直放站差不多1拖多成本优势大设备成本容量可调整容量受限于源容量可灵活组网可灵活组网组网RRU 数字直放站增加导频污染导致软切换增加结论结论：：在目前GSM 网络架构下，直放站的成本优势不太可能被RRU 完全代替。

但是在LTE 等模式下如果采用PICO/FemtoCell 模式，直放站市场会下滑比较快。

由于目前3G 网络对日益增长终端数据业务的承载能力仍略显不足，各大运营商都在大力投入WLAN 的建设，而数字直放站设备和WLAN 的融合混模覆盖可以增加运营商对其青睐。

基础之系统拓扑RRU直放站RRURRU基础之数字直放站覆盖注：这里仅讨论数字直放站方案优点：架设方便，成本低；缺点：存在同频干扰问题,需要收发天线之间大隔离度，防止PA 自激.需要开发数字ICS 算法降低同频干扰，会提高设备成本；空中传输信噪比恶化快，无法承载高据流量;TX RFRX RFDUC/DDCDDC/DUCduplexerNear repeaterRX RFTX RFduplexerBS freq relay freqTX RFRX RFDUC/DDCDDC/DUCduplexerremote repeaterRX RFTX RFduplexerBS freq relay freq BSUEUE优点：架设方便，成本低；收发不同频，无同频干扰；缺点：需要额外的频谱资源；增加移频中继设备，成本上升；空中传输信噪比恶化快，无法承载高据流量;TX RFRX RF DUC DDCOptical interfaceduplexerTX RFRX RFDUC DDC Optical interfaceduplexerNear repeaterRemote repeaterOptical fiber优点：没有同频干扰;传输数字化，信号无误差传输；降低了底噪。

高性能，承载高数据流量业务；缺点：铺设光纤成本高硬件成本稍微高；信号源通过射频电缆从基站天线耦合基础之中射频框图(数字直放站和RRU中射频功能几乎相同)基础之中射频框图TI HPAADS58C28/58C23 DAC3482/3484/34H84 TRF3705-02ADS58C28TI&SVA combo SolutionTI SVALMH6521 LMK048xx LMX2531/2541DAC3482/3484TI HPA&SVA High Speed Signal Chain Combo SolutionLMH6521 RX0 RX1TRF3705-02 I/Q Modulator TX0ADC ADCDAC DACPRI_REFSEC_REFTCXO10MHzLMX2531/41Digital ProcessorLMX048xxDual Loop PLLDual Loop PLLSVATRF3705-02VCXO30.72MHzDAC DACI/Q ModulatorTX1SVA基础之中射频框图TI HPA&SVA RF PA Combo Solution TI HPADAC6578/TLV5631/AMC7812/AMC7891 TMP75/TMP20 INA193TI&SVA combo SolutionTI SVALMH2110MCUDAC(DAC6578)Current Sensor(INA193)Power Detector(LMH2110)RF AttenuatorTemp Sensor(TMP75)AMC7812/7891TI系统方案之器件篇 系统方案之器件篇ADS58C28/ADS58C48接收机ADC 接收机Dual/Quad 11-bit 200MSPS ADC with SNRBoost3G Low Power Consumption• 335 mW/ch with 60+MHz SNRBoost 185MSPS • 35% power reduction from ADC62C17 • Wideband SNRBoost3G: 60MHz Signal BW • 72.2 dBFS SNR at 140MHz and 185MSPS • 88 dBc SFDR at 140MHz and 185MSPS • 6 dB gain in 1 dB steps • Selectable DDR LVDS or CMOS outputs • 9x9mm, 64-pin QFN package • 1.8V AVdd and DVdd supplies • No export license required• Lower system operating cost • Enables TD-SCDMA, LTE, WiMAX and MC-GSM • Optimization of SNR and SFDR • Compatible to the GC53xx family as well as all FPGAs and most ASICs • High density with ease of use from a QFN • See AppNote SLAA461 on Power Supply Design • Unlimited orders to China14bit BW=0.33*FsTI系统方案之器件篇 系统方案之器件篇ADS58C20/3: High SFDR Dual Channel Receiver IC• • • • • • • 14 bit Internal ADC, 9 or 14 bit output Maximum Input Sample Rate: 500MSPS Maximum Output Sample Rate: 250MSPS Optional 2x Decimating Filter Optional 75 MHz BW SNR Boost Power = 700mW/channel Input Buffer with high impedance eases filter design • 80-pin TQFP package with PowerPAD • Pin Compatible Family Members– ADS58C20 – 9 or 14-bit output, high SFDR –HD2-5 = 86 dBc MIN, 90 dBc TYP –Non-HD2-5 = 92 dBc MIN –SFDR in 40 MHz (Fs*3/8) = 90 dBc MIN – ADS58C23 – 9 of 14-bit output, reduced SFDR –SFDR = 80 dBc MIN 85 dBc TYP接收机ADC 接收机TI系统方案之器件篇 系统方案之器件篇ADS58B18/58B19• Low power consumption: 360mW with LVDS I/O • High Impedance input buffer • Flattens gain response across 3dB bandwidth • Removes sample-and-hold kickback • High performance with selectable SNRBoost • 66.2 dB SNR, 87 dBc SFDR at 70MHz IF • 72.2 dB SNR, 83 dBC SFDR at 150 MHZ with 30MHz wide SNRBoost • 6 dB gain in 1 dB steps for SNR/SFDR trade-off • 7x7mm, 48-pin QFN package • Selectable DDR LVDS or CMOS outputs with halfand full-swing LVDS modes • 1.8V AVdd and DVdd supplies • Export control compliant – no license requiredDPD反馈 反馈ADC 反馈Low Power, Buffered Input 11-bit 200MSPS/9bit 250Msps ADC with SNRBoost• Reduces load on power supply and minimizes thermal requirements – see 1Q 2010 Analog Applications Journal for best power designs • Eases gain matching for passive and active AFE designs in wide bandwidth DPD feedback signals • Provides high SNR and dynamic range required for high performance digital pre-distortion • Allows for optimization of SNR and SFDR for input signal swings between .5 and 1.5 Vpp • Small form-factor for minimized board space • Compatible to the GC53xx family as well as all FPGAs and most ASICsDAC5682z TX TRF372017 I/Q Modulator LO DPD FeedbackGC5322/28DUC-CFR-DPD DUC-CFR-DAC DACADS58B18ADCPGA870 Mixer Attenuator FB LO (EXT)TI系统方案之器件篇 系统方案之器件篇ADS62PF49TI系统方案之器件篇 系统方案之器件篇Dual 16-bit, 2x-4x Interpolation, 800MSPS DAC • • Dual 16-Bit 800 MSPS DAC 8-Bit Input LVDS Data Bus • 8 Sample Input FIFO • Optional Data Pattern Checker • Compatible with GC5330 Multi-DAC Synchronization Excellent Performance • 80dBc ACLR WCDMA TM1 at 153.6 MHz Low Power Dissipation • 1.1W at full-speed Digital Processing & Options: • Optional 2x/4x Interpolation FIR • Fs/2 and Fs/4 Coarse Mixer • Digital Quadrature Modulator Correction: Gain, Phase and Offset • • • • • • •DAC3283• •Temperature Sensor 3- or 4-wire Serial Control Interface On Chip 1.2V Reference 3.3V Analog, 1.8V Digital Supplies Small Package: 7x7mm 48-pin QFN Scaleable Output Current: 2 to 20mA Now in Production!• •TI系统方案之器件篇 系统方案之器件篇Quad and Dual Channel 16bit, 1.25GSPS DACs • DAC3484: Quad, Byte-wide DDR, 88-mRQFN • DAC3482: Dual, Word-wide DDR, 88-mRQFN • Low Power • Total Power ~ 1W • 65% lower power than competition • Space Saving Packages Options: • 9x9mm 88 pin mrQFN Package • Multi-DAC Synchronization • Input Sample FIFO • On-board 2x-32x PLL • Interleaved LVDS Data Bus • 4 ch: 250 MHz Bandwidth (312.5Msps) • 2 ch: 500 MHz Bandwidth (625Msps) • GC5330 Compatible • Digital Processing & Options: • Selectable 2x-16x Interpolation • Coarse Mixer • Complex Mixer with 32-bit NCO • Digital Quadrature Modulator Corr. • Sinx/x Correction FilterDAC3484/DAC3482• 3-wire or 4-wire serial control bus (SPI) • Integrated Temperature Sensor DAC3484 (Quad, 88-mRQFN): • Samples/EVMs Now • RTM June 2011 • Reduces board space by half when compared to today’s 2 dual DAC solutions. • Reduce interface pin count required by half compared to DAC5682Z. This saves cost on expensive FPGA IO. • Digital Signal Processing options allows for flexible IF placement • Optimized for wide bandwidth multiantenna applications.1.25GSPS, 8x, 140MHz IF, ACLR = 78dBcTI系统方案之器件篇 系统方案之器件篇• Same Features as DAC3484 • Very Low Power design: ~1W at 1.25GSPS • 32-LVDS data lines, DDR interface– Input Sample FIFO – Optional Data Pattern Checker – Optional Dual Parity Function: one for each complex channelDAC34H84Quad Channel 16bit, 1.25GSPS DAC, Word-wide DDR Interface 12x12mm, 196 BGA Package Modified Interface and Package • 32-Pairs LVDS Data Bus • Two 16-bit DDR Interfaces • 500 MHz Bandwidth Support • BGA Package • 12x12mm, 0.80mm pitch• Interface allows double the data rate than the DAC3484 • Multi-DAC Synchronization • On-board very low jitter PLL • Digital Processing & Options:– – – – – Selectable 2x-16x Interpolation Independent Complex Mixers with 32-bit NCO Power Saving Coarse Mixers: ±n*Fs/8 Digital Quadrature Modulator Correction (QMC) Sinx/x Correction Filters• 3-wire or 4-wire serial control bus (SPI) • Integrated Temperature Sensor20TI系统方案之器件篇TRF3705-0221TI 系统方案之器件篇•Multi-standard Base Stations•3GPP (LTE, W-CDMA, TDS-CDMA)•MC-GSM•WiMAX and WiBRO (OFDMA)•3GPP2 (CDMA2000)•Software Defined Radios –defense and commercial•Wireless infrastructure repeaters•Up to 4x8 MIMO transceivers•Up to 48 Channels of DUCs and DDCs in 4x 12 channelblocks, configurable into a single wideband DUC or DDC•1 DUC and DDC channel up to 100MS/s each •24 DUC and DDC channels up to 6.4MS/s each •1-98,304x decimation and interpolation range•40 Tx LVDS pairs, 38 Rx LVDS pairs with 1.24GSPS data rate support for Tx, 930 MSPS Rx•Supports multi-channel, multi-carrier, multi-mode andmulti-band operation across wide bandwidths•Complete analog and solution with reference design available to speed time to market•Upcoming EVM compatible with over 60 TI high speed ADC and DAC EVMs.•Fractional resampler for each 12 channel DUC/DDC block•I/Q imbalance correction for transmit and receive•Highly configurable DUC and DDC channels enable wide bandwidth support as well as multi-band, multi-mode transmit and receive solutions without FPGA development•Supports converters for up to 4 Tx and 8 Rx chains without the need for costly FPGAs•Allows for rapid development of highly flexible, software configurable wireless platforms•Enables rapid evaluation and prototyping of complete transmit and receive solution•Provides multi-rate support for each DUC/DDC block•Reduces DC offset and compensates for I/Q imbalances and LO leakage to improve receiver error vector magnitudeGC6016TI 系统方案之器件篇•Multi-standard Base Stations•3GPP (LTE, W-CDMA, TDS-CDMA)•MC-GSM•WiMAX and WiBRO(OFDMA)•3GPP2 (CDMA2000)•Multi-carrier power amps (MCPAs)•Wireless infrastructure repeaters •Up to 4x8 MIMO transceivers•Highly Integrated digital transmit and receive processor:•Digital Pre-Distortion –5th order adaptive correction •Crest Factor Reduction•1-48 Configurable bandwidth DUCs and DDCs•Supports multiple transmit antennas for main/diversity and MIMO applications•Four transmit antennas with 30MHz of bandwidth•Two transmit antennas with 60MHz of bandwidth •Supports multi-channel, multi-carrier, multi-mode andmulti-band operation across wide bandwidths•Complete analog and DSP solution with reference design •Direct connection to C6748 with TI high performance DPDalgorithm. Can also be used with customer DPD IP •DPD algorithm compensates for PA memory effects•40Tx LVDS pairs, 30 Rx LVDS pairs and 8 DPD feedback LVDS pairs with 1.2GSPS support (Rx), 921MSPS (Tx)•Integration reduces design complexity, development time, power consumption and cost compared to large FPGA (Virtex, Stratex) and ASIC DSP solutions•Simplifies board layout for 2x2, 2x4, 4x4 and 4x8 solutions while reducing cost by an order of magnitude vs. FPGAs •Allows for development of highly flexible, software configurable wireless platforms•Saves up to 6 man-months of evaluation and prototyping by enabling customer PA linearization within one hour•Provides flexible software environment for upgrading DPD algorithm to adapt to new and emerging standards•Improves ACLR by as much as 30 dB, enabling PA to be driven harder and to higher efficiencies•Supports converters for up to 4 Tx and 8 Rx chains plus DPD feedback without the need for costly FPGAsGC5330/5337TI系统方案之器件篇SVA LMH6521TI系统方案之器件篇LMH6517 to LMH6521Utra-Low noise Clock Jitter cleanerBlock DiagramUtra-Low jitter Clock GeneratorDual Buffer with 14 programmable outputsTI系统方案之器件篇LMK04800 +LMK01801 Clocking for RRU systemTI系统方案之器件篇 系统方案之器件篇3:10 Differential Fanout BufferSVA LMK00301TI系统方案之器件篇 系统方案之器件篇Wideband Frequency SynthesizerSVA LMX2581LMX2531,2541 to 2581TI系统方案之器件篇 系统方案之器件篇CPRI Serdes with Precision DCMSVA SCAN25100• Exceeds LV and HV CPRI voltage & jitter requirements • 614.4, 1228.8 and 2457.6Mbps operaion • 800ps Delay Calibration Measurement accuracy • Receiver and remote end synchronization without reference clock • Low noise recovered clock • Optional 8b/10b encoding • Transmit de-emphasis extends cable driveTI系统方案之器件篇 系统方案之器件篇CIF TLK10002TI系统方案之器件篇 系统方案之器件篇SVA LMH21108 GHz Logarithmic RMS Power Detector with 45 dB dynamic rangeTI系统方案之数字直放站方案 系统方案之数字直放站方案RX LO ADS58C28 ADS58C23 ADS58C20 DAC3484 DAC3482 DAC34H84 TX C TRF3703/4-17/TRF3705-02RX AAttenuatorsADC ADCAttenuators LMH65xxGC6016DUC-DDC DUC-DAC DAC DAC DACI/Q ModulatorAttenuators TRF372017I/Q ModulatorFPGAInterface ProtocolBuff.LOEMIF SPIEP M3/ARM Serdes TLK313xSVA CLOCKPowerUCD/TPSSupport 30MHz,12 carriers/ANTTI系统方案之 系统方案之1Tx2Tx带DPD方案 系统方案之 带 方案RX LO GC5322 GC5325 GC5328 TX CAttenuatorsADS58C28DAC5682zTRF372017ADC ADCAttenuators LMH65xxGC532xDUC-CFR-DPD DUC-CFR-DAC DACI/Q ModulatorLOADS58B18/19 RX BADCFPGADSP C6727BPGA870MixerAttenuatorSupport 20MHzTLK3132 TLK6002 TLK10002SerdesEPIEP M3/ARMSVA CLOCKPowerUCD/TPSTI系统方案之 系统方案之2x2 MIMO LTE 系统方案之GC5322 GC5325 GC5328 RX LO DAC5682z TRF372017GC532xDUC-CFR-DPD DUC-CFR-TX 1DAC DACI/Q ModulatorLOADS58B18/19 Attenuators ADS58C28ADCPGA870 Mixer AttenuatorADC ADCAttenuators LMH65xxGC532xDAC5682z TRF370317DUC-CFR-DPD DUC-CFRRX BTX 2DAC DACI/Q ModulatorFPGADSP C6727BSupport 20MHzTLK3132 TLK6002 TLK10002SerdesEPIEP M3/ARMSVA CLOCKPowerUCD/TPSTI系统方案之 系统方案之2x2 MIMO LTE 系统方案之RX LOGC5330 GC5337DAC3482 DAC3484 TX 1TRF372017 /3705-02GC533xDAC DACADS58B18/19 ADS62PF49I/Q ModulatorLOAttenuatorsADS58C28DUC-CFR-DPD DUC-CFR-DDCADCPGA870 Mixer AttenuatorADC ADCAttenuators LMH65xxDAC3482 TX 2TRF370317/3705-02RX BDAC DACI/Q ModulatorFPGADSP C6727BGC5330 This Arch can support 2 x30MHz in HP mode 24 TX and RX channels( 12 channels per ANT) Note DSP can be shared for up to 4 GC5330 Support ET functionTLK3132 TLK6002 TLK10002SerdesEPIEP M3/ARMSVA CLOCKPowerUCD/TPSTI系统方案之 系统方案之Two 2x2 MIMO LTE 系统方案之GC5330 GC5337RX LO Attenuators ADS58C48 ADS58C28 DAC3484 TX 1/2 TRF372017GC533xDAC DACADS58B18/19 ADS62PF49I/Q ModulatorLOADC ADCDUC-CFR-DPD DUC-CFRADC ADCAttenuators LMH65xx TX 3/4ADCPGA870 Mixer Attenuator-DDCDAC3484 TRF370317DAC DACI/Q ModulatorFPGADSP C6748TLK3132 TLK6002 TLK10002This Arch can support 4 x15MHz in HP mode and 4x30MHz in HB mode 24 TX and RX channels ( 6 channels per ANT) No ET support Note DSP can be shared for up to 4 GC5330 SVA CLOCK PowerUCD/TPSSerdesEPIEP M3/ARMTI系统方案之 系统方案之MGSM DPD方案 系统方案之 方案RX LO GC5330 GC5337 ADS58C28 ADS58C23 ADS58C20 DAC34H84 DAC3484 DAC3482 TRF372017/3705-02AttenuatorsADC ADCAttenuators LMH65xxGC533xDUC-CFR-DPD DUC-CFR-DDCTX CDAC DACADS62PF49I/Q ModulatorLOADC ADCAttenuator DemodulatorFPGADSP C6748TLK3132 TLK6002 TLK10002SerdesEPISupport 30MHz BW UMTS-30MHzSVA CLOCK PowerUCD/TPSEP M3/ARMADC/DAC模拟接口 模拟接口Transformer interface to ADCR-C-R滤波器用于吸收ADC采样开关 导致的开关噪声(Glitch);如果你发现你 的信号输出带有毛刺，那么它就是Glitch. ADC模拟口内部集成有高带宽的滤波器， 如果你的中频比较低，可以再增加外部 滤波器，以增强效果。