重庆大学EDA课程设计-vhdl语言-12.24小时时钟-乐曲播放电路-函数信号发生器

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EDA课程设计数字钟(综合课程设计)一_001

EDA课程设计数字钟（综合课程设计）一、设计要求（数字钟的功能）1、具有时、分显示功能（用数码管显示）。

以二十四小时循环计时。

2、具有清零，调节小时，分钟的功能。

3、具有整点（正小时）报时同时用多颗LED灯花样显示秒的功能。

4、运用多层次化设计方式，底层元件用VHDL编写，顶（最高）层元件用原理图法连线。

5、写出课程设计报告，包括设计源程序代码、顶层原理图及必要的文字说明。

二、目的1、掌握多位计数器相连的设计方法。

2、掌握十进制，六进制，二十四进制计数器的设计方法。

3、掌握扬声器的驱动及报时的设计。

4、LED灯的花样显示。

5、掌握CPLD技术的层次化设计方法。

三、硬件要求1、主芯片Altera EPF10K10LC84-4。

2、8个LED灯。

3、扬声器。

4、4位数码显示管。

5、8个按键开关（清零，调小时，调分钟）。

四、实验原理在同一CPLD芯片上集成了如下电路模块：1、时钟计数：秒……60进制BCD码计数。

分……60进制BCD码计数。

时……24进制BCD码计数。

同时整个计数器有清零、调时、调分功能。

在接近整数时能提供报时信号。

2、扬声器在整点时有报时驱动信号产生（响声持续多长时间？）。

3、LED灯按个人口味在整点时有花样显示信号产生。

五、实验内容及步骤1、根据电路特点，运用层次设计概念设计。

将此设计任务分成若干模块，规定每一模块的功能和各模块之间的接口。

加深层次化设计概念。

2、了解软件的元件管理深层含义，以及模块元件之间的连接概念，对于不同目录下的同一设计，如何熔合。

六、顶层原理图参考下图所示（模块化设计）。

用VHDL语言实现数字电子钟的设计(EDA课程设计报告-含源程序)

课程设计报告设计题目：用VHDL语言实现数字钟的设计班级：电子 0901学号： XXXXXXXX姓名：XXXXXXXXX指导教师：XXXXXXXXX设计时间：现代电子设计技术的核心已转向基于计算机的电子设计自动化技术，即EDA （Electronic Design Automation）技术。

EDA技术就是依赖计算机，在EDA工具软件平台上，对以硬件描述语言HDL（Hardware Description Language）为系统逻辑描述手段完成的设计文件，自动地完成逻辑编译、化简、分割、综合、布局布线以及逻辑优化和仿真测试，直至实现既定的电子线路系统功能。

EDA技术使得设计者的工作仅限于利用软件的方式，即利用硬件描述语言和EDA软件来完成对系统硬件功能的实现。

硬件描述语言是EDA技术的重要组成部分，常见的HDL语言有VHDL、Verilog、HDL、ABLE、AHDL、System Verilog和System C。

其中VHDL、Verilog在现在的EDA设计中使用最多，也拥有几乎所有主流EDA工具的支持。

VHDL语言具有很强的电路描述和建模能力，能从多个层次对数字系统进行建模和描述，从而大大简化硬件设计任务，提高了设计效率和可靠性。

在这次设计中，主要使用VHDL语言输入。

此次设计很好地完成了数字钟的定时、切换显示年月日和时分秒的功能，完成了小型FPGA的设计开发，锻炼了动手实践能力，达到了课程设计的目的。

关键词：EDA技术硬件描述语言VHDL 设计数字电子钟摘要 (2)1、课程设计目的 (4)2、课程设计内容及要求 (4)2.1 设计内容 (4)2.2 设计要求 (4)3、VHDL程序设计 (5)3.1 方案论证 (5)3.2 设计思路与方法 (6)3.2.1 设计思路 (6)3.2.2 设计方法 (7)4、仿真与分析 (7)5、器件编程下载及设计结果 (9)6、课程设计总结 (10)7、参考文献 (10)8、程序清单 (11)8.1 顶层模块 (11)8.2 秒脉冲模块 (13)8.3 数码管显示模块 (14)8.4 时分秒模块 (15)8.4.1 分秒模块 (16)8.4.2 小时模块 (18)8.5 年月日模块 (19)8.5.1 日期模块 (21)8.5.2 月份模块 (24)8.5.3 年份模块 (25)1、课程设计目的EDA技术课程设计在课程结束以后进行，在实践中验证理论知识，不仅是为了巩固课堂上所学知识，更是为了加深我们对EDA技术和VHDL语言的理解；为了让我们自己动手完成从设计输入、逻辑综合、功能仿真、设计实现到实现编程、时序仿真，一直到器件的下载测试的整个过程，真切感受利用EDA技术对FPGA进行设计开发的过程，锻炼和提高我们对器件的编程调试能力。

EDA课程设计---乐曲硬件演奏电路的VHDL设计

EDA课程设计题目：乐曲硬件演奏电路的VHDL设计一、设计题目：乐曲硬件演奏电路的VHDL 设计二、设计目标：1）能够播放“梁祝”乐曲。

2）能够通过LED 显示音阶。

3）具有“播放/停止”功能，并在此基础上实现“按键演奏”的电子琴功能。

三、设计原理：1. 音乐基础知识一段简单乐谱由音调和节拍组成，音调表示一个音符唱多高的频率，节拍表示一个音符唱多长的时间。

音符的节拍我们可以举例来说明。

在一张乐谱中，我们经常会看到这样的表达式，如1=C 44、1=G 43……等等。

以43为例加以说明，它表示乐谱中以四分音符为节拍，每一小结有三拍。

比如：图1其中1 、2 为一拍，3、4、5为一拍，6为一拍共三拍。

1 、2的时长为四分音符的一半，即为八分音符长，3、4的时长为八分音符的一半，即为十六分音符长，5的时长为四分音符的一半，即为八分音符长，6的时长为四分音符长。

那么一拍到底该唱多长呢？一般说来，如果乐曲没有特殊说明，一拍的时长大约为400—500ms 。

我们以一拍的时长为400ms为例，则当以四分音符为节拍时，四分音符的时长就为400ms，八分音符的时长就为200ms，十六分音符的时长就为100ms。

2.原理图框图：图2.框图3.原理图说明音乐播放原理说明音符的频率由数控分频器模块Speakera产生。

ToneTaba模块从NoteTabs模块中输入的音符数据，将对应的分频预置数据传送给Speakera模块，并将音符数据送到LED模块显示音阶。

NoteTabs模块中包含有一个音符数据ROM，里面存有歌曲“梁祝”的全部音调，在此模块中设置了一个8位二进制计数器，作为音符数据ROM的地址发生器。

这个计数器的计数频率为4Hz，即每一个数值的停留时间为0.25秒。

例如：“梁祝”乐曲的第一个音符为“3”，此音在逻辑中停留了4个时钟节拍，即1秒钟时间，所对应的“3”音符分频预置数为1036，在Speakera的输入端停留了1秒。

重庆大学EDA课程设计-EDA课程设计-vhdl语言-12.24小时时钟-乐曲播放电路-函数信号发生器

附录一、12/24小时数字时钟VHDL设计1，系统顶层逻辑图：时序仿真波形管脚定义以及锁定2，分频模块。

①各个分频模块的模块图：②，分别对应的仿真波形：③50mhz分频至1k模块代码：library ieee;use ieee.std_logic_unsigned.all;use ieee.std_logic_1164.all;entity wh4574_divto1k isport(clk50m:in std_logic;clk1k:out std_logic);end wh4574_divto1k;architecture behav of wh4574_divto1k issignal count1:std_logic_vector(14 downto0);signal count2:std_logic;signal co:std_logic;beginprocess(clk50m)beginif clk50m'event and clk50m='1' thenif count1="110000110100111" thencount1<="000000000000000";co<='1';elsecount1<=count1+'1';co<='0';end if;end if;end process;process(co)beginif co'event and co='1' thencount2<=not count2;end if;end process;clk1k<=count2;end behav;50mhz分频至2k模块代码：library ieee;use ieee.std_logic_unsigned.all;use ieee.std_logic_1164.all;entity wh4574_divto2k isport(clk50m:in std_logic;clk2k:out std_logic);end wh4574_divto2k;architecture behav of wh4574_divto2k issignal count1:std_logic_vector(13 downto0);signal count2:std_logic;signal co:std_logic;beginprocess(clk50m)beginif clk50m'event and clk50m='1' thenif count1="11000011010011" thencount1<="00000000000000";co<='1';elsecount1<=count1+'1';co<='0';end if;end if;end process;process(co)beginif co'event and co='1' thencount2<=not count2;end if;end process;clk2k<=count2;end behav;1k分频至5hz代码：library ieee;use ieee.std_logic_unsigned.all;use ieee.std_logic_1164.all;entity wh4574_div1kto5 isport(inclk1k:in std_logic;clk5hz:out std_logic);end wh4574_div1kto5;architecture behav of wh4574_div1kto5 is signal count1:std_logic_vector(6 downto 0);signal count2:std_logic;signal co:std_logic;beginprocess(inclk1k)beginif inclk1k'event and inclk1k='1' thenif count1="1100011" thencount1<="0000000";co<='1';elsecount1<=count1+'1';co<='0';end if;end if;end process;process(co)beginif co'event and co='1' thencount2<=not count2;end if;end process;clk5hz<=count2;end behav;5分频代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wh4574_div_5 isport(clk:in std_logic;q:out std_logic);end wh4574_div_5;architecture behav of wh4574_div_5 is signal count:std_logic_vector(2 downto 0); beginprocess(clk)beginif clk'event and clk='1' thenif count="100"thencount<="000";q<='1';elsecount<=count+1;q<='0';end if;end if;end process;end behav;。

EDA课程设计报告(电子钟VHDL 设计)

EDA课程设计报告（电子钟VHDL 设计）作者：dang168 时间：2008-10-05E D A课程设计报告-----电子钟VHDL 设计一设计要求设计一个电子钟，要求可以显示时、分、秒，用户可以设置时间.二.实验目的1. 掌握多位计数器相连的设计方法。

2. 掌握十六进制，二十四进制，六十进制计数器的设计方法。

3. 掌握CPLD技术的层次化设计方法。

4. 了解软件的元件管理含义以及模块元件之间的连接概念。

5. 掌握电子电路一般的设计方法，并了解电子产品的研制开发过程，基本掌握电子电路安装和调试的方法。

6. 培养独立分析问题，解决问题的能力。

三．硬件要求1．8位8段扫描共阴极数码显示管。

2. 三个按键开关（清零，调小时，调分钟）。

四．设计原理数字钟是一个将“时”“分”“秒”显示于人的视觉器官的计时装置。

它的计时周期为24小时；显示满刻度为23时59分59秒，另外具备校时功能和报时功能。

因此，一个基本的数字钟电路主要由“时”“分”“秒”计数器校时电路组成。

将标准秒信号送入“秒计数器”，“秒计数器”采用60进制计数器，每累加60秒发送一个“分脉冲”信号，该信号将被送到“时计数器”。

“时计数器”采用24进制计数器，可实现对一天24小时的累计。

译码显示电路将“时”“分”“秒”计数器的输出状态六段显示译码器译码。

通过六位ＬＥＤ七段显示器显示出来。

校时电路器是用来对“时”“分”“秒”显示数字进行校时调整的。

在同一ＣＰＬＤ芯片口集成如下电路模块：１．电子钟计数采用层次化设计，将设计任务分成若干个模块。

规定每一模块的功能和各模块之间的接口。

（１）ｓｅｃｏｎｄ（秒）６０进制ＢＣＤ码计数（２）ｍｉｎｕｔｅ（分）６０进制ＢＣＤ码计数（３）ｈｏｕｒ（时）２４进制ＢＣＤ码计数（４）ｃｌｏｃｋ　ｔｏｐ顶层设计同时整个计数器有清零，调时，调分功能。

２．端口引脚名称　输入　ｃｌｋ，ｒｅｓｅｔ，ｓｅｔｍｉｎ，ｓｅｔｈｏｕｒ　输出　ｓｅｃｏｎｄ—ｄａｏｕｔ，ｍｉｎｕｔｅ－ｄａｏｕｔ，ｈｏｕｒ－ｄａｏｕｔ五．设计原理图逻辑功能图：输入：CLK—时钟脉冲，RESET—复位信号，SETMIN—分加1信号，SETHOUR—秒加1信号输出：SECOND_DAOUT—秒输出，MINUTE_DAOUT—分输出，HOUR_DAOUT—时输出时序仿真：程序主要运用计数器完成，在时钟脉冲的作用下，完成时钟功能，由时序图可以看出每一个时钟脉冲上升沿秒加1，当接收到reset 信号，即reset为高电平，所有计数为零，并重新计数，setmin和sethour可以完成调节时钟功能，都是高电平调节，每来一个脉冲，相应的时或分加1。

EDA课程设计报告--24小时时钟

课程设计报告课程名称EDA课题名称24小时时钟专业自动化年级09级学号姓名1)课题的主要功能设计一个24小时的时钟，要有时分秒，分别用六位数码管显示，用两个拨码开关分别当做RST，EN用来控制时钟的复位和使能。

2)功能模块的划分图1 时钟功能模块图该智能时钟分为六个模块，分别为：计数器分频模块、三进制加法计数器模块、六进制加法计数器模块、十进制加法计数器模块、数码管动态显示模块、分频器模块。

3)主要功能的实现3.1、计数器分频功能计数器分频COUNTER如图2模块所示，计数器分频到0-22次，最后分出来的OUT[22]时间是0.8秒，近似于1秒。

3.2、三进制加法计数器功能三进制加法计数器模块DSQSAN如图4模块所示，CLK为计数时钟，RST 为1时，数码管上显示00，RST为0时EN为1时计数开始，每3个数,COUT 输出一个1。

3.3、六进制加法计数器功能六进制加法计数器模块DSQLIU如图3模块所示，CLK为计数时钟，RST 为1时，数码管上显示00，RST为0时EN为1时计数开始，每6个数,COUT输出一个1。

3.4、十进制加法计数器功能十进制加法计数器模块DSQSHI如图5模块所示，CLK为计数时钟，RST 为1时，数码管上显示00，RST为0时EN为1时计数开始，每10个数,COUT 输出一个1。

3.5、数码管动态显示功能数码管动态显示模块SMGM如图6模块所示，每一个数码管都有一个对应的CLK10到CLK5，CLK为数码管的扫描周期接COUT[10],SG接数码管的段码，BT接数码管的位码。

3.6、分频功能分频器模块FPQ如图7模块所示，对机器中自带的时钟频率进行分频由50MHZ分到10MHZ。

图2 COUNTER模块图3 DSQLIU模块图4 DSQSAN模块图5 DSQSHI模块图6 SMGM模块图7 FPQ模块4)各模块连接在一起最终图形解释：用COUT[22]当第一个十进制的CLK用这个十进制加法计数器当做秒钟的个位，然后用第一个十进制计数器的COUT当做第一个六进制加法计数器的CLK，用这个六进制加法计数器当做秒钟的十位，以此类推，上一个计数器的COUT接下一个计数器的CLK，用一个十进制加法计数器当做分钟的个位，一个六进制加法计数器当做分钟的十位，一个十进制加法计数器当做小时的个位，一个三进制加法计数器当做小时的十位，所有的计数器的RST和EN接在一起，实现同时复位和使能。

eda课程设计VHDL语言数字时钟电子琴来自重庆大学电子信息工程

rjy4600_cnt60_1—60进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_cnt60_1 isport(clk:in std_logic;en:in std_logic;bcd10,bcd1:buffer std_logic_vector(3 downto 0);preset:in std_logic;co:out std_logic);end rjy4600_cnt60_1;architecture rtl of rjy4600_cnt60_1 issignal co_1:std_logic;beginprocess(clk,preset)beginif preset='0' thenbcd1<="0000";elseif clk'event and clk='1' thenif en='1' thenif bcd1="1001" thenbcd1<="0000";elsebcd1<=bcd1+'1';end if;else if bcd1="0000" thenbcd1<="1001";elsebcd1<=bcd1-'1';end if;end if;end if;end if;end process;process(clk,preset,bcd1)beginif preset='0' thenbcd10<="0000";co_1<='0';elseif clk='1' and clk'event thenif en='1' thenif bcd1="1000" and bcd10="0101" thenco_1<='1';elsif bcd1="1001" and bcd10="0101" thenbcd10<="0000";co_1<='0';elsif bcd1="1001" thenbcd10<=bcd10+'1';co_1<='0';end if;else if bcd1="0001" and bcd10="0000" thenco_1<='0';elsif bcd1="0000" and bcd10="0000" thenbcd10<="0101";co_1<='1';elsif bcd1="0000" thenbcd10<=bcd10-'1';co_1<='0';else co_1<='0';end if;end if;end if;end if;end process;co<=not co_1;end rtl;rjy4600_cnt24：—24进制计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_cnt24 isport(clk:in std_logic;en:in std_logic;bcd10,bcd1:buffer std_logic_vector(3 downto 0));end rjy4600_cnt24;architecture rtl of rjy4600_cnt24 isbeginprocess(clk)beginif clk'event and clk='1' thenif en='1' thenif bcd1="1001" thenbcd1<="0000";elsif bcd1="0011" and bcd10="0010" thenbcd1<="0000";elsebcd1<=bcd1+'1';end if;else if bcd1="0000" and bcd10="0000" thenbcd1<="0011";elsif bcd1="0000" thenbcd1<="1001";else bcd1<=bcd1-'1';end if;end if;end if;end process;process(clk,bcd1)beginif clk='1' and clk'event thenif en='1' thenif bcd1="0011" and bcd10="0010" thenbcd10<="0000";elsif bcd1="1001" thenbcd10<=bcd10+'1';end if;else if bcd1="0000" and bcd10="0000" thenbcd10<="0010";elsif bcd1="0000" thenbcd10<=bcd10-'1';end if;end if;end if;end process;end rtl;rjy4600_div1000：—1000分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_div1000 isport(clk:in std_logic;q:out std_logic);end rjy4600_div1000;architecture rtl of rjy4600_div1000 issignal div:integer:=0;beginprocess(clk)beginif clk'event and clk='1' thenif div=999 thendiv<=0;q<='1';elsediv<=div+1;q<='0';end if;end if;end process;end rtl;rjy4600_display：—动态译码及显示扫描library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_display isport(din0:in std_logic_vector(3 downto 0);din1:in std_logic_vector(3 downto 0);din2:in std_logic_vector(3 downto 0);din3:in std_logic_vector(3 downto 0);din4:in std_logic_vector(3 downto 0);din5:in std_logic_vector(3 downto 0);clk:in std_logic;led_sa:out std_logic;led_sb:out std_logic;led_sc:out std_logic;led_a:out std_logic;led_b:out std_logic;led_c:out std_logic;led_d:out std_logic;led_e:out std_logic;led_f:out std_logic;led_g:out std_logic;led_dp:out std_logic);end rjy4600_display;architecture behave of rjy4600_display is signal seg:std_logic_vector(6 downto 0);signal sel:std_logic_vector(2 downto 0);signal num:std_logic_vector(3 downto 0);signal s:std_logic_vector(2 downto 0); beginled_sa<=sel(0);led_sb<=sel(1);led_sc<=sel(2);led_a<=seg(0);led_b<=seg(1);led_c<=seg(2);led_d<=seg(3);led_e<=seg(4);led_f<=seg(5);led_g<=seg(6);process(clk)beginif clk'event and clk='1' thenif s="101" thens<="000";elses<=s+'1';end if;end if;end process;process(s,din0,din1,din2,din3,din4,din5)beginif s="000" thensel<="000";num<=din0;led_dp<='0';elsif s="001" thensel<="001";num<=din1;led_dp<='0';elsif s="010" thensel<="010";num<=din2;led_dp<='0';elsif s="011" thensel<="011";num<=din3;led_dp<='0';elsif s="100" thensel<="100";num<=din4;led_dp<='0';elsif s="101" thensel<="101";num<=din5;led_dp<='0';elsesel<="XXX";num<="XXXX";led_dp<='0';end if;end process;seg<="0111111"when num=0 else"0000110"when num=1 else"1011011"when num=2 else"1001111"when num=3 else"1100110"when num=4 else"1101101"when num=5 else"1111101"when num=6 else"0000111"when num=7 else"1111111"when num=8 else"1101111"when num=9 else"1110111"when num=10 else"1111100"when num=11 else"0111001"when num=12 else"1011110"when num=13 else"1111001"when num=14 else"0000000"when num=15 else ---1110001"0000000";end behave;rjy4600_keyin：—按键输入模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_keyin isport(tm_ch:in std_logic;ch_h:in std_logic;ch_m:in std_logic;ch_s:in std_logic;clk_1:in std_logic;clk:in std_logic;a_d:in std_logic;co_60_1:in std_logic;co_60_2:in std_logic;o_q1:out std_logic;o_q2:out std_logic;o_q3:out std_logic;o_en:out std_logic;reset:out std_logic );end rjy4600_keyin;architecture rtl of rjy4600_keyin isbeginprocess(clk,tm_ch,clk_1,co_60_2,co_60_1)beginif clk'event and clk='1' thenif tm_ch='1' theno_en<='1';o_q3<=clk_1;o_q2<=co_60_2;o_q1<=co_60_1; reset<='1';--? else o_q1<=ch_h;o_q2<=ch_m;reset<= ch_s;o_q3<='0';if a_d='1' theno_en<='1';else o_en<='0';end if;end if;end if;end process;end rtl;rjy4600_12_24：12/24小时转换library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rjy4600_12_24 isport(c12_24:in std_logic;clk:in std_logic;chh:in std_logic_vector(3 downto 0);ch:in std_logic_vector(3 downto 0);chh_1:out std_logic_vector(3 downto 0);ch_1:out std_logic_vector(3 downto 0));end rjy4600_12_24;architecture rtl of rjy4600_12_24 isbeginprocess(c12_24,clk,chh,ch)beginif clk='1'and clk'event thenif c12_24='1' thenif ((chh="0001" and ch>"0010") or (chh="0010")) thenif ch<2 then ch_1<=ch+8;else chh_1<=chh-'1';ch_1<=ch-2;--ch_1<=ch-'1';--d_24<='0';end if;elsif chh="0000" and ch="0000" thenchh_1<="0001";ch_1<="0010";else chh_1<=chh;ch_1<=ch;end if;else chh_1<=chh;ch_1<=ch;end if;end if;end process;end rtl;rjy4600_shan：—闪烁模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_shan isport(clk_5:in std_logic;clk:in std_logic;s:in std_logic;xx:in std_logic_vector(3 downto 0);x:in std_logic_vector(3 downto 0);qq:out std_logic_vector(3 downto 0);q:out std_logic_vector(3 downto 0));end rjy4600_shan;architecture rtl of rjy4600_shan isbeginprocess(clk,clk_5,xx,x,s)beginif clk'event and clk='1' thenif s='0' thenif clk_5='1' thenqq<="1111";q<= "1111";else qq<=xx;q<=x;end if;else qq<=xx;q<=x;end if;end if;end process;end rtl;rjy4600_baoshi：—整点报时ibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_baoshi isport(clk50_1000:in std_logic;clk_1K:in std_logic;clk_2K:in std_logic;mm:in std_logic_vector(3 downto 0);m:in std_logic_vector(3 downto 0);ss:in std_logic_vector(3 downto 0);s:in std_logic_vector(3 downto 0);sound:out std_logic);end rjy4600_baoshi;architecture rtl of rjy4600_baoshi issignal jishu:integer range 0 to 50000;signal jishu1:integer range 0 to 50000;beginprocess(clk50_1000,mm,m,ss,s)beginif clk50_1000'event and clk50_1000='0' thenif s>="0101" and ss="0101" and m="1001" and mm="0101" then if jishu<20000 thensound<=clk_1K;else sound<='0';end if;if jishu=49999 thenjishu<=0;else jishu<=jishu+1;end if;elsif s="0000" and ss="0000" and m="0000" and mm="0000" then if jishu<20000 thensound<=clk_2K;else sound<='0';end if;if jishu=49999 thenjishu<=0;else jishu1<=jishu1+1;end if;else sound<='0';end if;end if;end process;end rtl;rjy4600_naozhong：—闹钟library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_naozhong isport(clk50_1000:in std_logic;naoz:in std_logic;hh:in std_logic_vector(3 downto 0);h:in std_logic_vector(3 downto 0);mm:in std_logic_vector(3 downto 0);m:in std_logic_vector(3 downto 0);ss:in std_logic_vector(3 downto 0);s:in std_logic_vector(3 downto 0);sound:out std_logic);end rjy4600_naozhong;architecture rtl of rjy4600_naozhong issignal nz:std_logic:='0';signal chh:std_logic_vector(3 downto 0);signal ch:std_logic_vector(3 downto 0);signal cmm:std_logic_vector(3 downto 0);signal cm:std_logic_vector(3 downto 0);signal css:std_logic_vector(3 downto 0);signal cs:std_logic_vector(3 downto 0);beginprocess(clk50_1000)beginif clk50_1000'event and clk50_1000='0' thenif naoz='0' thenchh<=hh;ch<=h;cmm<=mm;cm<=m;css<=ss;cs<=s;else if chh=hh and ch=h and cmm=mm and cm=m and css=ss then ---and cs=s sound<='1';else sound<='0';end if;end if;end if;end process;end rtl;rjy4600_nzsound：—闹钟响铃library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_nzsound isport(clk50_1000:in std_logic;clk_1K:in std_logic;clk_2K:in std_logic;--clk_1:in std_logic;naozhong_snd:in std_logic;sound:out std_logic);end rjy4600_nzsound;architecture rtl of rjy4600_nzsound issignal jishu:integer range 0 to 50000;signal jishu1:integer range 0 to 50000;signal didi:integer range 0 to 15:=0;beginprocess(clk50_1000)beginif clk50_1000'event and clk50_1000='0' thenif naozhong_snd='1' thenif didi=0 or didi=2 or didi=4 or didi=6 or didi=8 or didi=10 or didi=12 or didi=14 then if jishu<20000 thensound<=clk_1K;else sound<='0';end if;if jishu=49999 thenjishu<=0;didi<=didi+1;else jishu<=jishu+1;end if;elsif didi=1 or didi=3 or didi=5 or didi=7 or didi=9 or didi=11 or didi=13 then if jishu1<20000 thensound<=clk_2K;else sound<='0';end if;if jishu1=49999 thenjishu1<=0;didi<=didi+1;else jishu1<=jishu1+1;end if;else didi<=0; sound<='0';end if;else sound<='0';end if;end if;end process;end rtl;rjy4600_PS2_K：—ps2键盘串并行转换library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rjy4600_PS2_K isPort ( sysclk: in std_logic;ps2clk: in std_logic;ps2data: in std_logic;reset: in std_logic;led: out std_logic_vector(7 downto 0));end rjy4600_PS2_K;architecture behav of rjy4600_PS2_K issignal ps2clk_r : std_logic_vector(2 downto 0);signal ps2clkfall : std_logic;signal q : std_logic_vector(11 downto 0);signal ps2serialdata : std_logic_vector(10 downto 0) ; beginprocess(sysclk,reset)beginif reset='0' thenps2clk_r <= "000";elsif rising_edge(sysclk) thenps2clk_r(2) <= ps2clk_r(1);ps2clk_r(1) <= ps2clk_r(0);ps2clk_r(0) <= ps2clk;end if;end process;ps2clkfall<='1' when ps2clk_r="110" else '0';process(sysclk)beginif rising_edge(sysclk) thenif reset='0' then q <= (others =>'0');elsif ps2clkfall='1' thenif q(0)='0' thenq <= ps2data & "01111111111";elseq <= ps2data & q(11 downto 1);end if;end if;end if;end process;process(q)beginif q(0) = '0' thenps2serialdata <= q(11 downto 1);led <= not ps2serialdata(8 downto 1);elseled <="11111111";end if;end process;end behav;rjy4600_tone_rom1：—音符查表及简谱产生library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rjy4600_tone_rom1 isport(index:in std_logic_vector(7 downto 0);index1:in std_logic_vector(3 downto 0);c_g:in std_logic;play_elec:in std_logic;code:out std_logic_vector(3 downto 0);high1:out std_logic_vector(3 downto 0);tone:out std_logic_vector(10 downto 0));end rjy4600_tone_rom1;architecture rtl of rjy4600_tone_rom1 issignal index0:integer range 0 to 255;signal tone1:integer range 0 to 16#7ff#;signal code1:integer range 0 to 15;begintone<=conv_std_logic_vector(tone1,11);code<=conv_std_logic_vector(code1,4);search:process(index)beginindex0<=conv_integer(index1);if play_elec='0' thenif c_g='1' thencase index iswhen "10000010"=>tone1<=2047;code1<=0;high1<="0000";---9-nullwhen "10001000"=>tone1<=137;code1<=1;high1<="0000";---num lockwhen "10110101"=>tone1<=345;code1<=2;high1<="0000";---/when "10000011"=>tone1<=531;code1<=3;high1<="0000";---*when "10000100"=>tone1<=616;code1<=4;high1<="0000";----when "10010011"=>tone1<=772;code1<=5;high1<="0000";---7when "10001010"=>tone1<=912;code1<=6;high1<="0000";---8when "10000110"=>tone1<=1035;code1<=7;high1<="0000";---+when "10010100"=>tone1<=1092;code1<=1;high1<="0001";---4when "10001100"=>tone1<=1197;code1<=2;high1<="0001";---5when "10001011"=>tone1<=1290;code1<=3;high1<="0001";---6when "10010110"=>tone1<=1332;code1<=4;high1<="0001";---1when "10001101"=>tone1<=1410;code1<=5;high1<="0001";---2when "10000101"=>tone1<=1480;code1<=6;high1<="0001";---3when "10100101"=>tone1<=1542;code1<=7;high1<="0001";---enterwhen "10001111"=>tone1<=1570;code1<=1;high1<="0010";---0when "10011001"=>tone1<=1622;code1<=2;high1<="0010";---back spacewhen "10001110"=>tone1<=1669;code1<=3;high1<="0010";---.delwhen others=>null;end case;elsecase index iswhen "10000010"=>tone1<=2047;code1<=0;high1<="0000";---9-nullwhen "10001000"=>tone1<=773;code1<=1;high1<="0000";---num lockwhen "10110101"=>tone1<=912;code1<=2;high1<="0000";---/when "10000011"=>tone1<=1036;code1<=3;high1<="0000";---*when "10000100"=>tone1<=1092;code1<=4;high1<="0000";----when "10010011"=>tone1<=1197;code1<=5;high1<="0000";---7when "10001010"=>tone1<=1290;code1<=6;high1<="0000";---8when "10000110"=>tone1<=1372;code1<=7;high1<="0000";---+when "10010100"=>tone1<=1410;code1<=1;high1<="0001";---4when "10001100"=>tone1<=1480;code1<=2;high1<="0001";---5when "10001011"=>tone1<=1542;code1<=3;high1<="0001";---6when "10010110"=>tone1<=1570;code1<=4;high1<="0001";---1when "10001101"=>tone1<=1622;code1<=5;high1<="0001";---2when "10000101"=>tone1<=1669;code1<=6;high1<="0001";---3when "10100101"=>tone1<=1710;code1<=7;high1<="0001";---enterwhen "10001111"=>tone1<=1729;code1<=1;high1<="0010";---0when "10011001"=>tone1<=1764;code1<=2;high1<="0010";---back spacewhen "10001110"=>tone1<=1795;code1<=3;high1<="0010";---.delwhen others=>null;end case;end if;elseif c_g='1' thencase index0 iswhen 0=>tone1<=2047;code1<=0;high1<="0000";---9-nullwhen 1=>tone1<=137;code1<=1;high1<="0000";---num lockwhen 2=>tone1<=345;code1<=2;high1<="0000";---/when 3=>tone1<=531;code1<=3;high1<="0000";---*when 4=>tone1<=616;code1<=4;high1<="0000";----when 5=>tone1<=772;code1<=5;high1<="0000";---7when 6=>tone1<=912;code1<=6;high1<="0000";---8when 7=>tone1<=1035;code1<=7;high1<="0000";---+when 8=>tone1<=1092;code1<=1;high1<="0001";---4when 9=>tone1<=1197;code1<=2;high1<="0001";---5when 10=>tone1<=1290;code1<=3;high1<="0001";---6when 11=>tone1<=1332;code1<=4;high1<="0001";---1when 12=>tone1<=1410;code1<=5;high1<="0001";---2when 13=>tone1<=1480;code1<=6;high1<="0001";---3when 14=>tone1<=1542;code1<=7;high1<="0001";---enterwhen 15=>tone1<=1570;code1<=1;high1<="0010";---0when 16=>tone1<=1622;code1<=2;high1<="0010";---back spacewhen 17=>tone1<=1669;code1<=3;high1<="0010";---.delwhen others=>null;end case;elsecase index0 iswhen 0=>tone1<=2047;code1<=0;high1<="0000";---9-nullwhen 1=>tone1<=773;code1<=1;high1<="0000";---num lockwhen 2=>tone1<=912;code1<=2;high1<="0000";---/when 3=>tone1<=1036;code1<=3;high1<="0000";---*when 4=>tone1<=1092;code1<=4;high1<="0000";----when 5=>tone1<=1197;code1<=5;high1<="0000";---7when 6=>tone1<=1290;code1<=6;high1<="0000";---8when 7=>tone1<=1372;code1<=7;high1<="0000";---+when 8=>tone1<=1410;code1<=1;high1<="0001";---4when 9=>tone1<=1480;code1<=2;high1<="0001";---5when 10=>tone1<=1542;code1<=3;high1<="0001";---6when 11=>tone1<=1570;code1<=4;high1<="0001";---1when 12=>tone1<=1622;code1<=5;high1<="0001";---2when 13=>tone1<=1669;code1<=6;high1<="0001";---3when 14=>tone1<=1710;code1<=7;high1<="0001";---enterwhen 15=>tone1<=1729;code1<=1;high1<="0010";---0when 16=>tone1<=1764;code1<=2;high1<="0010";---back spacewhen 17=>tone1<=1795;code1<=3;high1<="0010";---.delwhen others=>null;end case;end if;end if;end process;end rtl;rjy4600_speaker2：—发音及音量调节library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rjy4600_speaker2 isport(clk_10m:in std_logic;a_d:in std_logic;tone:in std_logic_vector(10 downto 0);loud_cnt:in std_logic_vector(3 downto 0);--spks:out std_logic);end rjy4600_speaker2;architecture rtl of rjy4600_speaker2 issignal spks_d: std_logic;signal spks_a: std_logic;signal preclk:std_logic;signal fullspks:std_logic;signal spks0:std_logic;signal tone1:integer range 0 to 16#7ff#;signal n:integer range 0 to 10:=0;--signal jishu:integer range 0 to 2047;begintone1<=conv_integer(tone);n<=conv_integer(loud_cnt);--divideclk:process(clk_10m)variable count9:integer range 0 to 127;beginpreclk<='0';if count9>=10 then--?preclk<='1';count9:=0;elsif clk_10m'event and clk_10m='1' then count9:=count9+1;end if;end process;genspks:process(preclk,tone1)variable count11:integer range 0 to 16#7ff#; beginif preclk'event and preclk='1' thenif count11=16#7ff# thencount11:=tone1;fullspks<='1';else count11:=count11+1;fullspks<='0';end if;end if;end process;delayspks:process(fullspks)variable count2:std_logic;beginif fullspks'event and fullspks='1' thencount2:=not count2;if count2='1' thenspks0<='1';elsespks0<='0';end if;end if;end process;zkspks:process(preclk,spks0)beginif preclk'event and preclk='1' thenif n=1 thenif spks0='1' thenif jishu=2047-tone1 thenjishu<=0;spks_d<='0';elsif jishu<(2047-tone1)/8 thenspks_d<='1';jishu<=jishu+1;else spks_d<='0';jishu<=jishu+1;end if;else spks_d<='0';jishu<=0;end if;elsif n=2 thenif spks0='1' thenif jishu=2047-tone1 thenjishu<=0;spks_d<='0';elsif jishu<(2047-tone1)/16 thenspks_d<='1';jishu<=jishu+1;else spks_d<='0';jishu<=jishu+1;end if;else spks_d<='0';jishu<=0;end if;elsif n=3 thenif spks0='1' thenif jishu=2047-tone1 thenjishu<=0;spks_d<='0';elsif jishu<(2047-tone1)/32 thenspks_d<='1';jishu<=jishu+1;else spks_d<='0';jishu<=jishu+1;end if;else spks_d<='0';jishu<=0;end if;elsif n=4 thenif spks0='1' thenif jishu=2047-tone1 thenjishu<=0;spks_d<='0';elsif jishu<(2047-tone1)/128 thenspks_d<='1';jishu<=jishu+1;else spks_d<='0';jishu<=jishu+1;end if;else spks_d<='0';jishu<=0;end if;else spks_d<= spks0;end if;spks_a<= not spks_d;if a_d='0' thenspks<=spks_d;else spks<=spks_a ;end if;end if;end process;end rtl;rjy4600_mc_cnt：—音量分档调节library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rjy4600_mc_cnt isport(loud:in std_logic;loud_cnt:out std_logic_vector(3 downto 0));end rjy4600_mc_cnt;architecture rtl of rjy4600_mc_cnt issignal n:integer range 0 to 7:=0;beginprocess(loud)beginif loud'event and loud='1' thenif n<5 thenn<=n+1;else n<=0;end if;end if;end process;loud_cnt<=conv_std_logic_vector(n,4);end rtl;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity rjy4600_music_rom isport(clk:in std_logic;index:out std_logic_vector(3 downto 0));end rjy4600_music_rom;architecture behav of rjy4600_music_rom issubtype word is integer range 0 to 15;type memory is array(0 to 523) of word;signal rom:memory;signal clk_cnt:integer range 0 to 249;signal clk_4Hz:std_logic;signal adr:integer range 0 to 519;begindivide:process(clk)beginif clk'event and clk='1' thenif clk_cnt=249 thenclk_cnt<=0;clk_4Hz<='1';elseclk_cnt<=clk_cnt+1;clk_4Hz<='0';end if;end if;end process;cnt:process(clk_4Hz)beginif adr=523 thenadr<=0;elsif(clk_4Hz'event and clk_4Hz='1') thenadr<=adr+1;end if;end process;index<=conv_std_logic_vector(rom(adr),4);rom(0)<=3;rom(1)<=3;rom(2)<=3;rom(3)<=3;rom(4)<=5;rom(5)<=5;rom(6)<=5;rom(7)<=6;rom(8)<=8;rom(9)<=8;rom(10)<=8;rom(11)<=9;rom(12)<=6;rom(13)<=8;rom(14)<=5;rom(15)<=5;rom(16)<=12;rom(17)<=12;rom(18)<=12;rom(19)<=15; rom(20)<=13;rom(21)<=12;rom( 22) <=10;rom( 23) <=12; …………rjy4600_xiaod：—按键消抖library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity rjy4600_xiaod isport(clk_5Hz:in std_logic;key_in : in std_logic;key_out : out std_logic);end rjy4600_xiaod;ARCHITECTURE RTL OF rjy4600_xiaod IS beginprocess(key_in)beginif (key_in'event and key_in='1') then key_out<=clk_5Hz;end if;end process;END RTL;rjy4600_display：—动态译码及显示扫描process(s,din0,din1,din2,din3,din4,din5) beginif s="000" thensel<="000";num<=din0;led_dp<='0';elsif s="001" thensel<="001";num<=din1+"1010"; --------!!!!led_dp<='0';elsif s="010" thensel<="010";num<=din2;led_dp<='0';elsesel<="XXX";num<="XXXX";led_dp<='0';end if;end process;seg<="0111111"when num=0 else"0000110"when num=1 else"1011011"when num=2 else"1001111"when num=3 else"1100110"when num=4 else"1101101"when num=5 else"1111101"when num=6 else"0000111"when num=7 else"1111111"when num=8 else"1101111"when num=9 else"0001000"when num=10 else ----1110111"1000000"when num=11 else ----1111100"0000001"when num=12 else ----0111001"1011110"when num=13 else"1111001"when num=14 else"1110001"when num=15 else"0000000";end behave;。

EDA数字钟课程设计--用VHDL语言实现数字钟的设计

课程设计报告设计题目：用VHDL语言实现数字钟的设计班级：电子1002班学号：20102625姓名：于晓指导教师：李世平、李宁设计时间：2012年12月摘要数字钟是一种用数字电路技术实现时、分、秒计时的钟表。

本设计主要是实现数字钟的功能，程序用VHDL语言编写，整体采用TOP-TO-DOWN设计思路，具有基本的显示年月日时分秒和星期的功能，此外还有整点报时功能。

该数字钟的实现程序分为顶层模块、年月模块、日模块、时分秒定时模块、数码管显示模块、分频模块、星期模块，此外还有一个库。

该程序主要是用了元件例化的方法，此外还有进程等重要语句。

没有脉冲时，显示时分秒，set按钮产生第一个脉冲时，显示年月日，第2个脉冲到来时可预置年份，第3个脉冲到来时可预置月份，依次第4、5、6、7、8个脉冲到来时分别可预置日期、时、分、秒、星期，第 9个脉冲到来时设置星期后预置结束，正常工作，显示的是时分秒和星期。

调整设置通过Up来控制，UP为高电平，upclk有脉冲到达时，预置位加1，否则减1。

当整点到达时，报时器会鸣响，然后手动按键停止报时。

关键词：数字钟，VHDL，元件例化，数码管1、课程设计目的掌握利用可编程逻辑器件和EDA设计工具进行电子系统设计的方法2、课程设计内容及要求设计实现一个具有带预置数的数字钟，具有显示年月日时分秒的功能。

用6个数码管显示时分秒，set按钮产生第一个脉冲时，显示切换年月日，第2个脉冲到来时可预置年份，第3个脉冲到来时可预置月份，依次第4、5、6、7个脉冲到来时分别可预置日期、时、分、秒，第 8个脉冲到来后预置结束，正常工作，显示的是时分秒。

Up为高电平时，upclk有脉冲到达时，预置位加1.否则减1，还可以在此基础上增加其它功能。

3、VHDL程序设计3.1整体设计思路本设计采用top-down 模式设计，分模块进行，各功能都使用元件例化方式设计，主要有LED显示模块、时分秒定时模块、日期模块、年月模块、分频模块、星期模块，此外还创建了一个程序包，用来实现年月日、时分秒的加减调整。

EDA课程设计报告之数字时钟设计(免费哦~)

计算机科学与技术学院EDA课程设计报告设计题目：数字时钟的设计班级：姓名：学号：日期：2011年6月20日一、系统设计要求1、具有时、分、秒的计数显示功能，24小时循环显示。

2、具有异步清零、预置初值功能，实现LED动态显示，整点报时采用声音报时，几点报几下。

3、采用元件例化方式实现各模块间的连接。

二、系统设计方案1、整个模块采用两个时钟，一个时钟的频率为一秒，用于程序秒的输入。

另一个时钟频率较高，用于七段显示器的选择端口三八译码器的输入时钟。

2、时分秒皆采用两个位的计数，一位代表十位，一位代表个位。

分秒为60进制，时为24进制。

个位逢九向十位进一，秒逢59向分进一，分逢59向时进一。

3、在小时的子程序里把两位小时数转换成一位数作为报时程序的输入。

三、主要VHDL源程序秒—底层LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY SECOND ISPORT (CLK1,R:IN STD_LOGIC;CO1:OUT STD_LOGIC;S0,S1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END ;ARCHITECTURE XIA OF SECOND ISBEGINPROCESS(CLK1,R,SS0,SS1)VARIABLE SSS0,SSS1:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF R='1' THEN SSS0:="00000000";SSS1:="00000000";ELSIF CLK1'EVENT AND CLK1='1' THENIF SSS1="00000101" AND SSS0="00001001"THEN CO1<='1';SSS0:="00000000"; SSS1:="00000000";ELSIF SSS0="00001001" THEN SSS0:="00000000";SSS1:=SSS1+1;ELSE SSS0:=SSS0+1;CO1<='0';END IF;END IF;S0<=SSS0;S1<=SSS1;END PROCESS;END ;分—底层LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY MINUTE ISPORT (CLK2,R,S:IN STD_LOGIC;MM0,MM1:IN STD_LOGIC_VECTOR(3 DOWNTO 0);CO2:OUT STD_LOGIC;M0,M1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ;ARCHITECTURE XIA OF MINUTE ISBEGINPROCESS(CLK2,R,S,MM0,MM1)VARIABLE MMM0,MMM1:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF R='1' THEN MMM0:="0000";MMM1:="0000";ELSIF S='1' THEN MMM0:=MM0;MMM1:=MM1;ELSIF CLK2'EVENT AND CLK2='1' THENIF MMM1="0101" AND MMM0="1001"THEN CO2<='1';MMM0:="0000"; MMM1:="0000";ELSIF MMM0="1001" THEN MMM0:="0000";MMM1:=MMM1+1;CO2<='0'; ELSE MMM0:=MMM0+1;CO2<='0';END IF;END IF;M0<=MMM0;M1<=MMM1;END PROCESS;END ;时—底层LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.std_logic_unsigned.all;ENTITY HOUR ISPORT (CLK3,R,S:IN STD_LOGIC;HH0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);HH1:IN STD_LOGIC_VECTOR(1 DOWNTO 0);H0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);H1:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);NUMBER2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END ;ARCHITECTURE XIA OF HOUR ISBEGINPROCESS(CLK3,R,S,HH0,HH1)VARIABLE HHH0:STD_LOGIC_VECTOR(3 DOWNTO 0);VARIABLE HHH1:STD_LOGIC_VECTOR(1 DOWNTO 0);VARIABLE NUMBER1,NUMBER0:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF R='1' THEN HHH0:="0000";HHH1:="00";ELSIF S='1' THEN HHH0:=HH0;HHH1:=HH1;ELSIF CLK3'EVENT AND CLK3='1' THENIF HHH0="0011" AND HHH1="10"THEN HHH0:="0000";HHH1:="00";ELSIF HHH0="1001" THEN HHH1:=HHH1+1;HHH0:="0000";ELSE HHH0:=HHH0+1;END IF;END IF;H0<=HHH0;H1<=HHH1;IF HHH1="00" THEN NUMBER0:="00000000";ELSIF HHH1="01" THEN NUMBER0:="00001010";ELSIF HHH1="10" THEN NUMBER0:="00010100";END IF;NUMBER1:=NUMBER0+HHH0;IF NUMBER1="00000000" THEN NUMBER2<="00001100";ELSIF NUMBER1>"000001100" THEN NUMBER2<=NUMBER1-"00001100"; ELSE NUMBER2<=NUMBER1;END IF;END PROCESS;END ;报时—底层LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY RING ISPORT(CLK4,CLK5:IN STD_LOGIC;NUMBER:IN STD_LOGIC_VECTOR(7 DOWNTO 0);P:OUT STD_LOGIC);END;ARCHITECTURE ONE OF RING ISBEGINPROCESS(CLK4,CLK5,NUMBER)VARIABLE R:STD_LOGIC;VARIABLE TEX:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLK4='1' THENIF (NUMBER/="0000000"AND TEX<NUMBER) THEN R:=CLK5;ELSE R:='0';END IF;IF CLK5'EVENT AND CLK5='1' THENIF TEX<NUMBER THENTEX:=TEX+1;END IF;END IF;ELSE TEX:="00000000";END IF;P<=R;END PROCESS;END;显示—底层LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY dec7s ISPORT(a1,a2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);a3,a4,a5:IN STD_LOGIC_VECTOR(3 DOWNTO 0); a6:IN STD_LOGIC_VECTOR(1 DOWNTO 0);led7s1,led7s2,led7s3,led7s4,led7s5,led7s6 :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END;ARCHITECTURE one OF dec7s ISBEGINPROCESS(a1,a2,a3,a4,a5,a6)BEGINCASE a1 ISWHEN "00000000"=>led7s1<="00111111";WHEN "00000001"=>led7s1<="00000110";WHEN "00000010"=>led7s1<="01011011";WHEN "00000011"=>led7s1<="01001111";WHEN "00000100"=>led7s1<="01100110";WHEN "00000101"=>led7s1<="01101101";WHEN "00000110"=>led7s1<="01111101";WHEN "00000111"=>led7s1<="00000111";WHEN "00001000"=>led7s1<="01111111";WHEN "00001001"=>led7s1<="01101111";WHEN OTHERS=>led7s1<="11111111";END CASE;CASE a2 ISWHEN "00000000"=>led7s2<="00111111";WHEN "00000001"=>led7s2<="00000110";WHEN "00000010"=>led7s2<="01011011";WHEN "00000011"=>led7s2<="01001111";WHEN "00000100"=>led7s2<="01100110";WHEN "00000101"=>led7s2<="01101101";WHEN "00000110"=>led7s2<="01111101";WHEN "00000111"=>led7s2<="00000111";WHEN "00001000"=>led7s2<="01111111";WHEN "00001001"=>led7s2<="01101111";WHEN OTHERS=>led7s2<="11111111"; END CASE;CASE a3 ISWHEN "0000"=>led7s3<="00111111";WHEN "0001"=>led7s3<="00000110";WHEN "0010"=>led7s3<="01011011";WHEN "0011"=>led7s3<="01001111";WHEN "0100"=>led7s3<="01100110";WHEN "0101"=>led7s3<="01101101";WHEN "0110"=>led7s3<="01111101";WHEN "0111"=>led7s3<="00000111";WHEN "1000"=>led7s3<="01111111";WHEN "1001"=>led7s3<="01101111";WHEN OTHERS=>led7s3<="11111111"; END CASE;CASE a4 ISWHEN "0000"=>led7s4<="00111111";WHEN "0001"=>led7s4<="00000110";WHEN "0010"=>led7s4<="01011011";WHEN "0011"=>led7s4<="01001111";WHEN "0100"=>led7s4<="01100110";WHEN "0101"=>led7s4<="01101101";WHEN "0110"=>led7s4<="01111101";WHEN "0111"=>led7s4<="00000111";WHEN "1000"=>led7s4<="01111111";WHEN "1001"=>led7s4<="01101111";WHEN OTHERS=>led7s4<="11111111"; END CASE;CASE a5 ISWHEN "0000"=>led7s5<="00111111";WHEN "0001"=>led7s5<="00000110";WHEN "0010"=>led7s5<="01011011";WHEN "0011"=>led7s5<="01001111";WHEN "0100"=>led7s5<="01100110";WHEN "0101"=>led7s5<="01101101";WHEN "0110"=>led7s5<="01111101";WHEN "0111"=>led7s5<="00000111";WHEN "1000"=>led7s5<="01111111";WHEN "1001"=>led7s5<="01101111";WHEN OTHERS=>led7s5<="11111111"; END CASE;CASE a6 ISWHEN "00"=>led7s6<="00111111";WHEN "01"=>led7s6<="00000110";WHEN "10"=>led7s6<="01011011";WHEN OTHERS=>led7s6<="11111111"; END CASE;END PROCESS;END one;顶层LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;ENTITY TOP ISPORT (CP,CLK,R0,S0:IN STD_LOGIC;SM0,SM1,SH0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);SH1:IN STD_LOGIC_VECTOR(1 DOWNTO 0);SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);PP:OUT STD_LOGIC);END;ARCHITECTURE XIA OF TOP ISSIGNAL Y0,Y1:STD_LOGIC_VECTOR(7 DOWNTO 0);SIGNAL Y2,Y3,Y4:STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL Y5:STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL YY6,YY1,YY2,YY3,YY4,YY5,YY7,PNUMBER:STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL CO11,CO22:STD_LOGIC;component SECONDPORT (CLK1,R:IN STD_LOGIC;CO1:OUT STD_LOGIC;S0,S1:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));end component;component MINUTEPORT (CLK2,R,S:IN STD_LOGIC;MM0,MM1:IN STD_LOGIC_VECTOR(3 DOWNTO 0);CO2:OUT STD_LOGIC;M0,M1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));end component;component HOURPORT (CLK3,R,S:IN STD_LOGIC;HH0:IN STD_LOGIC_VECTOR(3 DOWNTO 0);HH1:IN STD_LOGIC_VECTOR(1 DOWNTO 0);H0:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);H1:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);NUMBER2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));end component;component RINGPORT(CLK4,CLK5:IN STD_LOGIC;NUMBER:IN STD_LOGIC_VECTOR(7 DOWNTO 0);P:OUT STD_LOGIC);end component;component dec7sPORT(a1,a2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);a3,a4,a5:IN STD_LOGIC_VECTOR(3 DOWNTO 0);a6:IN STD_LOGIC_VECTOR(1 DOWNTO 0);led7s1,led7s2,led7s3,led7s4,led7s5,led7s6:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));end component;BEGINYY7<="00000000";U1:SECOND PORT MAP(CLK1=>CLK,R=>R0,S0=>Y0,S1=>Y1,CO1=>CO11); U2:MINUTE PORT MAP(CLK2=>CO11,R=>R0,S=>S0,M0=>Y2,M1=>Y3,CO2=>CO22,MM0=>SM0,MM1=>SM1);U3:HOUR PORT MAP(CLK3=>CO22,R=>R0,S=>S0,H0=>Y4,H1=>Y5,HH0=>SH0,HH1=>SH1,NUMBER2=>PNUMBER);U4:RING PORT MAP(CLK4=>CO22,CLK5=>CLK,NUMBER=>PNUMBER,P=>PP); U5:dec7s PORT MAP(a1=>Y0,led7s1=>YY1,a2=>Y1,led7s2=>YY2,a3=>Y2,led7s3=>YY3,a4=>Y3,led7s4=>YY4,a5=>Y4,led7s5=>YY5,a6=>Y5,led7s6=>YY6);PROCESS(CP)VARIABLE SELL:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINIF CP'EVENT AND CP='1' THENIF SELL="111" THEN SELL:="000" ;ELSE SELL:=SELL+1;END IF;END IF;CASE SELL ISWHEN "000"=>Y<=YY1;WHEN "001"=>Y<=YY2;WHEN "010"=>Y<=YY3;WHEN "011"=>Y<=YY4;WHEN "100"=>Y<=YY5;WHEN "101"=>Y<=YY6;WHEN OTHERS=>Y<=YY7;END CASE;SEL<=SELL;END PROCESS;END;四、系统仿真/硬件验证五、设计中遇到的问题与体会自己想了哈。

EDA课程设计_数字时钟(闹钟)

课程设计说明书题目：闹钟学院（系）：年级专业：学号：学生姓名：指导教师：教师职称：目录第1章摘要 (1)第2章设计方案……………………………………………………………………………2.1 VHDL简介……………………………………………………………………………2.2 设计思路……………………………………………………………………………第3章模块介绍……………………………………………………………………………第4章 Verilog HDL设计源程序…………………………………………………………第5章波形仿真图…………………………………………………………………………第6章管脚锁定及硬件连线………………………………………………………………心得体会 (17)参考文献 (18)第一章摘要在当今社会，数字电路产品的应用在我们的实际生活中显得越来越重要，与我们的生活联系愈加紧密，例如计算机、仪表、电子钟等等，使我们的生活工作较以前的方式更加方便、完善，带来了很多的益处。

在此次EDA课程，我的设计课题是闹钟，使用VHDL语言进行编程完成。

报告书主要由设计方案、模块介绍、设计源程序、仿真波形图和管脚锁定及硬件连线四部分组成。

设计方案主要介绍了我对于设计课题的大致设计思路，之后各个部分将会详细介绍设计组成及程序。

第二章设计方案§2.1 VHDL简介数字电路主要是基于两个信号（我们可以简单的说是有电压和无电压），用数字信号完成对数字量进行算术运算和逻辑运算的电路我们称之为数字电路，它具有逻辑运算和逻辑处理等功能，数字电路可分为组合逻辑电路和时序逻辑电路。

EDA技术，就是以大规模可编程逻辑器件为设计载体，以硬件描述语言为系统逻辑描述的主要表达方式，以计算机、大规模可编程逻辑器件的开发软件及实验开发系统为设计工具，通过有关的开发软件，自动完成用软件的方式设计的电子系统到硬件系统的逻辑编译、逻辑化简、逻辑分割、逻辑综合及优化、逻辑布局布线、逻辑仿真，直至完成对于特定目标芯片的适配编译、逻辑映射、编程下载等工作，最终形成集成电子系统或专用集成芯片的一门新技术。

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附录一、12/24小时数字时钟VHDL设计1，系统顶层逻辑图：时序仿真波形管脚定义以及锁定2，分频模块。

①各个分频模块的模块图：②，分别对应的仿真波形：③50mhz分频至1k模块代码：library ieee;use ieee.std_logic_unsigned.all;use ieee.std_logic_1164.all;entity wh4574_divto1k isport(clk50m:in std_logic;clk1k:out std_logic);end wh4574_divto1k;architecture behav of wh4574_divto1k is signal count1:std_logic_vector(14 downto 0);signal count2:std_logic;signal co:std_logic;beginprocess(clk50m)beginif clk50m'event and clk50m='1' thenif count1="110000110100111" then count1<="000000000000000";co<='1';elsecount1<=count1+'1';co<='0';end if;end if;end process;process(co)beginif co'event and co='1' thencount2<=not count2;end if;end process;clk1k<=count2;end behav;50mhz分频至2k模块代码：library ieee;use ieee.std_logic_unsigned.all;use ieee.std_logic_1164.all;entity wh4574_divto2k isport(clk50m:in std_logic;clk2k:out std_logic);end wh4574_divto2k;architecture behav of wh4574_divto2k is signal count1:std_logic_vector(13 downto 0);signal count2:std_logic;signal co:std_logic;beginprocess(clk50m)beginif clk50m'event and clk50m='1' thenif count1="11000011010011" thencount1<="00000000000000";co<='1';elsecount1<=count1+'1';co<='0';end if;end if;end process;process(co)beginif co'event and co='1' thencount2<=not count2;end if;end process;clk2k<=count2;end behav;1k分频至5hz代码：library ieee;use ieee.std_logic_unsigned.all;use ieee.std_logic_1164.all;entity wh4574_div1kto5 isport(inclk1k:in std_logic;clk5hz:out std_logic);end wh4574_div1kto5;architecture behav of wh4574_div1kto5 is signal count1:std_logic_vector(6 downto 0);signal count2:std_logic;signal co:std_logic;beginprocess(inclk1k)beginif inclk1k'event and inclk1k='1' thenif count1="1100011" thencount1<="0000000";co<='1';elsecount1<=count1+'1';co<='0';end if;end if;end process;process(co)beginif co'event and co='1' thencount2<=not count2;end if;end process;clk5hz<=count2;end behav;5分频代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wh4574_div_5 isport(clk:in std_logic;q:out std_logic);end wh4574_div_5;architecture behav of wh4574_div_5 is signal count:std_logic_vector(2 downto 0); beginprocess(clk)beginif clk'event and clk='1' thenif count="100"thencount<="000";q<='1';elsecount<=count+1;q<='0';end if;end if;end process;end behav;3，按键去抖动模块，二选一模块。

①模块图：②时序仿真波形依次为：③源代码：按键去抖动：library ieee;use ieee.std_logic_unsigned.all;use ieee.std_logic_1164.all;entity wh4574_qudou isport(clk,keyin :in std_logic;keyout:out std_logic);end wh4574_qudou;architecture behav of wh4574_qu dou isbeginprocess(clk)variable count1,count2:std_logic _vector(3 downto 0);beginif clk'event and clk='1' thenif keyin='0' thenif count1="0101" thenkeyout<='0';else count1:=count1+1;end if;elsif keyin='1' thenif count2="0101" thenkeyout<='1';else count2:=count2+1;end if;end if;end if;end process;end behav;二选一数选器：library ieee;use ieee.std_logic_1164.all;entity wh4574_T_mux2 isport(sel,a,b:in std_logic;q:out std_logic);end wh4574_T_mux2;architecture bav of wh4574_T_mux2 is beginprocess(sel,a,b)beginif sel='1' thenq<=a;elseq<=b;end if;end process;end bav;4，24,60进制计数器模块，24小时转12小时模块，动态译码显示模块。

①模块图：②时序仿真波形图。

24进制计数波形：60进制仿真波形：24小时制转12小时制：③，程序源代码.24进制计数器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wh4574_count24 isport(CLK:in std_logic;bcd10,bcd1:buffer std_logic_vector(3 downto 0);CO:OUT STD_LOGIC);end wh4574_count24;architecture behav of wh4574_count24 is beginprocess(CLK,bcd10)beginif CLK'EVENT AND CLK='1' THENif bcd10="0010"and bcd1="0011" th enbcd1<="0000";CO<='1';elsif bcd1="1001" thenbcd1<="0000";CO<='0';elsebcd1<=bcd1+'1';CO<='0';end if;end if;end process;process(CLK,bcd1)beginif CLK'event and CLK='1' thenif bcd1="0011"and bcd10="0010" th enbcd10<="0000";elsif bcd1="1001" thenbcd10<=bcd10+'1';end if;end if;end process;end behav;60进制：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wh4574_count60 isport(clk:in std_logic;bcd10,bcd1:buffer std_logic_vector(3 downto 0);preset:in std_logic;co:out std_logic);end wh4574_count60;architecture rtl of wh4574_count60 is signal co_1:std_logic;beginprocess(clk,preset)beginif preset='0' thenbcd1<="0000";elseif clk='1'and clk'event thenif bcd1="1001" thenbcd1<="0000";elsebcd1<=bcd1+'1';end if;end if;end if;end process;process(clk,preset,bcd1)beginif preset='0' thenbcd10<="0000";co_1<='0';elseif clk='1'and clk'event thenif bcd1="1000"and bcd10="0101" th enco_1<='1';elsif bcd1="1001"and bcd10="0101" thenbcd10<="0000";co_1<='0';elsif bcd1="1001" thenbcd10<=bcd10+'1';co_1<='0';end if;end if;end if;end process;co<=not co_1;end rtl;24转换12library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wh4574_trans isport(clk:in std_logic;switchP:in std_logic;T24_10,T24_1:in std_logic_vector(3 downto 0);T12_10,T12_1:buffer std_logic_vect or(3 downto 0));end wh4574_trans;architecture behav of wh4574_trans is beginprocess(T24_10,T24_1)begincase switchP&T24_10&T24_1 iswhen "100000000"=>T12_10<="000 0";T12_1<="0000";when "100000001"=>T12_10<="000 0";T12_1<="0001";when "100000010"=>T12_10<="000 0";T12_1<="0010";when "100000011"=>T12_10<="000 0";T12_1<="0011";when "100000100"=>T12_10<="000 0";T12_1<="0100";when "100000101"=>T12_10<="0000";T12_1<="0101";when "100000110"=>T12_10<="000 0";T12_1<="0110";when "100000111"=>T12_10<="000 0";T12_1<="0111";when "100001000"=>T12_10<="000 0";T12_1<="1000";when "100001001"=>T12_10<="000 0";T12_1<="1001";when "100010000"=>T12_10<="000 1";T12_1<="0000";when "100010001"=>T12_10<="000 1";T12_1<="0001";when "100010010"=>T12_10<="000 0";T12_1<="0000";when "100010011"=>T12_10<="000 0";T12_1<="0001";when "100010100"=>T12_10<="000 0";T12_1<="0010";when "100010101"=>T12_10<="000 0";T12_1<="0011";when "100010110"=>T12_10<="000 0";T12_1<="0100";when "100010111"=>T12_10<="000 0";T12_1<="0101";when "100011000"=>T12_10<="000 0";T12_1<="0110";when "100011001"=>T12_10<="000 0";T12_1<="0111";when "100100000"=>T12_10<="000 0";T12_1<="1000";when "100100001"=>T12_10<="000 0";T12_1<="1001";when "100100010"=>T12_10<="000 1";T12_1<="0000";when "100100011"=>T12_10<="000 1";T12_1<="0001";when "100100100"=>T12_10<="000 0";T12_1<="0000";when "000000000"=>T12_10<="000 0";T12_1<="0000";when "000000001"=>T12_10<="000 0";T12_1<="0001";when "000000010"=>T12_10<="0000";T12_1<="0010";when "000000011"=>T12_10<="000 0";T12_1<="0011";when "000000100"=>T12_10<="000 0";T12_1<="0100";when "000000101"=>T12_10<="000 0";T12_1<="0101";when "000000110"=>T12_10<="000 0";T12_1<="0110";when "000000111"=>T12_10<="000 0";T12_1<="0111";when "000001000"=>T12_10<="000 0";T12_1<="1000";when "000001001"=>T12_10<="000 0";T12_1<="1001";when "000010000"=>T12_10<="000 1";T12_1<="0000";when "000010001"=>T12_10<="000 1";T12_1<="0001";when "000010010"=>T12_10<="000 1";T12_1<="0010";when "000010011"=>T12_10<="000 1";T12_1<="0011";when "000010100"=>T12_10<="000 1";T12_1<="0100";when "000010101"=>T12_10<="000 1";T12_1<="0101";when "000010110"=>T12_10<="000 1";T12_1<="0110";when "000010111"=>T12_10<="000 1";T12_1<="0111";when "000011000"=>T12_10<="000 1";T12_1<="1000";when "000011001"=>T12_10<="000 1";T12_1<="1001";when "000100000"=>T12_10<="001 0";T12_1<="0000";when "000100001"=>T12_10<="001 0";T12_1<="0001";when "000100010"=>T12_10<="001 0";T12_1<="0010";when "000100011"=>T12_10<="001 0";T12_1<="0011";when "000100100"=>T12_10<="0010";T12_1<="0100";when others=>T12_10<="ZZZZ";T12 _1<="ZZZZ";end case;end process;end behav;动态译码显示模块library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wh4574_led isport(din0,din1,din2,din3,din4,din5,din6,din7:i n std_logic_vector(3 downto 0);clk:in std_logic;led_sa,led_sb,led_sc:out std_logic;led_a,led_b,led_c,led_d,led_e,led_f,led _g,led_dp:out std_logic);end entity;architecture behav of wh4574_led is signal seg:std_logic_vector(6 downto 0); signal sel:std_logic_vector( 2 downto 0); signal num:std_logic_vector(3 downto 0); signal s:std_logic_vector(2 downto 0); beginled_sa<=sel(0);led_sb<=sel(1);led_sc<=sel(2);led_a<=seg(0);led_b<=seg(1);led_c<=seg(2);led_d<=seg(3);led_e<=seg(4);led_f<=seg(5);led_g<=seg(6);process(clk)beginif rising_edge(clk) thenif s="111" thens<="000";else s<=s+'1';end if;end if;end process;process(s,din0,din1,din2,din3,din4,din5,din6, din7)beginif s="000" thensel<="000";num<=din0;led_dp<='0';elsif s="001" thensel<="001" ;num<=din1;led_dp<='0';elsif s="010" thensel<="010" ;num<=din2;led_dp<='1';elsif s="011" thensel<="011" ;num<=din3;led_dp<='0';elsif s="100" thensel<="100" ;num<=din4;led_dp<='1';elsif s="101" thensel<="101" ;num<=din5;led_dp<='0';elsif s="110" thensel<="110";num<=din6;led_dp<='0';elsesel<="111";num<=din7;led_dp<='0';end if;end process;seg<="0111111" when num=0 else"0000110" when num=1 else "1011011" when num=2 else "1001111" when num=3 else "1100110" when num=4 else "1101101" when num=5 else "1111101" when num=6 else "0000111" when num=7 else "1111111" when num=8 else "1101111" when num=9 else "1110111" when num=10 else "1111100" when num=11 else "0111001" when num=12 else "1011110" when num=13 else "ZZZZZZZ" when num=14 else "1110001" when num=15 else "ZZZZZZZ";end behav;5，整点报时模块：①，模块图：②，时序仿真波形③，源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity wh4574_chuck isport(clk_2K,clk_1K,clk1:in std_logic;ss,s,mm,m:in std_logic_vector(3 do wnto 0);buzz:out std_logic);end wh4574_chuck;architecture behav of wh4574_chuck is signal buzz_1:std_logic;beginprocess(ss,s,mm,m,clk_2K,clk_1K,clk1) beginif (mm="0101" and m="1001") and (ss ="0101") and (s>4) and (s<=9) thenif clk1='1' thenbuzz_1<=clk_1K;elsebuzz_1<='Z';end if;elsif (mm="0000" and m="0000") and (ss="0000") and (s="0000") thenif clk1='1' thenbuzz_1<=clk_2K;elsebuzz_1<='Z';end if;elsebuzz_1<='Z';end if;buzz<=buzz_1;end process;end behav;二乐曲播放电路设计1 电路系统逻辑顶层图：时序仿真波形：管脚定义锁定表：2乐曲节拍发生器模块：①，模块图及时序仿真波形：②，程序源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity wh4574_music_rom isport(clk,back,pause: in std_logic;index: out std_logic_vector(3 downto 0);set1: in std_logic_vector(3 downto 0)); end wh4574_music_rom;architecture behav of wh4574_music_rom is subtype word is integer range 0 to 15;type memory is array(0 to 523) of word; signal rom: memory;signal clk_cnt: integer range 0 to 249; signal clk_4Hz: std_logic;signal adr: integer range 0 to 523;begindivide: process(clk)beginif (clk'event and clk ='1') thenif clk_cnt=249 thenclk_cnt<=0;clk_4Hz<='1';elseclk_cnt<=clk_cnt+1;clk_4Hz<='0';end if;end if;end process;cnt:process(clk_4Hz,back,pause)beginif pause='1' thenif adr=523 thenadr<=0;elsif (back='0') thenadr<=0;elsif (clk_4Hz'event and clk_4Hz='1'and back='1') thenadr<=adr+1;end if;elsenull;end if;end process;music:process(set1)beginif set1="0011" thenindex<=conv_std_logic_vector(rom(adr),4); rom(0)<=0;rom(1)<=0;rom(2)<=0;rom(3)<=5; rom(4)<=8;rom(5)<=5;rom(6)<=8;rom(7)<=9; rom(8)<=11;rom(9)<=11;rom(10)<=10;rom(11 )<=9;rom(12)<=9;rom(13)<=10;rom(14)<=10;rom(1 5)<=0;rom(16)<=0;rom(17)<=0;rom(18)<=0;rom(19) <=5;rom(20)<=8;rom(21)<=5;rom(22)<=8;rom(23) <=9;rom(24)<=11;rom(25)<=11;rom(26)<=10;rom( 27)<=9;rom(28)<=9;rom(29)<=10;rom(30)<=9;rom(31 )<=8;rom(32)<=8;rom(33)<=8;rom(34)<=0;rom(35)<=0;<=9;rom(40)<=11;rom(41)<=11;rom(42)<=9;rom(4 3)<=8;rom(44)<=8;rom(45)<=6;rom(46)<=6;rom(47) <=5;rom(48)<=5;rom(49)<=5;rom(50)<=5;rom(51) <=5;rom(52)<=0;rom(53)<=0;rom(54)<=0;rom(55) <=0;rom(56)<=0;rom(57)<=0;rom(58)<=0;rom(59) <=5;rom(60)<=8;rom(61)<=5;rom(62)<=8;rom(63) <=9;rom(64)<=11;rom(65)<=11;rom(66)<=10;rom( 67)<=9;rom(68)<=9;rom(69)<=10;rom(70)<=10;rom(7 1)<=0;rom(72)<=0;rom(73)<=0;rom(74)<=0;rom(75) <=5;rom(76)<=8;rom(77)<=5;rom(78)<=8;rom(79) <=9;rom(80)<=11;rom(81)<=11;rom(82)<=10;rom( 83)<=9;rom(84)<=9;rom(85)<=10;rom(86)<=9;rom(87 )<=8;rom(88)<=8;rom(89)<=8;rom(90)<=0;rom(91) <=13;rom(92)<=13;rom(93)<=11;rom(94)<=11;rom( 95)<=10;rom(96)<=9;rom(97)<=9;rom(98)<=8;rom(99) <=9;rom(100)<=9;rom(101)<=8;rom(102)<=10;ro m(103)<=8;rom(104)<=8;rom(105)<=8;rom(106)<=8;rom( 107)<=8;rom(108)<=9;rom(109)<=10;rom(110)<=10;ro m(111)<=9;rom(112)<=9;rom(113)<=9;rom(114)<=9;rom( 115)<=9;rom(116)<=0;rom(117)<=7;rom(118)<=8;rom( 119)<=7;rom(120)<=6;rom(121)<=6;rom(122)<=6;rom( 123)<=12; om(127)<=13;rom(128)<=12;rom(129)<=12;rom(130)<=11;r om(131)<=11;rom(132)<=10;rom(133)<=10;rom(134)<=10;r om(135)<=10;rom(136)<=11;rom(137)<=10;rom(138)<=11;r om(139)<=11;rom(140)<=8;rom(141)<=8;rom(142)<=8;rom( 143)<=8;rom(148)<=9;rom(149)<=10;rom(150)<=10;ro m(151)<=10;rom(152)<=10;rom(153)<=10;rom(154)<=0;ro m(155)<=7;rom(156)<=8;rom(157)<=7;rom(158)<=6;rom( 159)<=6;rom(160)<=6;rom(161)<=8;rom(162)<=8;rom( 163)<=8;rom(164)<=9;rom(165)<=9;rom(166)<=7;rom( 167)<=7;rom(168)<=8;rom(169)<=8;rom(170)<=9;rom( 171)<=9;rom(172)<=9;rom(173)<=9;rom(174)<=9;rom( 175)<=10;rom(176)<=11;rom(177)<=11;rom(178)<=9;ro m(179)<=10;rom(180)<=10;rom(181)<=11;rom(182)<=13;r om(183)<=12;rom(184)<=12;rom(185)<=12;rom(186)<=12;r om(187)<=12;rom(188)<=8;rom(189)<=8;rom(190)<=9;rom( 191)<=9;rom(192)<=12;rom(193)<=12;rom(194)<=12;r om(195)<=8;rom(196)<=8;rom(197)<=9;rom(198)<=9;rom( 199)<=8;rom(200)<=12;rom(201)<=12;rom(202)<=12;r om(203)<=12;rom(204)<=0;rom(205)<=10;rom(206)<=10;ro m(207)<=12;rom(208)<=13;rom(209)<=13;rom(210)<=10;r om(211)<=9;rom(212)<=9;rom(213)<=8;rom(214)<=8;rom( 215)<=12;om(219)<=12;rom(220)<=0;rom(221)<=10;rom(222)<=10;ro m(223)<=12;rom(224)<=13;rom(225)<=13;rom(226)<=15;r om(227)<=14;rom(228)<=14;rom(229)<=13;rom(230)<=13;r om(231)<=12;rom(232)<=12;rom(233)<=10;rom(234)<=9;ro m(235)<=8;rom(236)<=8;rom(237)<=8;rom(238)<=6;rom( 239)<=8;rom(240)<=11;rom(241)<=11;rom(242)<=10;r om(243)<=9;rom(244)<=9;rom(245)<=8;rom(246)<=9;rom( 247)<=9;rom(248)<=9;rom(249)<=9;rom(250)<=9;rom( 251)<=9;rom(252)<=8;rom(253)<=8;rom(254)<=9;rom( 255)<=9;rom(256)<=12;rom(257)<=12;rom(258)<=12;r om(259)<=8;rom(260)<=8;rom(261)<=9;rom(262)<=9;rom( 263)<=8;rom(264)<=12;rom(265)<=12;rom(266)<=12;r om(267)<=12;rom(268)<=0;rom(269)<=10;rom(270)<=10;ro m(271)<=12;rom(272)<=13;rom(273)<=13;rom(274)<=15;r om(275)<=14;rom(276)<=14;rom(277)<=13;rom(278)<=13;r om(279)<=12;rom(280)<=12;rom(281)<=12;rom(282)<=12;r om(283)<=12;rom(284)<=0;rom(285)<=10;rom(286)<=10;ro m(287)<=12;rom(288)<=13;rom(289)<=13;rom(290)<=15;r om(291)<=14;rom(292)<=14;rom(293)<=13;rom(294)<=13;r om(295)<=12;rom(296)<=12;rom(297)<=10;rom(298)<=14;r om(299)<=15;rom(300)<=15;rom(301)<=15;rom(302)<=10;r om(303)<=10; om(307)<=9;rom(308)<=9;rom(309)<=8;rom(310)<=8;rom( 311)<=8;rom(312)<=8;rom(313)<=8;rom(314)<=8;rom( 315)<=8;rom(316)<=8;rom(317)<=8;rom(318)<=8;rom( 319)<=8;rom(320)<=0;rom(321)<=0;rom(322)<=0;rom( 323)<=0;rom(324)<=0;rom(325)<=0;rom(326)<=0;rom( 327)<=0;rom(328)<=0;rom(329)<=0;rom(330)<=0;rom( 331)<=0;rom(332)<=0;rom(333)<=0;rom(334)<=0;rom( 335)<=0;rom(336)<=0;rom(337)<=0;rom(338)<=0;rom( 339)<=0;rom(340)<=0;rom(341)<=0;rom(342)<=0;rom( 343)<=0;rom(344)<=0;rom(345)<=0;rom(346)<=0;rom( 347)<=0;rom(348)<=0;rom(349)<=0;rom(350)<=0;rom( 351)<=0;rom(352)<=0;rom(353)<=0;rom(354)<=0;rom( 355)<=0;rom(356)<=0;rom(357)<=0;rom(358)<=0;rom( 359)<=0;rom(360)<=0;rom(361)<=0;rom(362)<=0;rom( 363)<=0;rom(364)<=0;rom(365)<=0;rom(366)<=0;rom( 367)<=0;rom(368)<=0;rom(369)<=0;rom(370)<=0;rom( 371)<=0;rom(372)<=0;rom(373)<=0;rom(374)<=0;rom( 375)<=0;rom(376)<=0;rom(377)<=0;rom(378)<=0;rom( 379)<=0;rom(380)<=0;rom(381)<=0;rom(382)<=0;rom( 383)<=0;rom(384)<=0;rom(385)<=0;rom(386)<=0;rom( 387)<=0;rom(388)<=0;rom(389)<=0;rom(390)<=0;rom( 391)<=0;rom(392)<=0;rom(393)<=0;rom(394)<=0;rom( 395)<=0;rom(396)<=0;rom(397)<=0;rom(398)<=0;rom( 399)<=0;rom(400)<=0;rom(401)<=0;rom(402)<=0;rom( 403)<=0;rom(404)<=0;rom(405)<=0;rom(406)<=0;rom( 407)<=0;rom(408)<=0;rom(409)<=0;rom(410)<=0;rom( 411)<=0;rom(412)<=0;rom(413)<=0;rom(414)<=0;rom( 415)<=0;rom(416)<=0;rom(417)<=0;rom(418)<=0;rom( 419)<=0;rom(420)<=0;rom(421)<=0;rom(422)<=0;rom( 423)<=0;rom(424)<=0;rom(425)<=0;rom(426)<=0;rom( 427)<=0;rom(428)<=0;rom(429)<=0;rom(430)<=0;rom( 431)<=0;rom(432)<=0;rom(433)<=0;rom(434)<=0;rom( 435)<=0;rom(436)<=0;rom(437)<=0;rom(438)<=0;rom( 439)<=0;rom(440)<=0;rom(441)<=0;rom(442)<=0;rom( 443)<=0;rom(444)<=0;rom(445)<=0;rom(446)<=0;rom( 447)<=0;rom(448)<=0;rom(449)<=0;rom(450)<=0;rom( 451)<=0;rom(452)<=0;rom(453)<=0;rom(454)<=0;rom( 455)<=0;rom(456)<=0;rom(457)<=0;rom(458)<=0;rom( 459)<=0;rom(460)<=0;rom(461)<=0;rom(462)<=0;rom( 463)<=0;rom(464)<=0;rom(465)<=0;rom(466)<=0;rom( 467)<=0;rom(468)<=0;rom(469)<=0;rom(470)<=0;rom( 471)<=0;elsif set1="0001" thenindex<=conv_std_logic_vector(rom(adr),4); rom(0)<=8;rom(1)<=8;rom(2)<=7;rom(3)<=8; rom(4)<=12;rom(5)<=12;rom(6)<=12;rom(7)< =12;rom(8)<=8;rom(9)<=8;rom(10)<=7;rom(11)<= 8;rom(12)<=10;rom(13)<=10;rom(14)<=10;rom( 15)<=10;rom(16)<=8;rom(17)<=8;rom(18)<=7;rom(19) <=8;rom(20)<=5;rom(21)<=5;rom(22)<=10;rom(23 )<=10;rom(24)<=9;rom(25)<=6;rom(26)<=7;rom(27) <=8;rom(28)<=9;rom(29)<=9;rom(30)<=9;rom(31) <=9;rom(32)<=8;rom(33)<=8;rom(34)<=7;rom(35) <=8;rom(36)<=12;rom(37)<=12;rom(38)<=12;rom( 39)<=12;rom(40)<=13;rom(41)<=13;rom(42)<=14;rom( 43)<=13;rom(44)<=10;rom(45)<=10;rom(46)<=10;rom( 47)<=10;rom(48)<=13;rom(49)<=13;rom(50)<=14;rom( 51)<=15;rom(52)<=12;rom(53)<=12;rom(54)<=10;rom( 55)<=10;rom(56)<=11;rom(57)<=10;rom(58)<=6;rom(5 9)<=9;rom(60)<=8;rom(61)<=8;rom(62)<=8;rom(63) <=8;rom(64)<=8;rom(65)<=8;rom(66)<=7;rom(67) <=8;rom(68)<=12;rom(69)<=12;rom(70)<=12;rom( 71)<=12;rom(72)<=8;rom(73)<=8;rom(74)<=7;rom(75) <=8;rom(76)<=10;rom(77)<=10;rom(78)<=10;rom( 79)<=10;rom(80)<=8;rom(81)<=8;rom(82)<=7;rom(83) <=8;rom(84)<=5;rom(85)<=5;rom(86)<=10;rom(87 )<=10;rom(88)<=9;rom(89)<=6;rom(90)<=7;rom(91) <=8;rom(92)<=9;rom(93)<=9;rom(94)<=9;rom(95) <=9;rom(96)<=8;rom(97)<=8;rom(98)<=7;rom(99) <=8;rom(100)<=12;rom(101)<=12;rom(102)<=12;r om(103)<=12;rom(104)<=13;rom(105)<=13;rom(106)<=14;r om(107)<=15;rom(108)<=12;rom(109)<=12;rom(110)<=12;r om(111)<=12;rom(112)<=13;rom(113)<=13;rom(114)<=14;r om(115)<=15;rom(116)<=12;rom(117)<=12;rom(118)<=10;r om(119)<=10;rom(120)<=11;rom(121)<=10;rom(122)<=5;ro m(123)<=9;rom(124)<=8;rom(125)<=5;rom(126)<=15;ro m(127)<=14;rom(128)<=13;rom(129)<=13;rom(130)<=11;r om(131)<=9;rom(132)<=9;rom(133)<=5;rom(134)<=14;ro m(135)<=13;rom(136)<=12;rom(137)<=12;rom(138)<=9;ro m(139)<=8;rom(140)<=8;rom(141)<=8;rom(142)<=9;rom( 143)<=10;rom(144)<=11;rom(145)<=11;rom(146)<=11;r om(147)<=13;rom(148)<=12;rom(149)<=12;rom(150)<=10;r om(151)<=9;rom(152)<=10;rom(153)<=10;rom(154)<=11;r om(155)<=11;rom(156)<=12;rom(157)<=8;rom(158)<=15;ro m(159)<=14;rom(160)<=13;rom(161)<=13;rom(162)<=11;r om(163)<=11;rom(164)<=14;rom(165)<=15;rom(166)<=15;r om(167)<=15;rom(168)<=12;rom(169)<=12;rom(170)<=15;r om(171)<=14;rom(172)<=15;rom(173)<=15;rom(174)<=15;r om(175)<=13;rom(176)<=14;rom(177)<=15;rom(178)<=15;r om(179)<=15; rom(180)<=13;rom(181)<=14;rom(182)<=15;r om(183)<=15;rom(184)<=15;rom(185)<=15;rom(186)<=12;r om(187)<=12;rom(188)<=12;rom(189)<=12;rom(190)<=0;ro m(191)<=8;rom(192)<=15;rom(193)<=14;rom(194)<=13;r om(195)<=13;rom(196)<=11;rom(197)<=9;rom(198)<=9;ro m(199)<=7;rom(200)<=14;rom(201)<=13;rom(202)<=12;r om(203)<=12;rom(204)<=9;rom(205)<=8;rom(206)<=8;rom( 207)<=8;rom(208)<=9;rom(209)<=10;rom(210)<=11;ro m(211)<=11;rom(212)<=11;rom(213)<=13;rom(214)<=12;r om(215)<=12;rom(216)<=10;rom(217)<=9;rom(218)<=10;ro m(219)<=10;rom(220)<=10;rom(221)<=11;rom(222)<=12;r om(223)<=8;rom(224)<=15;rom(225)<=14;rom(226)<=13;r om(227)<=13;rom(228)<=11;rom(229)<=11;rom(230)<=14;r om(231)<=15;rom(232)<=15;rom(233)<=15;rom(234)<=12;r om(235)<=12;rom(236)<=9;rom(237)<=14;rom(238)<=15;ro m(239)<=15;rom(240)<=15;rom(241)<=13;rom(242)<=14;r om(243)<=15;rom(244)<=15;rom(245)<=15;rom(246)<=13;r om(247)<=14;rom(248)<=15;rom(249)<=15;rom(250)<=15;r om(251)<=9;rom(252)<=9;rom(253)<=9;rom(254)<=15;ro m(255)<=15;rom(256)<=14;rom(257)<=14;rom(258)<=12;r om(259)<=12;rom(260)<=8;rom(261)<=8;rom(262)<=7;rom( 263)<=8;rom(264)<=12;rom(265)<=12;rom(266)<=12;r om(267)<=12;。