半导体制造技术(1)
半导体工艺讲解
半导体⼯艺讲解半导体⼯艺讲解(1)--掩模和光刻（上）概述光刻⼯艺是半导体制造中最为重要的⼯艺步骤之⼀。
主要作⽤是将掩膜板上的图形复制到硅⽚上，为下⼀步进⾏刻蚀或者离⼦注⼊⼯序做好准备。
光刻的成本约为整个硅⽚制造⼯艺的1/3，耗费时间约占整个硅⽚⼯艺的40～60%。
光刻机是⽣产线上最贵的机台，5～15百万美元/台。
主要是贵在成像系统（由15～20个直径为200～300mm的透镜组成）和定位系统（定位精度⼩于10nm）。
其折旧速度⾮常快，⼤约3～9万⼈民币/天，所以也称之为印钞机。
光刻部分的主要机台包括两部分：轨道机（Tracker），⽤于涂胶显影；扫描曝光机（Scanning )光刻⼯艺的要求：光刻⼯具具有⾼的分辨率；光刻胶具有⾼的光学敏感性；准确地对准；⼤尺⼨硅⽚的制造；低的缺陷密度。
光刻⼯艺过程⼀般的光刻⼯艺要经历硅⽚表⾯清洗烘⼲、涂底、旋涂光刻胶、软烘、对准曝光、后烘、显影、硬烘、刻蚀、检测等⼯序。
1、硅⽚清洗烘⼲（Cleaning and Pre-Baking）⽅法：湿法清洗＋去离⼦⽔冲洗＋脱⽔烘焙（热板150～2500C,1～2分钟，氮⽓保护）⽬的：a、除去表⾯的污染物（颗粒、有机物、⼯艺残余、可动离⼦）；b、除去⽔蒸⽓，是基底表⾯由亲⽔性变为憎⽔性，增强表⾯的黏附性（对光刻胶或者是HMDS-〉六甲基⼆硅胺烷）。
2、涂底（Priming)⽅法：a、⽓相成底膜的热板涂底。
HMDS蒸⽓淀积，200～2500C,30秒钟；优点：涂底均匀、避免颗粒污染； b、旋转涂底。
缺点：颗粒污染、涂底不均匀、HMDS⽤量⼤。
⽬的：使表⾯具有疏⽔性，增强基底表⾯与光刻胶的黏附性。
3、旋转涂胶（Spin-on PR Coating）⽅法：a、静态涂胶（Static）。
硅⽚静⽌时，滴胶、加速旋转、甩胶、挥发溶剂（原光刻胶的溶剂约占65～85%,旋涂后约占10～20%）；b、动态（Dynamic）。
低速旋转（500rpm_rotation per minute）、滴胶、加速旋转（3000rpm）、甩胶、挥发溶剂。
半导体制造技术导论离子注入工艺
• 阈值电压控制：通过离子注入工艺调节PMOS和NMOS
区
的阈值电压
• NMOS器件：N型半导体作为沟道，P型半导体作为源漏
• 掺杂区形成：通过离子注入工艺形成PMOS和NMOS的
区
源漏区
离子注入工艺在光电二极管中的应用
光电二极管的结构特点
• P-N结：由P型半导体和N型半导体组成的结
• 光敏区：位于P-N结附近的区域，对光敏感
• 掺杂浓度均匀性：如何实现更均匀的掺杂，提高器件性能
• 注入损伤：离子注入过程中如何减少对半导体材料的损伤
• 工艺集成：如何将离子注入工艺与其他工艺集成，提高生产效率
解决方案
• 优化离子注入设备和工艺：提高掺杂浓度的均匀性和降低注入损伤
• 采用新型离子注入技术：如扫描离子注入、等离子体浸入离子注入等，提高工艺效
• 多离子注入技术的发展：实现多种元素的共注入，提高器件的性能和可靠性
离子注入工艺的发展方向
• 精确控制掺杂：实现更精确的浓度控制和更均匀的掺杂
• 降低能耗优化离子注入设备和工艺，降低能耗
• 环保减排：减少离子注入过程中的污染排放，提高环保水平
离子注入工艺面临的挑战及解决方案
离子注入工艺面临的挑战
果
• 加强工艺集成：与光刻、刻蚀等工艺进行集成，提高生产效率
离子注入工艺在未来半导体制造中的应用前景
离子注入工艺在集成电路制造中的应用
• 提高晶体管、二极管等器件的性能，提高集成电路的整体性能
• 实现新型器件的制作，如鳍式场效应晶体管（FinFET）等
离子注入工艺在光电二极管制造中的应用
• 提高光电二极管的光电转换效率，提高光电传感器的性能
• 大电流器件：需要承受大电流的器件
半导体制造技术智慧树知到答案章节测试2023年上海工程技术大学
第一章测试1.“摩尔定律”是（）提出的？A:1965年B:1958年C:1960D:1970年答案:A2.第一个晶体管是（）材料晶体管？A:锗B:硅C:碳答案:A3.戈登摩尔是（）科学家。
A:德国B:美国C:法国D:英国答案:B4.第一个集成电路在（）被研制。
A:1960B:1955C:1965D:1958答案:D5.（）被称为中国“芯片之父”。
1、A:邓中翰B:许居衍C:沈绪榜D:吴德馨答案:A第二章测试1.硅在地壳中的储量为（）。
A:第四B:第二C:第三D:第一答案:B2.脱氧后的沙子主要以（）的形式。
A:碳化硅B:硅C:二氧化硅答案:C3.半导体级硅的纯度（）。
A:99.99999％B:99.999999％C:99.999％D:99.9999999％答案:D4.西门子工艺制备得到的硅为单晶硅。
（）A:对B:错答案:B5.一片硅片只有一个定位边。
（）A:错B:对答案:A6.晶面指数（m1 m2 m3）： m1 、m2 、m3分别为晶面在X、Y、Z轴上截距的倒数。
（）A:错B:对答案:B第三章测试1.通过薄膜淀积方法生长薄膜不消耗衬底的材料。
（）A:对B:错答案:A2.热氧化法在硅衬底上制备二氧化硅需要消耗硅衬底。
（）A:错B:对答案:B3.二氧化硅可以与氢氟酸发生反应。
（）A:错B:对答案:B4.薄膜的密度越大，表明致密性越低。
（）A:对B:错答案:B5.电阻率，表征导电能力的参数，同一种物质的电阻率在任何情况下都是不变的。
（）A:错B:对答案:A第四章测试1.光刻本质上是光刻胶的光化学反应。
（）A:错B:对答案:B2.一个透镜的数值孔径越大就能把更少的衍射光会聚到一点。
（）A:错B:对答案:A3.使用正胶进行光刻时，晶片上所得到的图形与掩膜版图形相同。
（）A:错B:对答案:B4.使用负胶进行光刻时，晶片上得到的图形与掩膜版上的图形相反。
（）A:对B:错答案:A5.正性光刻胶经过曝光后，可以溶解于显影液。
半导体制造技术
Semiconductor Manufacturing Technology半导体制造技术Instructor’s ManualMichael QuirkJulian SerdaCopyright Prentice HallTable of Contents目录OverviewI. Chapter1. Semiconductor industry overview2. Semiconductor materials3. Device technologies—IC families4. Silicon and wafer preparation5. Chemicals in the industry6. Contamination control7. Process metrology8. Process gas controls9. IC fabrication overview10. Oxidation11. Deposition12. Metallization13. Photoresist14. Exposure15. Develop16. Etch17. Ion implant18. Polish19. Test20. Assembly and packagingII. Answers to End-of-Chapter Review QuestionsIII. Test Bank (supplied on diskette)IV. Chapter illustrations, tables, bulleted lists and major topics (supplied on CD-ROM)Notes to Instructors:1)The chapter overview provides a concise summary of the main topics in each chapter.2)The correct answer for each test bank question is highlighted in bold. Test bankquestions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.2Chapter 1Introduction to the Semiconductor Industry Die:管芯 defective:有缺陷的Development of an Industry•The roots of the electronic industry are based on the vacuum tube and early use of silicon for signal transmission prior to World War II. The first electronic computer, the ENIAC, wasdeveloped at the University of Pennsylvania during World War II.•William Shockley, John Bardeen and Walter Brattain invented the solid-state transistor at Bell Telephone Laboratories on December 16, 1947. The semiconductor industry grew rapidly in the 1950s to commercialize the new transistor technology, with many early pioneers working inSilicon Valley in Northern California.Circuit Integration•The first integrated circuit, or IC, was independently co-invented by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor in 1959. An IC integrates multiple electronic components on one substrate of silicon.•Circuit integration eras are: small scale integration (SSI) with 2 - 50 components, medium scale integration (MSI) with 50 – 5k components, large scale integration (LSI) with 5k to 100kcomponents, very large scale integration (VLSI) with 100k to 1M components, and ultra large scale integration (ULSI) with > 1M components.1IC Fabrication•Chips (or die) are fabricated on a thin slice of silicon, known as a wafer (or substrate). Wafers are fabricated in a facility known as a wafer fab, or simply fab.•The five stages of IC fabrication are:Wafer preparation: silicon is purified and prepared into wafers.Wafer fabrication: microchips are fabricated in a wafer fab by either a merchant chip supplier, captive chip producer, fabless company or foundry.Wafer test: Each individual die is probed and electrically tested to sort for good or bad chips.Assembly and packaging: Each individual die is assembled into its electronic package.Final test: Each packaged IC undergoes final electrical test.•Key semiconductor trends are:Increase in chip performance through reduced critical dimensions (CD), more components per chip (Moore’s law, which predicts the doubling of components every 18-24 months) andreduced power consumption.Increase in chip reliability during usage.Reduction in chip price, with an estimated price reduction of 100 million times for the 50 years prior to 1996.The Electronic Era•The 1950s saw the development of many different types of transistor technology, and lead to the development of the silicon age.•The 1960s were an era of process development to begin the integration of ICs, with many new chip-manufacturing companies.•The 1970s were the era of medium-scale integration and saw increased competition in the industry, the development of the microprocessor and the development of equipment technology. •The 1980s introduced automation into the wafer fab and improvements in manufacturing efficiency and product quality.•The 1990s were the ULSI integration era with the volume production of a wide range of ICs with sub-micron geometries.Career paths•There are a wide range of career paths in semiconductor manufacturing, including technician, engineer and management.2Chapter 2 Characteristics of Semiconductor MaterialsAtomic Structure•The atomic model has three types of particles: neutral neutrons（不带电的中子）, positively charged protons（带正电的质子）in the nucleus and negatively charged electrons（带负电的核外电子） that orbit the nucleus. Outermost electrons are in the valence shell, and influence the chemical and physical properties of the atom. Ions form when an atom gains or loses one or more electrons.The Periodic Table•The periodic table lists all known elements. The group number of the periodic table represents the number of valence shell electrons of the element. We are primarily concerned with group numbers IA through VIIIA.•Ionic bonds are formed when valence shell electrons are transferred from the atoms of one element to another. Unstable atoms (e.g., group VIIIA atoms because they lack one electron) easily form ionic bonds.•Covalent bonds have atoms of different elements that share valence shell electrons.3Classifying Materials•There are three difference classes of materials:ConductorsInsulatorsSemiconductors•Conductor materials have low resistance to current flow, such as copper. Insulators have high resistance to current flow. Capacitance is the storage of electrical charge on two conductive plates separated by a dielectric material. The quality of the insulation material between the plates is the dielectric constant. Semiconductor materials can function as either a conductor or insulator.Silicon•Silicon is an elemental semiconductor material because of four valence shell electrons. It occurs in nature as silica and is refined and purified to make wafers.•Pure silicon is intrinsic silicon. The silicon atoms bond together in covalent bonds, which defines many of silicon’s properties. Silicon atoms bond together in set, repeatable patterns, referred to asa crystal.•Germanium was the first semiconductor material used to make chips, but it was soon replaced by silicon. The reasons for this change are:Abundance of siliconHigher melting temperature for wider processing rangeWide temperature range during semiconductor usageNatural growth of silicon dioxide•Silicon dioxide (SiO2) is a high quality, stable electrical insulator material that also serves as a good chemical barrier to protect silicon from external contaminants. The ability to grow stable, thin SiO2 is fundamental to the fabrication of Metal-Oxide-Semiconductor (MOS) devices. •Doping increases silicon conductivity by adding small amounts of other elements. Common dopant elements are from trivalent, p-type Group IIIA (boron) and pentavalent, n-type Group VA (phosphorus, arsenic and antimony).•It is the junction between the n-type and p-type doped regions (referred to as a pn junction) that permit silicon to function as a semiconductor.4Alternative Semiconductor Materials•The alternative semiconductor materials are primarily the compound semiconductors. They are formed from Group IIIA and Group VA (referred to as III-V compounds). An example is gallium arsenide (GaAs).•Some alternative semiconductors come from Group IIA and VIA, referred to as II-VI compounds. •GaAs is the most common III-V compound semiconductor material. GaAs ICs have greater electron mobility, and therefore are faster than ICs made with silicon. GaAs ICs also have higher radiation hardness than silicon, which is better for space and military applications. The primary disadvantage of GaAs is the lack of a natural oxide.5Chapter 3Device TechnologiesCircuit Types•There are two basic types of circuits: analog and digital. Analog circuits have electrical data that varies continuously over a range of voltage, current and power values. Digital circuits have operating signals that vary about two distinct voltage levels – a high and a low.Passive Component Structures•Passive components such as resistors and capacitors conduct electrical current regardless of how the component is connected. IC resistors are a passive component. They can have unwanted resistance known as parasitic resistance. IC capacitor structures can also have unintentional capacitanceActive Component Structures•Active components, such as diodes and transistors can be used to control the direction of current flow. PN junction diodes are formed when there is a region of n-type semiconductor adjacent to a region of p-type semiconductor. A difference in charge at the pn junction creates a depletion region that results in a barrier voltage that must be overcome before a diode can be operated. A bias voltage can be configured to have a reverse bias, with little or no conduction through the diode, or with a forward bias, which permits current flow.•The bipolar junction transistor (BJT) has three electrodes and two pn junctions. A BJT is configured as an npn or pnp transistor and biased for conduction mode. It is a current-amplifying device.6• A schottky diode is formed when metal is brought in contact with a lightly doped n-type semiconductor material. This diode is used in faster and more power efficient BJT circuits.•The field-effect transistor (FET), a voltage-amplifying device, is more compact and power efficient than BJT devices. A thin gate oxide located between the other two electrodes of the transistor insulates the gate on the MOSFET. There are two categories of MOSFETs, nMOS (n-channel) and pMOS (p-channel), each which is defined by its majority current carriers. There is a biasing scheme for operating each type of MOSFET in conduction mode.•For many years, nMOS transistors have been the choice of most IC manufacturers. CMOS, with both nMOS and pMOS transistors in the same IC, has been the most popular device technology since the early 1980s.•BiCMOS technology makes use of the best features of both CMOS and bipolar technology in the same IC device.•Another way to categorize FETs is in terms of enhancement mode and depletion mode. The major different is in the way the channels are doped: enhancement-mode channels are doped opposite in polarity to the source and drain regions, whereas depletion mode channels are doped the same as their respective source and drain regions.Latchup in CMOS Devices•Parasitic transistors can create a latchup condition(???????) in CMOS ICs that causes transistors to unintentionally（无心的） turn on. To control latchup, an epitaxial layer is grown on the wafer surface and an isolation barrier（隔离阻障）is placed between the transistors. An isolation layer can also be buried deep below the transistors.Integrated Circuit Productsz There are a wide range of semiconductor ICs found in electrical and electronic products. This includes the linear IC family, which operates primarily with anal3og circuit applications, and the digital IC family, which includes devices that operate with binary bits of data signals.7Chapter 4Silicon and Wafer Preparation8z Semiconductor-Grade Silicon•The highly refined silicon used for wafer fabrication is termed semiconductor-grade silicon (SGS), and sometimes referred to as electronic-grade silicon. The ultra-high purity of semiconductor-grade silicon is obtained from a multi-step process referred to as the Siemens process.Crystal Structure• A crystal is a solid material with an ordered, 3-dimensional pattern over a long range. This is different from an amorphous material that lacks a repetitive structure.•The unit cell is the most fundamental entity for the long-range order found in crystals. The silicon unit cell is a face-centered cubic diamond structure. Unit cells can be organized in a non-regular arrangement, known as a polycrystal. A monocrystal are neatly arranged unit cells.Crystal Orientation•The orientation of unit cells in a crystal is described by a set of numbers known as Miller indices.The most common crystal planes on a wafer are (100), (110), and (111). Wafers with a (100) crystal plane orientation are most common for MOS devices, whereas (111) is most common for bipolar devices.Monocrystal Silicon Growth•Silicon monocrystal ingots are grown with the Czochralski (CZ) method to achieve the correct crystal orientation and doping. A CZ crystal puller is used to grow the silicon ingots. Chunks of silicon are heated in a crucible in the furnace of the puller, while a perfect silicon crystal seed is used to start the new crystal structure.• A pull process serves to precisely replicate the seed structure. The main parameters during the ingot growth are pull rate and crystal rotation. More homogeneous crystals are achieved with a magnetic field around the silicon melt, known as magnetic CZ.•Dopant material is added to the melt to dope the silicon ingot to the desired electrical resistivity.Impurities are controlled during ingot growth. A float-zone crystal growth method is used toachieve high-purity silicon with lower oxygen content.•Large-diameter ingots are grown today, with a transition underway to produce 300-mm ingot diameters. There are cost benefits for larger diameter wafers, including more die produced on a single wafer.Crystal Defects in Silicon•Crystal defects are interruptions in the repetitive nature of the unit cell. Defect density is the number of defects per square centimeter of wafer surface.•Three general types of crystal defects are: 1) point defects, 2) dislocations, and 3) gross defects.Point defects are vacancies (or voids), interstitial (an atom located in a void) and Frenkel defects, where an atom leaves its lattice site and positions itself in a void. A form of dislocation is astacking fault, which is due to layer stacking errors. Oxygen-induced stacking faults are induced following thermal oxidation. Gross defects are related to the crystal structure (often occurring during crystal growth).Wafer Preparation•The cylindrical, single-crystal ingot undergoes a series of process steps to create wafers, including machining operations, chemical operations, surface polishing and quality checks.•The first wafer preparation steps are the shaping operations: end removal, diameter grinding, and wafer flat or notch. Once these are complete, the ingot undergoes wafer slicing, followed by wafer lapping to remove mechanical damage and an edge contour. Wafer etching is done to chemically remove damage and contamination, followed by polishing. The final steps are cleaning, wafer evaluation and packaging.Quality Measures•Wafer suppliers must produce wafers to stringent quality requirements, including: Physical dimensions: actual dimensions of the wafer (e.g., thickness, etc.).Flatness: linear thickness variation across the wafer.Microroughness: peaks and valleys found on the wafer surface.Oxygen content: excessive oxygen can affect mechanical and electrical properties.Crystal defects: must be minimized for optimum wafer quality.Particles: controlled to minimize yield loss during wafer fabrication.Bulk resistivity(电阻系数): uniform resistivity from doping during crystal growth is critical. Epitaxial Layer•An epitaxial layer (or epi layer) is grown on the wafer surface to achieve the same single crystal structure of the wafer with control over doping type of the epi layer. Epitaxy minimizes latch-up problems as device geometries continue to shrink.Chapter 5Chemicals in Semiconductor FabricationEquipment Service Chase Production BayChemical Supply Room Chemical Distribution Center Holding tank Chemical drumsProcess equipmentControl unit Pump Filter Raised and perforated floorElectronic control cablesSupply air ductDual-wall piping for leak confinement PumpFilterChemical control and leak detection Valve boxes for leak containment Exhaust air ductStates of Matter• Matter in the universe exists in 3 basic states (宇宙万物存在着三种基本形态): solid, liquid andgas. A fourth state is plasma.Properties of Materials• Material properties are the physical and chemical characteristics that describe its unique identity.• Different properties for chemicals in semiconductor manufacturing are: temperature, pressure andvacuum, condensation, vapor pressure, sublimation and deposition, density, surface tension, thermal expansion and stress.Temperature is a measure of how hot or cold a substance is relative to another substance. Pressure is the force exerted per unit area. Vacuum is the removal of gas molecules.Condensation is the process of changing a gas into a liquid. Vaporization is changing a liquidinto a gas.Vapor pressure is the pressure exerted by a vapor in a closed container at equilibrium.Sublimation is the process of changing a solid directly into a gas. Deposition is changing a gas into a solid.Density is the mass of a substance divided by its volume.Surface tension of a liquid is the energy required to increase the surface area of contact.Thermal expansion is the increase in an object’s dimension due to heating.Stress occurs when an object is exposed to a force.Process Chemicals•Semiconductor manufacturing requires extensive chemicals.• A chemical solution is a chemical mixture. The solvent is the component of the solution present in larger amount. The dissolved substances are the solutes.•Acids are solutions that contain hydrogen and dissociate in water to yield hydronium ions. A base is a substance that contains the OH chemical group and dissociates in water to yield the hydroxide ion, OH-.•The pH scale is used to assess the strength of a solution as an acid or base. The pH scale varies from 0 to 14, with 7 being the neutral point. Acids have pH below 7 and bases have pH values above 7.• A solvent is a substance capable of dissolving another substance to form a solution.• A bulk chemical distribution (BCD) system is often used to deliver liquid chemicals to the process tools. Some chemicals are not suitable for BCD and instead use point-of-use (POU) delivery, which means they are stored and used at the process station.•Gases are generally categorized as bulk gases or specialty gases. Bulk gases are the relatively simple gases to manufacture and are traditionally oxygen, nitrogen, hydrogen, helium and argon.The specialty gases, or process gases, are other important gases used in a wafer fab, and usually supplied in low volume.•Specialty gases are usually transported to the fab in metal cylinders.•The local gas distribution system requires a gas purge to flush out undesirable residual gas. Gas delivery systems have special piping and connections systems. A gas stick controls the incoming gas at the process tool.•Specialty gases may be classified as hydrides, fluorinated compounds or acid gases.Chapter 6Contamination Control in Wafer FabsIntroduction•Modern semiconductor manufacturing is performed in a cleanroom, isolated from the outside environment and contaminants.Types of contamination•Cleanroom contamination has five categories: particles, metallic impurities, organic contamination, native oxides and electrostatic discharge. Killer defects are those causes of failure where the chip fails during electrical test.Particles: objects that adhere to a wafer surface and cause yield loss. A particle is a killer defect if it is greater than one-half the minimum device feature size.Metallic impurities: the alkali metals found in common chemicals. Metallic ions are highly mobile and referred to as mobile ionic contaminants (MICs).Organic contamination: contains carbon, such as lubricants and bacteria.Native oxides: thin layer of oxide growth on the wafer surface due to exposure to air.Electrostatic discharge (ESD): uncontrolled transfer of static charge that can damage the microchip.Sources and Control of Contamination•The sources of contamination in a wafer fab are: air, humans, facility, water, process chemicals, process gases and production equipment.Air: class number designates the air quality inside a cleanroom by defining the particle size and density.Humans: a human is a particle generator. Humans wear a cleanroom garment and follow cleanroom protocol to minimize contamination.Facility: the layout is generally done as a ballroom (open space) or bay and chase design.Laminar airflow with air filtering is used to minimize particles. Electrostatic discharge iscontrolled by static-dissipative materials, grounding and air ionization.Ultrapure deiniozed (DI) water: Unacceptable contaminants are removed from DI water through filtration to maintain a resistivity of 18 megohm-cm. The zeta potential represents a charge on fine particles in water, which are trapped by a special filter. UV lamps are used for bacterial sterilization.Process chemicals: filtered to be free of contamination, either by particle filtration, microfiltration (membrane filter), ultrafiltration and reverse osmosis (or hyperfiltration).Process gases: filtered to achieve ultraclean gas.Production equipment: a significant source of particles in a fab.Workstation design: a common layout is bulkhead equipment, where the major equipment is located behind the production bay in the service chase. Wafer handling is done with robotic wafer handlers. A minienvironment is a localized environment where wafers are transferred on a pod and isolated from contamination.Wafer Wet Cleaning•The predominant wafer surface cleaning process is with wet chemistry. The industry standard wet-clean process is the RCA clean, consisting of standard clean 1 (SC-1) and standard clean 2 (SC-2).•SC-1 is a mixture of ammonium hydroxide, hydrogen peroxide and DI water and capable of removing particles and organic materials. For particles, removal is primarily through oxidation of the particle or electric repulsion.•SC-2 is a mixture of hydrochloric acid, hydrogen peroxide and DI water and used to remove metals from the wafer surface.•RCA clean has been modified with diluted cleaning chemistries. The piranha cleaning mixture combines sulfuric acid and hydrogen peroxide to remove organic and metallic impurities. Many cleaning steps include an HF last step to remove native oxide.•Megasonics(兆声清洗) is widely used for wet cleaning. It has ultrasonic energy with frequencies near 1 MHz. Spray cleaning will spray wet-cleaning chemicals onto the wafer. Scrubbing is an effective method for removing particles from the wafer surface.•Wafer rinse is done with overflow rinse, dump rinse and spray rinse. Wafer drying is done with spin dryer or IPA(异丙醇) vapor dry (isopropyl alcohol).•Some alternatives to RCA clean are dry cleaning, such as with plasma-based cleaning, ozone and cryogenic aerosol cleaning.Chapter 7Metrology and Defect InspectionIC Metrology•In a wafer fab, metrology refers to the techniques and procedures for determining physical and electrical properties of the wafer.•In-process data has traditionally been collected on monitor wafers. Measurement equipment is either stand-alone or integrated.•Yield is the percent of good parts produced out of the total group of parts started. It is an indicator of the health of the fabrication process.Quality Measures•Semiconductor quality measures define the requirements for specific aspects of wafer fabrication to ensure acceptable device performance.•Film thickness is generally divided into the measurement of opaque film or transparent film. Sheet resistance measured with a four-point probe is a common method of measuring opaque films (e.g., metal film). A contour map shows sheet resistance deviations across the wafer surface.•Ellipsometry is a nondestructive, noncontact measurement technique for transparent films. It works based on linearly polarized light that reflects off the sample and is elliptically polarized.•Reflectometry is used to measure a film thickness based on how light reflects off the top and bottom surface of the film layer. X-ray and photoacoustic technology are also used to measure film thickness.•Film stress is measured by analyzing changes in the radius of curvature of the wafer. Variations in the refractive index are used to highlight contamination in the film.•Dopant concentration is traditionally measured with a four-point probe. The latest technology is the thermal-wave system, which measures the lattice damage in the implanted wafer after ion implantation. Another method for measuring dopant concentration is spreading resistance probe. •Brightfield detection is the traditional light source for microscope equipment. An optical microscope uses light reflection to detect surface defects. Darkfield detection examines light scattered off defects on the wafer surface. Light scattering uses darkfield detection to detectsurface particles by illuminating the surface with laser light and then using optical imaging.•Critical dimensions (CDs) are measured to achieve precise control over feature size dimensions.The scanning electron microscope is often used to measure CDs.•Conformal step coverage is measured with a surface profiler that has a stylus tip.•Overlay registration measures the ability to accurately print photoresist patterns over a previously etched pattern.•Capacitance-voltage (C-V) test is used to verify acceptable charge conditions and cleanliness at the gate structure in a MOS device.Analytical Equipment•The secondary-ion mass spectrometry (SIMS) is a method of eroding a wafer surface with accelerated ions in a magnetic field to analyze the surface material composition.•The atomic force microscope (AFM) is a surface profiler that scans a small, counterbalanced tip probe over the wafer to create a 3-D surface map.•Auger electron spectroscopy (AES) measures composition on the wafer surface by measuring the energy of the auger electrons. It identifies elements to a depth of about 2 nm. Another instrument used to identify surface chemical species is X-ray photoelectron spectroscopy (XPS).•Transmission electron microscopy (TEM) uses a beam of electrons that is transmitted through a thin slice of the wafer. It is capable of quantifying very small features on a wafer, such as silicon crystal point defects.•Energy-dispersive spectrometer (EDX) is a widely used X-ray detection method for identifying elements. It is often used in conjunction with the SEM.• A focused ion beam (FIB) system is a destructive technique that focuses a beam of ions on the wafer to carve a thin cross section from any wafer area. This permits analysis of the wafermaterial.Chapter 8Gas Control in Process ChambersEtch process chambers••The process chamber is a controlled vacuum environment where intended chemical reactions take place under controlled conditions. Process chambers are often configured as a cluster tool. Vacuum•Vacuum ranges are low (rough) vacuum, medium vacuum, high vacuum and ultrahigh vacuum (UHV). When pressure is lowered in a vacuum, the mean free path(平均自由行程) increases, which is important for how gases flow through the system and for creating a plasma.Vacuum Pumps•Roughing pumps are used to achieve a low to medium vacuum and to exhaust a high vacuum pump. High vacuum pumps achieve a high to ultrahigh vacuum.•Roughing pumps are dry mechanical pumps or a blower pump (also referred to as a booster). Two common high vacuum pumps are a turbomolecular (turbo) pump and cryopump. The turbo pump is a reliable, clean pump that works on the principle of mechanical compression. The cryopump isa capture pump that removes gases from the process chamber by freezing them.。
半导体制造技术
半导体制造技术
半导体制造技术是指以半导体材料为基础，利用先进的设备、工艺和测试技术，在晶圆上制作各种尺寸、形状和功能的集成电路（IC）元件。
半导体制造技术包括晶圆生产、片上集成、封装、测试等一系列步骤。
晶圆生产技术是半导体制造的核心步骤，其目的是在晶圆表面形成一层导电层，用于在其表面制作微纳米尺寸的元件及连接线路。
常用的晶圆生产技术有光刻、电镀、气相沉积、激光刻蚀、无损整形、金属化学气相沉积等。
片上集成技术是将器件与线路集成在一个晶片上，实现信号传输及功能实现。
目前，在片上集成中使用的技术主要有光刻、激光刻蚀和激光加工等。
封装技术是指将晶片封装到一个容器中，以便将其与外部电路和环境完全隔离，并保护其内部结构。
一般来说，封装技术可以分为焊接、固化、涂覆、压合和滴胶等。
测试技术是检查半导体元件及集成电路性能的手段，如功耗测试、性能测试、动态测试、稳态测试等。
第六讲：光刻工艺(半导体制造技术)
❖ 工艺宽容度
整个光刻过程步骤之多，而且每一步骤都 会影响最终的图形尺寸， 另外每一工艺步骤都 有它的内部变异。不同的光刻胶对工艺变异的 容忍性都不一样。那么，容忍性越高，在晶圆 表面达到所需要尺寸的可能性就越大，或者说 工艺的宽容度就越大。
❖ 针孔
所谓针孔是指光刻胶层中尺寸非常小的空 穴。可以是涂胶工艺中由环境中的微粒污染物 造成的，也可以由光刻胶层结构上的空穴造成。 针孔是有害的，因为它可以允许刻蚀剂渗过光 刻胶层进而在晶圆表面层刻蚀除小孔。
光源则来自电磁 接近式 光谱的其他成分。
投影式
X 射线 电子束
步进式
曝光光源
普通光源光的波长范围大，图形边缘衍射现象 严重，满足不了特征尺寸的要求。所以作为晶圆生产 用的曝光光源必须是某一单一波长的光源；另外光源 还必须通过反射镜和透镜，使光源发出的光转化成一 束平行光，这样才能保证特征尺寸的要求。
时间和温度是软烘焙的参数，不完全的烘焙在 曝光过程中造成图像形成不完整和在刻蚀过程 中造成多余的光刻胶漂移；过分烘焙会造成光 刻胶中的聚合物产生聚合反应，并且不与曝光
射线反应。
负胶必须在氮气中进行烘焙，而正胶可以 在空气中烘焙。
下表总结了不同的烘焙方式
方法
烘焙时间（分钟） 温度控制 生产率
速度
光刻胶
正性
负性 PMMA PMIPK PBS TFECA COP (PCA)
聚合物
酚醛树脂（间 甲酚甲醛） 聚异戊二烯 聚甲基丙烯酸酯
聚甲基异丙烯基酮
聚丁烯 1 砜
聚三氟乙烷基氯丙烯 酸酯 共聚物（ a 氰乙基丙烯酸， a 氨基乙烷基丙烯酸酯）
极性
感光性
曝光光源
(Coul/cm )
+
半导体sgt工艺(一)
半导体sgt工艺(一)半导体sgt工艺介绍•半导体sgt工艺是一种重要的制程技术，用于制造先进的半导体器件。
•SGT是Selective Growth Transistor的缩写，选择性生长晶体管。
•它通过控制晶体管的生长方向和材料特性，使得器件性能更优秀。
工艺流程1.接收基片–首先，选择合适的半导体基片作为起始材料。
–基片的选择要符合所需器件的特定要求。
2.清洗准备–对基片进行严格的清洗准备，以去除表面的杂质和污染物。
–清洗过程中使用特定的溶液和工艺参数，确保表面的纯净度和平整度。
3.预先处理–对基片进行一系列的预处理步骤，以增强材料的表面活性和吸附能力。
–预处理通常包括化学气相沉积（CVD）或物理气相沉积（PVD）等工艺。
4.蚀刻处理–利用化学蚀刻或物理蚀刻的方式，对基片进行局部削减和形状调整。
–蚀刻处理会在基片表面形成必要的结构和凹陷，以便后续的生长步骤。
5.晶体管生长–在设计好的区域上进行晶体管的选择性生长。
–借助CVD或其他生长工艺，沉积特定材料在预定位置上，形成晶体管结构。
6.后续处理–对晶体管进行后续的清洗和退火处理，提高材料的结晶质量和界面特性。
–还可能包括沉积其他材料层、刻蚀、光刻等工艺，以完成整个器件的制造。
应用领域•SGT工艺广泛应用于高性能和先进的半导体器件制造，特别是：–高频器件：如射频放大器、微波器件等。
–低功耗CMOS器件：如功耗控制电路、片上系统等。
–光电器件：如光电二极管、光电传感器等。
优势和挑战•优势：–半导体sgt工艺能够提高器件性能，如频率响应、开关速度、功耗等。
–可实现精确的材料控制和器件结构设计。
–适应性强，可以应用于不同材料和器件类型。
•挑战：–工艺复杂，需要精确的控制和长时间的优化。
–成本较高，对设备和材料的投入要求较高。
–需要与其他工艺相结合，以实现完整的器件制造。
结论•半导体sgt工艺作为一种先进的制程技术，在半导体器件制造领域发挥着重要作用。
半导体工艺《半导体制造技术》答案
光刻 NMOS 管源漏区→NMOS 管源漏区磷注入
光刻 PMOS 管源漏区→PMOS 管源漏区硼注入
BPSG 沉积回流/增密
电子科技大学微电子与固体电子学院
2013 年 5 月 8 日
光刻接触孔BPSG 刻蚀
溅射 Si-Al-Cu→光刻金属互连刻蚀 Si-Al-Cu
该截面实际无压焊窗口，此图仅为示意，压焊窗口版图为一些亮区方块 SiO2 和 SiN 钝化层沉积→光刻压焊窗口→SiO2 和 SiN 刻蚀合金化退火 4. 什么是浅槽隔离 STI？（即简要描述浅槽隔离 STI） ，它取代了什么工艺？ 浅槽隔离是在衬底上通过刻蚀槽、 氧化物填充及氧化物平坦化等步骤， 制作晶体管有源区之 间的隔离区的一种工艺。它取代了 LOCOS 隔离工艺。
N MAX 0.4 0.4 5 1015 cm2 9.7 1020 cm3 RP 207 A
exp t kT
x j RP RP 2 ln N MAX N B 582 A 207 A 2 ln 9.7 1020 cm 3 1016 cm 3 1574 A
电子科技大学微电子与固体电子学院
2013 年 5 月 8 日
步骤：等离子体形成、高能氩离子轰击金属靶材、金属原子溅射、金属原子输运、金属原子 沉积、尾气排出。 优点：台阶覆盖能力相对好、能沉积合金材料、能进行原位溅射刻蚀（反溅） 2. 列出集成电路金属互连对金属的 7 种要求。 电阻率低、电流密度高；粘附性好、接触电阻低；易于沉积、间隙填充好（大马士革） ；易 于刻蚀、易于平坦化（大马士革） ；抗温循性能好（延展性好） ；抗腐蚀性能好；抗应力性能 好。 3. 现代集成电路用铜互连取代铝互连的原因是什么？简要描述大马士革工艺的流程。 原因：铜电导率更低可以降低 RC 延迟；铜抗电迁移能力更好。 大马士革工艺流程：层间介质沉积和图形化、金属填隙、金属平坦化 CMP。 4. 列出硅化物的 3 个作用。 降低器件寄生电阻；降低接触电阻；作为金属与硅之间的粘合剂。 第五章作业 1. 请写出光刻的 8 个基本步骤 气相成底模、涂胶、软烘、对准和曝光、曝光后烘焙、显影、坚膜、显影后检查。 2. 请列出软烘的至少 2 个作用 去除溶剂从而： 改善胶的粘附性、 优化胶的光吸收特性和显影能力、 缓解涂胶时产生的应力、 防止曝光时挥发污染设备。 3. 已知接触孔版图图形为一些小方块，如果使用正胶，掩膜版应该是暗版还是亮版？ 暗版。 接触孔处待刻蚀层材料应该去除， 因此不应被光刻胶覆盖， 因此该处光刻胶应曝光 （正胶） ， 因此版图图形为透光部分，而其他部分为不透光部分，故为暗版。 4. 已知某台分步重复光刻机的紫外光源波长为 248nm、光学系统的数值孔径为 0.7、工艺 因子为 0.7，试计算该设备光刻的分辨率和焦深。 分辨率：R=kλ/NA=0.7*248nm/0.7=248nm 焦深：DOF=λ/2(NA)2=248nm/(2×0.72)=253nm 第六章作业 1. 为什么现代集成电路工艺多采用干法刻蚀？ 干法刻蚀各向异性，可以实现图形精确转移。 2. 待刻蚀层厚度为 5000A，待刻蚀层与掩膜层选择比为 5:1，待刻蚀层与刻蚀终止层选择比 为 10:1，过刻蚀时间为 20%，请问需要掩膜层的最小厚度是多少？刻蚀终止层的刻蚀深度 是多少？ 掩膜层厚度：5000A/(5:1)*(1+20%)=1200A 刻蚀终止层的刻蚀深度：5000A/(10:1)*20%=100A 3. 描述反应离子刻蚀的机理。 反应离子刻蚀属于物理和化学混合刻蚀。 ①进入真空反应室的刻蚀气体在射频电场的作用下分解电离形成等离子体， 等离子体由高能 电子、反应正离子、自由基、反应原子或原子团组成。 ②反应室被设计成射频电场垂直于被刻蚀样片表面且射频电源电极 （称为阴极） 的面积小于 接地电极（称为阳极）的面积时，在系统的电源电极上产生一个较大的自偏置电场。 ③等离子体中的反应正离子在自偏置电场中加速得到能量轰击样片表面， 这种离子轰击不仅 对样片表面有一定的溅射作用形成物理刻蚀， 而且提高了表面层自由基和反应原子或原子团 的化学活性，加速与样片的化学反应。 ④由于离子轰击的方向性，遭受离子轰击的底面比未遭受离子轰击的侧面的刻蚀要快得多，
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二.工艺流程 衬底选择 光刻 晶圆处理 构装 测试
1.前段（FrontEnd）制程（典型的PN结隔离的掺 金TTL电路工艺流程）
• 1.衬底选择 10Ω.cm111晶向,偏离2O~5O P型Siρ 晶圆（晶片）晶圆（晶片） 的生产由砂即（二氧化硅）开始，经由电弧炉的提炼还原成冶炼级的硅，再经 由盐酸氯化，产生三氯化硅，经蒸馏纯化后，透过慢速分解过程，制成棒状或 粒状的「多晶硅」。一般晶圆制造厂，将多晶硅融解后，再利用硅晶种慢慢拉 出单晶硅晶棒。一支85公分长，重76.6公斤的8寸硅晶棒，约需2天半时间长成 。经研磨、抛光、切片后，即成半导体之原料晶圆片 第一次光刻—N+埋层扩 散孔 1。减小集电极串联电阻 2。减小寄生PNP管的影响 外延层淀积 1。 VPE（Vaporousphaseepitaxy)气相外延生长硅 SiCl4+H2→Si+HCl 2。氧化 Tepi<Xjc+Xmc+TBL-up+tepi-ox 第二次光刻—P+隔离扩散孔 在衬底上形成孤立 的外延层岛,实现元件的隔离. 第三次光刻—P型基区扩散孔 决定NPN管的基区 扩散位置范围 第四次光刻—N+发射区扩散孔 集电极和N型电阻的接触孔,以及 外延层的反偏孔。 Al—N-Si欧姆接触：ND≥1019cm-3， 第五次光刻—引线接触 孔 第六次光刻—金属化内连线：反刻铝
2.晶圆处理
• 一、晶圆处理制程
• 晶圆处理制程之主要工作为在矽晶圆上制作电路与电子元件（如电晶体、电容体、逻辑闸等） ，为上述各制程中所需技术最复杂且资金投入最多的过程，以微处理器（Microprocessor）为例 ，其所需处理步骤可达数百道，而其所需加工机台先进且昂贵，动辄数千万一台，其所需制造 环境为为一温度、湿度与含尘（Particle）均需控制的无尘室（Clean-Room），虽然详细的处理 程序是随著产品种类与所使用的技术有关；不过其基本处理步骤通常是晶圆先经过适当的清洗 （Cleaning）之後，接著进行氧化（Oxidation）及沈积，最後进行微影、蚀刻及离子植入等反覆 步骤，以完成晶圆上电路的加工与制作。
4.测试(1)
• 测试制程（InitialTestandFinalTest） 1晶片切割（DieSaw） 2黏晶（ DieBond） 黏晶之目的乃將一顆顆之晶粒置於導線架上並以銀膠（ epoxy）黏著固定。黏晶完成後之導線架則經由傳輸設備送至彈匣（ magazine）內，以送至下一製程進行銲線。 3銲線（WireBond） IC構裝製程（Packaging）則是利用塑膠或陶瓷包裝晶粒與配線以成 積體電路（IntegratedCircuit；簡稱IC），此製程的目的是為了製造出 所生產的電路的保護層，避免電路受到機械性刮傷或是高溫破壞。 最後整個積體電路的周圍會向外拉出腳架（Pin），稱之為打線，作 為與外界電路板連接之用。 4封膠（Mold） 封膠之主要目的為防 止濕氣由外部侵入、以機械方式支持導線、內部產生熱量之去除及 提供能夠手持之形體。其過程為將導線架置於框架上並預熱，再將 框架置於壓模機上的構裝模上，再以樹脂充填並待硬化。
• 後段（BackEnd）---后工序
3.构装
• 三、IC构装制程 • IC構裝製程（Packaging）：利用塑膠或陶瓷包裝晶粒與配線以成積
體電路 目的：是為了製造出所生產的電路的保護層，避免電路受到 機械性刮傷或是高溫破壞。 • 构装（Packaging）：IC構裝依使用材料可分為陶瓷（ceramic）及塑 膠（plastic）兩種，而目前商業應用上則以塑膠構裝為主。以塑膠構 裝中打線接合為例，其步驟依序為晶片切割（diesaw）、黏晶（ diemount/diebond）、銲線（wirebond）、封膠（mold）、剪切/成 形（trim/form）、印字（mark）、電鍍（plating）及檢驗（ inspection）等。
• 二、晶圆针测制程
• 经过WaferFab之制程後，晶圆上即形成一格格的小格，我们称之为晶方或是晶粒（Die），在 一般情形下，同一片晶圆上皆制作相同的晶片，但是也有可能在同一片晶圆上制作不同规格的 产品；这些晶圆必须通过晶片允收测试，晶粒将会一一经过针测（Probe）仪器以测试其电气特 性，而不合格的的晶粒将会被标上记号（InkDot），此程序即称之为晶圆针测制程（ WaferProbe）。然後晶圆将依晶粒为单位分割成一粒粒独立的晶粒
测试（2）
• 5剪切/成形（Trim/Form） 剪切之目的為將導線架上構裝完成之晶 粒獨立分開，並把不需要的連接用材料及部份凸出之樹脂切除（ dejunk）。成形之目的則是將外引腳壓成各種預先設計好之形狀， 以便於裝置於電路版上使用。剪切與成形主要由一部衝壓機配上多 套不同製程之模具，加上進料及出料機構所組成。 6印字（Mark） 印字乃將字體印於構裝完的膠體之上，其目的在於註明商品之規格 及製造者等資訊。 7檢驗（Inspection） 晶片切割之目的為將前製 程加工完成之晶圓上一顆顆之檢驗之目的為確定構裝完成之產品是 否合於使用。其中項目包括諸如：外引腳之平整性、共面度、腳距 、印字是否清晰及膠體是否有損傷等的外觀檢驗。 8封装 制程处 理的最后一道手续，通常还包含了打线的过程。以金线连接芯片与 导线架的线路，再封装绝缘的塑料或陶瓷外壳，并测试集成电路功 能是否正常。
半导体制造技术
一.概述 二.半导体生产工艺流程 三.成果与应用
2020/4/6
一.概述
详细追述了半导体发展的历史并吸收了当今最新技术资料，全书共分20章，根据应用于半导体制 造的主要技术分类来安排章节，包括与半导体制造相关的基础技术信息；总体流程图的工艺模型概 况，用流程图将硅片制造的主要领域连接起来；具体讲解每一个主要工艺；集成电路装配和封装的 后部工艺概况。此外，各章为读者提供了关于质量测量和故障排除的问题，这些都是会在硅片制造 中遇到的实际问题。