Marvell_千兆以太网PHY芯片_88E1340S
KSZ8852HLE 10 100 Ethernet PHY 评估板用户指南说明书
KSZ8852HLE Evaluation Board User Guide Revision 1.0 / August 20, 2014Table of ContentsIntroduction (3)1Board Features (3)2KSZ8852HLE-EVAL Evaluation Board Kit (3)3Hardware Description (3)3.1Device Configuration (5)3.1.1Strap-in Configuration (5)3.1.2EEPROM Configuration (5)3.2Power Supplies (5)3.3Port 3 Parallel Host Interface (6)3.4GPIO pins (7)3.510/100 Ethernet PHY Ports (8)3.6100BASE-FX Fiber Port Option (9)3.7LED Indicators (9)3.8List of Jumpers and Connectors (9)3.9Board Layout (11)4Using the KSZ8852HLE Evaluation Board (11)5Reference Documents (12)6Revision History (12)List of FiguresFigure 1 KSZ8852HLE Evaluation Board (4)Figure 2 Power Supply Section and Related Jumper Locations (6)Figure 3 GPIO Connectors and Strap-in Jumper Locations (8)Figure 4 Topside Layout of the Board (11)List of TablesTable 1 Strap-In Configuration Jumpers (5)Table 2 Power Supply Related Jumpers (6)Table 3 Signal Descriptions on the Parallel (Host-Port) Connector J16 (7)Table 4 GPIO Pin Selection for KSZ8852HLE (8)Table 5 LED Functions (9)Table 6 List of Jumpers and Connectors (10)IntroductionThe KSZ8852HLE Evaluation Board provides a platform in which to test or explore the functionally of the KSZ8852HLE Ethernet switch.The KSZ8852HLE is an integrated 3-port 10BASE-T / 100BASE-TX/FX managed Ethernet switch with two 10/100 PHY ports, and generic parallel interface connectivity to a host processor on port 3. The KSZ8852HLE includes all the functions of a 10/100BASE-T/TX/FX switch system that combines switch engine, frame buffers management, addresses look-up table, queue management, MIB counters, media access controllers (MAC) and PHY transceiver interfaces. It is fully compliant with the IEEE 802.3 standards (10BASE-T and 100BASE-TX).This KSZ8852HLE Evaluation Board User Guide provides the information necessary to configure and set up the board to evaluate or test the KSZ8852HLE device in different environments.1 Board FeaturesThe KSZ8852HLE Evaluation Board encompasses the following features.•Micrel’s KSZ8852HLE Integrated 3-Port 10/100 Managed Ethernet Switch•Two Ethernet LAN Interfaces with RJ-45 jacks and isolation magnetics (Ports 1 & 2)•Auto MDI/MDI-X for automatic detection and correction for straight-through and crossover cables •Generic 8/16 bit parallel Host processor interface (Port 3)•Provisioning for line side and chip side over-voltage protection (optional)•On-board 3.3V and 1.8V/2.5V regulators•Configurable for VDDIO of 3.3V, 2.5V, or 1.8V operation•Serial interface for EEPROM•LED indicators for link status and activity of the RJ-45 ports•25 MHz crystal•Jumpers for power up configuration of the device•Jumpers for GPIO pins and I/O voltage selection•Board operates from a single 5V DC supply•Reset switch•Various test points2 KSZ8852HLE-EVAL Evaluation Board KitThe KSZ8852HLE-EVAL kit includes the following:•KSZ8852HLE Evaluation Board•KSZ8852HLE Evaluation Board User’s Guide (This document, available in the eval kit documention at the Micrel website)•KSZ8852HLE Evaluation Board Schematic (Available in the eval kit documentation at the Micrel website)3 Hardware DescriptionThe KSZ8852HLE Evaluation board is a small form-factor board (5.2” x 4.75”) that can be configured by a host processor connected through the 16-bit generic parallel host interface. In addition to passing full-rateEthernet traffic, the external host processor can read and write the entire register set within the KSZ8852HLE device through this interface.The board supports different types of host processors. Therefore a strap-in configuration mode is provided to set the parallel interface according to the type of processor used. Strap-in mode configuration occurs at power on time where the voltage level on certain pins is automatically sampled and used to configure various features in the device. This is accomplished with the on board jumper options. Available configuration options are explained in detail in the following sections. Figure 1 is a picture of the KSZ8852HLE Evaluation board.Figure 1 KSZ8852HLE Evaluation Board3.1 Device Configuration3.1.1 Strap-in ConfigurationStrap-in configuration is used for setting up the parallel host interface and to indicate the presence of an EEPROM. This is accomplished by setting available configuration jumpers which are used at device power-up. Simply set the board’s configuration jumpers to the desired settings and apply power to the board. The configuration can be changed while power is applied to the board by changing the jumper settings and pressing the convenient manual reset button for the new settings to take effect. Note that even if no external strap-in jumpers are set, internal pull-up and pull-down resistors will set the KSZ8852HLE to the default configuration.The following table covers each jumper used for the strap-in option and describes its function.JUMPER FUNCTION SETTING DEFAULT JP301 Parallel Bus Width select Pins 1-2 closed: 16-bitPins 2-3 closed: 8-bit16-bitJP302 Parallel Bus Endian-modeselect Pins 1-2 closed: Little EndianPins 2-3 closed: Big EndianLittle EndianJP303 EEPROM select Pins 1-2 closed: EEPROM presentPins 2-3 closed: EEPROM not presentEEPROM not presentTable 1 Strap-In Configuration Jumpers3.1.2 EEPROM ConfigurationThe KSZ8852HLE Evaluation Board has a serial EEPROM to enable loading the MAC address into the device at power-up time with a pre-programmed value. The strap-in option should be set to enable the EEPROM presence, as indicated on the above table. If enabled, the first seven words of the Serial EEPROM will be read. Registers 0x010 – 0x015 will be loaded with words 0x01 – 0x03 from the EEPROM.In addition, the remainder of EEPROM space (0x07 – 0x3F) can be written or read and used as needed by the host processor.Supported EEPROM: 93C463.2 Power SuppliesThe board requires a single 5V DC supply, which can be provided through a barrel power-supply jack (J11) or through the parallel host port. The current requirement is 200mA.The pin diameter of jack J11 is 2.5mm on early boards, and is 2.1mm on newer boards. 2.5mm plugs are recommended because they are generally compatible with both jack sizes. A 2.1mm plug, however, cannot be used with the 2.5mm jack.JP3 must be in place if the board is powered through the parallel port. There is a 3.3V regulator on the board supplying power for the KSZ8852HLE and other components. A separate on-board voltage regulator is provided for the optional 2.5V and 1.8V supplies for KSZ8852HLE’s I/O interface (VDD_IO).JP404 and JP406 are used for VDD_IO selection. JP403 and JP405 must be in place and other options properly selected before powering up the board.JUMPER FUNCTION SETTINGJP3 Enable +5V supply from host-port connector J16 Closed: enabledOpen: disabled, use external powersupply through J11JP403 +3.3V supply for KSZ8852 analog circuits Must be closedJP405 +1.2V supply for KSZ8852 analog circuits Must be closedJP408 +1.2V supply for KSZ8852 digital circuits Must be closedVDD_IO selection 3.3V 2.5V 1.8VJP404 Pins 2-3closed Pins 1-2closedPins 1-2closedJP406 X open ClosedTable 2 Power Supply Related JumpersFigure 2 Power Supply Section and Related Jumper Locations3.3 Port 3 Parallel Host InterfaceThe board features a 40-pin connector (J16) for interfacing the Bus Interface Unit (BIU) on the KSZ8852HLE to an external host processor. The BIU is a generic parallel host interface providing access to the MAC of Port 3.The 40-pin connector is a standard dual-row straight pin header. To access the internal registers, MIB counters, etc., a host processor board such as the Micrel KSZ9692MII-PTP-EV board has to be connected to the parallel interface. Strap-in configurations determine the mode of host interface operation at power-up.The voltage level on all interface pins (VDD_IO) can be set to 1.8V, 2.5V or 3.3V of operation, enabling a direct connection to different type of host processors.Signal Pin No. Type FunctionSD[15:0] 5-20 I/O Shared Data BusIn 16-bit mode:SD[15:0] -> D[15:0] data access when CMD = “0”.SD[10:2] -> A[10:2] address access and SD[15:12] -> BE[3:0] byte enableaccess when CMD = “1” (SD[1:0] and SD[11] are not used).In 8-bit mode:SD[7:0] -> D[7:0] data access when CMD = “0”.SD[7:0] -> A[7:0] 1st address access and SD[2:0] -> A[10:8] 2nd address accesswhen CMD = “1” (SD[7:3] are not used during 2nd address access).CMD 28 Input Command TypeThis command input determines the SD[15:0] shared data bus access cycleinformation.0: Data access1: Command access for address and byte enableCSN 23 Input Chip Select EnableChip Enable is an active low signal used to enable the shared data bus access. INTRN 31 Output InterruptThis low active signal asserted low when an interrupt is being requested.RDN 36 Input Asynchronous ReadThis low active signal is asserted to low during a read cycle.A 4.7K pull-up resistor is recommended on this signal.WRN 35 Input Asynchronous WriteThis low active signal is asserted low during a write cycle.PME/ EEPROM 27 Output/InputPower Management EventThis output signal indicates that a Wake On LAN event has been detected. TheKSZ8852HLE is requesting the system to wake up from low power mode. Itsassertion polarity is programmable with the default polarity to be active low.EEPROM select Configuration ModeDuring Power-on/Reset time this pin is an input and the strap-in value is readby KSZ8852HLE to determine the presence of an EEPROM. (see descriptionof JP303 in Table 1)RSTN 24 Input ResetThis is the Hardware reset pin. It is active Low. This reset input is required tobe low for a minimum of 10 ms after supply voltages VDD_IO and 3.3V arestable.+5V 1, 3 Power supplyConnection to +5V supply of the Host processor board.GND 2, 4, 21,22, 25,26, 29,33, 34,37-40GroundN.C. 30, 32Table 3 Signal Descriptions on the Parallel (Host-Port) Connector J163.4 GPIO pinsKSZ8852HLE chip has up to 7 General Purpose I/O (GPIO) pins which are available on the evaluationboard at connector J15. Three GPIO pins of the KSZ8852HLE device are shared with EEPROM signals and are user programmable. By default the EEPROM signals are enabled, therefore initially only 4 GPIO pins are available. If more than 4 GPIO pins are required, the user needs to program IOMXSEL register (0x0D6) as follows:IOMXSEL register(0x0D6)Description SettingBit 5 Selection of EESK or GPIO3for Pin 53 1 = This pin is used for EESK (default) 0 = This pin is used for GPIO3Bit 2 Selection of EEDIO or GPIO4for Pin 54 1 = This pin is used for EEDIO (default) 0 = This pin is used for GPIO4Bit 1 Selection of EECS or GPIO5for Pin 55 1 = This pin is used for EECS (default) 0 = This pin is used for GPIO5Table 4 GPIO Pin Selection for KSZ8852HLEGPIO signals are on the odd numbered pins of connector J15. All even numbered pins are GND connections.Figure 3 GPIO Connectors and Strap-in Jumper Locations3.5 10/100 Ethernet PHY PortsThere are two 10/100 Ethernet PHY ports on the KSZ8852HLE evaluation board. The ports can be connected to an Ethernet traffic generator or analyzer via standard RJ-45 connectors using CAT-5 (or better) UTP cables. Both ports support auto MDI/MDI-X, eliminating the need for cross-over cables.Transformers are utilized for proper interfacing to an Ethernet network. In addition, optional over- voltage protection devices D5 thru D12 may be installed to protect the KSZ8852HLE in the event of an over- voltage condition.The FXSD1 and FXSD2 pins should be pulled low by installing jumpers on pins 3 & 4 of J12 and J13.3.6 100BASE-FX Fiber Port OptionThe board supports optional 100BASE-FX fiber modules, but this feature is not available on the KSZ8852HLE. For applications that require fiber on one or both 100 Mbps ports, use the KSZ8462HL. 3.7 LED IndicatorsThe evaluation board provides two LEDs (PxLED1, PxLED0) for each PHY port. The LED indicators are programmable to four different states. LED mode is selected through bits [9:8] of the SGCR7 register (0x00E-0x00F).The LED mode definitions are specified in Table 7. See Figure 2 for the LEDs’ orientation on the KSZ8852HLE evaluation board in the power supply section.SGCR7 Control Register (0x00E-0x00F) Bits[9:8]00 (default) 01 10 11PxLED1 = Speed PxLED1 = Active PxLED1 = Duplex PxLED1 = DuplexPxLED0 = Link/Active PxLED0 = Link PxLED0 = Link/Active PxLED0 = LinkTable 5 LED FunctionsThe KSZ8852HLE evaluation board also has a power LED (D3) for the 3.3V power supply. When D3 is illuminated, the board’s 3.3V power supply is “on”.The activity LED indicators for Port-1 and Port-2 are powered by 3.3V, regardless of the VDD_IO selected for the device.3.8 List of Jumpers and ConnectorsJumper Description SettingJP2 PWRDN Chip Power-down Place Jumper for full chip power-down JP3 Enable +5V supply from host-port connector Closed: enabledOpen: disabledJP10, 11 Power selection for the Fiber module Leave open when no Fiber ModulepresentJP77, 78 FXSD1, FXSD2 Fiber signal detect input forPort 1 and Port 2 (not used)Jumper Description SettingJP301-303 Strapping options See Table 1JP403-408 Power-supply strapping options See Table 2JP409 Enable bi-directional Reset signal Closed: enable Reset signal on bothdirectionsOpen: Local reset signal does not affectthe host processor board.J1, J2 RJ45 connectors for Port-1 and Port-2J11 +5V DC Power JackJ12, J13 FXSD pin connections Pins 1-2 closed: connect to SD signalfrom fiber modulePins 3-4 closed: ground the FXSD pins,for copper modeJ15 GPIO HeaderJ16 Parallel Host-port interface (Port-3)Table 6 List of Jumpers and Connectors3.9 Board LayoutThe layout of the board is shown in Figure 3. The key areas are indicated.Figure 4 Topside Layout of the BoardThe KSZ8852HLE Evaluation board interfaces directly with the KSZ9692PB SOC board (KSZ9692-MII-PTP-EV), providing a complete evaluation platform. In this setup, Port3 of the KSZ8852HLE is connected to the SOC board through its parallel host interface. For more details on this configuration, refer to the KSZ8462HL Evaluation Kit User Guide.4 Using the KSZ8852HLE Evaluation BoardThe Evaluation Board is intended to provide a platform that enables designers to investigate and evaluate the capabilities of the KSZ8852HLE device. It is not intended to be a complete development system to be used for an entire product design effort.5 Reference DocumentsKSZ8852HLE DatasheetKSZ8852HLE Evaluation Board SchematicKSZ8852HLE Evaluation Board Gerber filesIEEE802.3 SpecificationKSZ8462HL Evaluation Kit User Guide6 Revision History© Micrel, Inc. 2014All rights reservedMicrel is a registered trademark of Micrel and its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners.The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury.Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.。
BT4网卡支持列表以及个网卡情况基本信息
BT4网卡支持列表以及个网卡情况基本信息（参照这个选一款称心如意的“避雷针”吧！）By:MPCI接口无线网卡：Asus WL-138g v2驱动：bcm43xx芯片组:Broadcom 使用正常(笔者估计这是一块旧的Broadcom芯片,其实Broadcom芯片总体支持很差) Dlink DWL-AG530 使用正常Dlink DWL-G520芯片组: Atheros 扩展天线: RP-SMA 使用正常Dlink DWL-G510芯片组: Ralink扩展天线: SMA-REV 不能工作。
虽然支持Ralink芯片组.Foxconn WLL-3350驱动: rt2500MSI PC60G驱动: RT61芯片组: Ralink 除了注入等部分功能，其余使用正常Netgear WG311T驱动: Madwifi-ng芯片组: Atheros External Antenna: RP-SMA Connector Works perfectly out of the box. Injection works as Well.Netgear WPN311驱动: Madwifi-ng芯片组: Atheros 扩展天线: RP-SMA 包括注入都能完美工作SMC SMCWPCI-G芯片组: Atheros扩展天线: External SMA (detachable) 包括注入都能完美工作基于Broadcom BCM4306 802.11b/g (rev 3)的无线网卡：Dell 1350 WLAN Mini-PCI 2.6.20-BT-PwnSauce-NOSMP HP Pavilion ZV5330us HP Pavilion zd8000 Compaq Presario 2500 驱动: bcm43xx 只能监控，不能注入(笔者曾经用过，加-x 30和iwconfig rate 1M可以简单注入)基于Broadcom BCM4318 802.11b/g的无线网卡：驱动: bcm43xx 可以监控，使用aircrack-ng0.9可支持简单的注入，键入命令：bt ~ # ifconfig eth0 up bt ~ # iwconfig eth0 mode Monitor channel 然后使用1号和3号攻击模式IBM AR5212 802.11abg NIC (rev 01)驱动: AtherosIPW2100(小提示：IPW就是Intel Pro Wireless:)驱动: IPW2100 只能监控，不能注入IPW2200驱动: IPW2200 (需要注入驱动补丁) 只能监控，不能注入IPW3945驱动: IPW3945 只能监控，不能注入IPW3945(另一版本IPW3945)Driver : IPWRAW, 写一些命令后正常工作WN360G驱动: prism54 Mini PCIe (内置笔记本MiniPCIE接口)：Gigabit Atheros card 正常工作Broadcom BCM4311 802.11b/g驱动: bcm43xx (bcmwl5.sys) 只能监控，不能注入PCMCIA接口无线网卡：3COM 3CRWE154G72 v1驱动: prism54芯片组: Conexant PrismGT FullMAC注意: 有的版本不是此芯片组3COM 3CRPAG175B with XJACKAntenna驱动: Madwifi-ng芯片组: Atheros AR5212 完美工作，使用起来就像教程中一样．AirLink101 AWLC4130驱动: Madwifi-ng芯片组: Atheros 有人说100%兼容ASUS WL100G驱动: bcm43xx芯片组: Broadcom BCM43xx 启动没找到Belkin F5D6020 v3驱动: Realtek芯片组: rtl8180 包括注入完全兼容Belkin F5D7010 V1000驱动: bcm43xx芯片组: Broadcom BCM43xx 没有完全测试玩Belkin F5D7010 V3000UK驱动: RT61芯片组: Unknown will update later (SORRY) 可以监控，无法注入Belkin F5D7010 V5000驱动: Atheros芯片组: Atheros 很好的工作了Belkin F5D7010 V6000驱动: RT61芯片组: Ralink 改进驱动，作者没有写明是否正常工作Belkin F5D7011驱动: bcm43xx芯片组: Broadcom 4306 启动正常，注入我自己的无线AP正常Buffalo WLI-CB-G54HP驱动: bcm43xx芯片组: Broadcom BCM43xx 正常工作(笔者猜测这也是一张旧的Broadcom卡,因为新的支持的都不太好)Cisco AIR-PCM350驱动: airo芯片组: Cisco Aironet 升级驱动可进入监控模式Cisco Aironet AIR-CB21AG-A-K9驱动: Madwifi-ng芯片组: Atheros 作者未写明Dlink DWA-645驱动: Madwifi-ng芯片组: Atheros AR5416 a/b/g/n 升级驱动Dlink DWL-650+驱动: acx100芯片组: Texas Instruments ACX100 使用一些方法可以调用驱动Dlink DWL-G650驱动: Madwifi-ng芯片组: Atheros AR5212 a/b/g 可以进入监控，注入作者未写明Dlink DWL-G650M芯片组: Atheros Communications, Inc. AR5005VL 802.11bg Wireless NIC (rev 01)Dlink DWL-G650+驱动: Ndiswrapper芯片组:Texas Instruments ACX100 NdisWrapper不能用Aircrack-ng软件包(就是说基本Linux无望)D-Link WNA-1330驱动: Madwifi-ng芯片组: Atheros 发现在监控模式下无法切回频道1正常工作，只能先退出监控模式．Enterasys Roamabout 802.11 DS High Rate驱动: orinoco_cs, wvlan_cs, wavelan_cs芯片组: Hermes I 模式: 802.11b only (11Mbps) 最新的驱动可以监控，但不能注入，注意以前驱动有个大bug.Gigabyte GN-WM01GT AirCruiserG Mach G驱动: madwifi-ng芯片组: Atheros 模式：2.4Ghz 802.11b/g 108Mbps. 除了在包注入时有点问题，其余完美的工作．Linksys WPC11v4驱动: Maxim芯片组: rtl8180 包括注入均能完美的工作Linksys WPC11v4驱动: Philips SA2400芯片组: rtl8180 Notes: Requires terminal input of iwconfig and dhcpcd wlan0 包括注入均能正常的工作Linksys WPC54G v3驱动: bcm43xx芯片组: Broadcom Corporation BCM4318 [AirForce One 54g] 802.11g Wireless LAN Controller (rev 02) 可以监控，无法注入Motorola WN825G v2驱动: bcm43xx芯片组: Broadcom 4306 可以监控，注入未测试，估计和其它Broadcom网卡一样无法注入NetGear MA401驱动: HostAP芯片组: Prism 2 你必须加载HostAP驱动进行注入.NetGear WPN511驱动: Madwifi-ng芯片组: Atheros 包括注入均能工作，经过测试1-5攻击方式发现完美工作．NetGear WPN511 - Range Max驱动: Madwifi-ng芯片组: Atheros AR5212 a/b/g 和大多说Atheros一样，可以工作NetGear WG511T驱动: Madwifi-ng芯片组: Atheros 正常工作，支持全5种攻击方式，如果发现有问题可按下述命令试验：BT ~#airmon-ng stop ath0 BT ~#airmon-ng start wifi0 BT ~#ifconfig ath0 down BT ~#airmon-ng start ath1 BT ~#airmon-ng start wifi0NetGear W AG511v2驱动: Madwifi-ng芯片组: AtherosNetGear WG511 v1驱动: prism54芯片组: Conexant PrismGT FullMAC注意: v2/v3版并不是这个芯片组包括注入均能完美工作。
88E8039网卡驱动安装过程
Marvell 88E8039网卡驱动安装过程
1、首先登录联想网站，点击右下角的“服务与支持”—“驱动下载”
如下图：
图一
2、在“通过驱动编号查找驱动”后边的框内输入88E8039网卡的驱动编号“459”如下图：
图二
3、点击下一步后出现驱动下载界面，点击下载按钮进行下载。
如下图：
图三
4、文件下载成功后找到下载的文件。
如下图：
图四
5、可以新建一个文件夹，将上图中下载好的安装文件复制进去。
双击安装文件后进行解压，文件将解压到当前目录。
解压过程如下图：
图五
6、解压后无直接的安装程序，如下图：
图六
7、依次用鼠标右键点击“我的电脑”，左键点击“属性”，点击“硬件”选择“设备管理器”。
看到带黄色问号“以太网控制器”。
如下图：
图七
8、右键点击“以太网控制器”选择“更新驱动程序”，如下图：
图八
9、选择“否，暂时不”，点击“下一步”。
如下图：
图九
10、选择“从列表或指定位置安装”，点击下一步。
如下图：
图十
11、选择搜索位置，点击“浏览”，选择驱动存放的盘，如C盘或者E盘等。
如下图：
图十一
12、找到刚才解压的文件夹，选择下图中选中的文件夹，点击确定。
如图：
图十二13、点击“下一步”开始安装
图十三14、自动安装过程，等待即可
图十四
15、安装完成。
点击“完成”即可退出，不需要重启计算机。
如下图：
图十五。
MAX系列芯片大全
MAXIM/DALLAS 中文数据资料DS12CR887, DS12R885, DS12R887 RTC，带有恒压涓流充电器DS1870 LDMOS RF功放偏置控制器DS1921L-F5X Thermochron iButtonDS1923 温度/湿度记录仪iButton，具有8kB数据记录存储器DS1982, DS1982-F3, DS1982-F5 1k位只添加iButton?DS1990A 序列号iButtonDS1990R, DS1990R-F3, DS1990R-F5 序列号iButtonDS1991 多密钥iButtonDS2129 LVD SCSI 27线调节器DS2401 硅序列号DS2406 双通道、可编址开关与1k位存储器DS2408 1-Wire、8通道、可编址开关DS2411 硅序列号，带有VCC输入DS2413 1-Wire双通道、可编址开关DS2430A 256位1-Wire EEPROMDS2431 1024位、1-Wire EEPROMDS2480B 串行、1-Wire线驱动器，带有负荷检测DS2482-100 单通道1-Wire主控制器DS2482-100 勘误表PDF: 2482-100A2DS2482-800, DS2482S-800 八通道1-Wire主控制器DS2482-800 勘误表PDF: 2482-800A2DS2502 1k位只添加存储器DS2505 16k位只添加存储器DS28E04-100 4096位、可寻址、1-Wire EEPROM，带有PIODS3170DK DS3/E3单芯片收发器开发板DS3231, DS3231S 高精度、I2C集成RTC/TCXO/晶振DS33Z44 四路以太网映射器DS3902 双路、非易失、可变电阻器，带有用户EEPROMDS3906 三路、非易失、小步长调节可变电阻与存储器DS3984 4路冷阴极荧光灯控制器DS4302 2线、5位DAC，提供三路数字输出DS80C400-KIT DS80C400评估套件DS80C410, DS80C411 具有以太网和CAN接口的网络微控制器DS80C410 勘误表PDF: 80C410A1DS89C430, DS89C440, DS89C450 超高速闪存微控制器DS89C430 勘误表PDF: 89C430A2DS89C440 勘误表PDF: 89C440A2DS89C450 勘误表PDF: 89C450A2DS89C430 勘误表PDF: 89C430A3DS89C440 勘误表PDF: 89C440A3DS89C450 勘误表PDF: 89C450A3DS89C430 勘误表PDF: 89C430A5DS89C440 勘误表PDF: 89C440A5DS89C450 勘误表PDF: 89C450A5DS9090K 1-Wire器件评估板, B版DS9097U-009, DS9097U-E25, DS9097U-S09 通用1-Wire COM端口适配器DS9490, DS9490B, DS9490R USB至1-Wire/iButton适配器MAX1034, MAX1035 8/4通道、±VREF多量程输入、串行14位ADCMAX1072, MAX1075 1.8Msps、单电源、低功耗、真差分、10位ADCMAX1076, MAX1078 1.8Msps、单电源供电、低功耗、真差分、10位ADC，内置电压基准MAX1146, MAX1147, MAX1148, MAX1149 多通道、真差分、串行、14位ADCMAX1149EVKIT MAX1149评估板/评估系统MAX1220, MAX1257, MAX1258 12位、多通道ADC/DAC，带有FIFO、温度传感器和GPIO端口MAX1224, MAX1225 1.5Msps、单电源、低功耗、真差分、12位ADCMAX1258EVKIT MAX1057, MAX1058, MAX1257, MAX1258评估板/评估系统MAX1274, MAX1275 1.8Msps、单电源、低功耗、真差分、12位ADCMAX13000E, MAX13001E, MAX13002E, MAX13003E, MAX13004E, MAX13005E 超低电压电平转换器MAX1302, MAX1303 8/4通道、±VREF多量程输入、串行16位ADCMAX1304, MAX1305, MAX1306, MAX1308, MAX1309, MAX1310, MAX1312, MAX1313,MAX1314 8/4/2通道、12位、同时采样ADC，提供±10V、±5V或0至+5V模拟输入范围MAX13050, MAX13052, MAX13053, MAX13054 工业标准高速CAN收发器，具有±80V故障保护MAX13080E, MAX13081E, MAX13082E, MAX13083E, MAX13084E, MAX13085E, MAX13086E, MAX13087E, MAX13088E, MAX13089E +5.0V、±15kV ESD保护、失效保护、热插拔、RS-485/RS-422收发器MAX13101E, MAX13102E, MAX13103E, MAX13108E 16通道、带有缓冲的CMOS逻辑电平转换器MAX1334, MAX1335 4.5Msps/4Msps、5V/3V、双通道、真差分10位ADCMAX1336, MAX1337 6.5Msps/5.5Msps、5V/3V、双通道、真差分8位ADCMAX13481E, MAX13482E, MAX13483E ±15kV ESD保护USB收发器, 外部/内部上拉电阻MAX1350, MAX1351, MAX1352, MAX1353, MAX1354, MAX1355, MAX1356, MAX1357 双路、高端、电流检测放大器和驱动放大器MAX1450 低成本、1%精确度信号调理器，用于压阻式传感器MAX1452 低成本、精密的传感器信号调理器MAX1487, MAX481, MAX483, MAX485, MAX487, MAX488, MAX489, MAX490, MAX491 低功耗、限摆率、RS-485/RS-422收发器MAX1492, MAX1494 3位半和4位半、单片ADC，带有LCD驱动器MAX1494EVKIT MAX1493, MAX1494, MAX1495评估板/评估系统MAX1497, MAX1499 3位半和4位半、单片ADC，带有LED驱动器和μC接口MAX1499EVKIT MAX1499评估板/评估系统MAX15000, MAX15001 电流模式PWM控制器, 可调节开关频率MAX1515 低电压、内置开关、降压/DDR调节器MAX1518B TFT-LCD DC-DC转换器, 带有运算放大器MAX1533, MAX1537 高效率、5路输出、主电源控制器，用于笔记本电脑MAX1533EVKIT MAX1533评估板MAX1540A, MAX1541 双路降压型控制器，带有电感饱和保护、动态输出和线性稳压器MAX1540EVKIT MAX1540评估板MAX1551, MAX1555 SOT23、双输入、USB/AC适配器、单节Li+电池充电器MAX1553, MAX1554 高效率、40V、升压变换器，用于2至10个白光LED驱动MAX1556, MAX1557 16μA IQ、1.2A PWM降压型DC-DC转换器MAX1556EVKIT MAX1556EVKIT评估板MAX1558, MAX1558H 双路、3mm x 3mm、1.2A/可编程电流USB开关，带有自动复位功能MAX1586A, MAX1586B, MAX1586C, MAX1587A, MAX1587C 高效率、低IQ、带有动态内核的PMIC，用于PDA和智能电话MAX16801A/B, MAX16802A/B 离线式、DC-DC PWM控制器, 用于高亮度LED驱动器MAX1858A, MAX1875A, MAX1876A 双路180°异相工作的降压控制器，具有排序/预偏置启动和POR MAX1870A 升/降压Li+电池充电器MAX1870AEVKIT MAX1870A评估板MAX1874 双路输入、USB/AC适配器、1节Li+充电器，带OVP与温度调节MAX1954A 低成本、电流模式PWM降压控制器，带有折返式限流MAX1954AEVKIT MAX1954A评估板MAX19700 7.5Msps、超低功耗模拟前端MAX19700EVKIT MAX19700评估板/评估系统MAX19705 10位、7.5Msps、超低功耗模拟前端MAX19706 10位、22Msps、超低功耗模拟前端MAX19707 10位、45Msps、超低功耗模拟前端MAX19708 10位、11Msps、超低功耗模拟前端MAX2041 高线性度、1700MHz至3000MHz上变频/下变频混频器，带有LO缓冲器/开关MAX2043 1700MHz至3000MHz高线性度、低LO泄漏、基站Rx/Tx混频器MAX220, MAX222, MAX223, MAX225, MAX230, MAX231, MAX232, MAX232A, MAX233,MAX233A, MAX234, MAX235, MAX236, MAX237, MAX238, MAX239, MAX240, MAX241,MAX242, MAX243, MAX244, MAX245, MAX246, MAX247, MAX248, MAX249 +5V供电、多通道RS-232驱动器/接收器MAX2335 450MHz CDMA/OFDM LNA/混频器MAX2370 完备的、450MHz正交发送器MAX2370EVKIT MAX2370评估板MAX2980 电力线通信模拟前端收发器MAX2986 集成电力线数字收发器MAX3013 +1.2V至+3.6V、0.1μA、100Mbps、8路电平转换器MAX3205E, MAX3207E, MAX3208E 双路、四路、六路高速差分ESD保护ICMAX3301E, MAX3302E USB On-the-Go收发器与电荷泵MAX3344E, MAX3345E ±15kV ESD保护、USB收发器，UCSP封装，带有USB检测MAX3394E, MAX3395E, MAX3396E ±15kV ESD保护、大电流驱动、双/四/八通道电平转换器, 带有加速电路MAX3535E, MXL1535E +3V至+5V、提供2500VRMS隔离的RS-485/RS-422收发器，带有±15kV ESD保护MAX3570, MAX3571, MAX3573 HI-IF单芯片宽带调谐器MAX3643EVKIT MAX3643评估板MAX3645 +2.97V至+5.5V、125Mbps至200Mbps限幅放大器，带有信号丢失检测器MAX3645EVKIT MAX3645评估板MAX3654 47MHz至870MHz模拟CATV互阻放大器MAX3654EVKIT MAX3654评估板MAX3657 155Mbps低噪声互阻放大器MAX3658 622Mbps、低噪声、高增益互阻前置放大器MAX3735, MAX3735A 2.7Gbps、低功耗、SFP激光驱动器MAX3737 多速率激光驱动器，带有消光比控制MAX3737EVKIT MAX3737评估板MAX3738 155Mbps至2.7Gbps SFF/SFP激光驱动器，带有消光比控制MAX3744, MAX3745 2.7Gbps SFP互阻放大器，带有RSSIMAX3744EVKIT, MAX3745EVKIT MAX3744, MAX3745评估板MAX3748, MAX3748A, MAX3748B 紧凑的、155Mbps至4.25Gbps限幅放大器MAX3785 6.25Gbps、1.8V PC板均衡器MAX3787EVKIT MAX3787评估板MAX3793 1Gbps至4.25Gbps多速率互阻放大器，具有光电流监视器MAX3793EVKIT MAX3793评估板MAX3805 10.7Gbps自适应接收均衡器MAX3805EVKIT MAX3805评估板MAX3840 +3.3V、2.7Gbps双路2 x 2交叉点开关MAX3841 12.5Gbps CML 2 x 2交叉点开关MAX3967 270Mbps SFP LED驱动器MAX3969 200Mbps SFP限幅放大器MAX3969EVKIT MAX3969评估板MAX3982 SFP铜缆预加重驱动器MAX3983 四路铜缆信号调理器MAX3983EVKIT MAX3983评估板MAX3983SMAEVKIT MAX3983 SMA连接器评估板MAX4079 完备的音频/视频后端方案MAX4079EVKIT MAX4079评估板MAX4210, MAX4211 高端功率、电流监视器MAX4210EEVKIT MAX4210E、MAX4210A/B/C/D/F评估板MAX4211EEVKIT MAX4211A/B/C/D/E/F评估板MAX4397 用于双SCART连接器的音频/视频开关MAX4397EVKIT MAX4397评估系统/评估板MAX4411EVKIT MAX4411评估板MAX4729, MAX4730 低电压、3.5、SPDT、CMOS模拟开关MAX4754, MAX4755, MAX4756 0.5、四路SPDT开关，UCSP/QFN封装MAX4758, MAX4759 四路DPDT音频/数据开关，UCSP/QFN封装MAX4760, MAX4761 宽带、四路DPDT开关MAX4766 0.075A至1.5A、可编程限流开关MAX4772, MAX4773 200mA/500mA可选的限流开关MAX4795, MAX4796, MAX4797, MAX4798 450mA/500mA限流开关MAX4826, MAX4827, MAX4828, MAX4829, MAX4830, MAX4831 50mA/100mA限流开关, 带有空载标记, μDFN封装MAX4832, MAX4833 100mA LDO，带有限流开关MAX4834, MAX4835 250mA LDO，带有限流开关MAX4836, MAX4837 500mA LDO，带有限流开关MAX4838A, MAX4840A, MAX4842A 过压保护控制器，带有状态指示FLAGMAX4850, MAX4850H, MAX4852, MAX4852H 双路SPDT模拟开关，可处理超摆幅信号MAX4851, MAX4851H, MAX4853, MAX4853H 3.5/7四路SPST模拟开关，可处理超摆幅信号MAX4854 7四路SPST模拟开关，可处理超摆幅信号MAX4854H, MAX4854HL 四路SPST、宽带、信号线保护开关MAX4855 0.75、双路SPDT音频开关，具有集成比较器MAX4864L, MAX4865L, MAX4866L, MAX4867, MAX4865, MAX4866 过压保护控制器，具有反向保护功能MAX4880 过压保护控制器, 内置断路开关MAX4881, MAX4882, MAX4883, MAX4884 过压保护控制器, 内部限流, TDFN封装MAX4901, MAX4902, MAX4903, MAX4904, MAX4905 低RON、双路SPST/单路SPDT、无杂音切换开关, 可处理负电压MAX4906, MAX4906F, MAX4907, MAX4907F 高速/全速USB 2.0开关MAX5033 500mA、76V、高效率、MAXPower降压型DC-DC变换器MAX5042, MAX5043 双路开关电源IC，集成了功率MOSFET和热插拔控制器MAX5058, MAX5059 可并联的副边同步整流驱动器和反馈发生器控制ICMAX5058EVKIT MAX5051, MAX5058评估板MAX5062, MAX5062A, MAX5063, MAX5063A, MAX5064, MAX5064A, MAX5064B 125V/2A、高速、半桥MOSFET驱动器MAX5065, MAX5067 双相、+0.6V至+3.3V输出可并联、平均电流模式控制器MAX5070, MAX5071 高性能、单端、电流模式PWM控制器MAX5072 2.2MHz、双输出、降压或升压型转换器，带有POR和电源失效输出MAX5072EVKIT MAX5072评估板MAX5074 内置MOSFET的电源IC，用于隔离型IEEE 802.3af PD和电信电源MAX5078 4A、20ns、MOSFET驱动器MAX5084, MAX5085 65V、200mA、低静态电流线性稳压器, TDFN封装MAX5088, MAX5089 2.2MHz、2A降压型转换器, 内置高边开关MAX5094A, MAX5094B, MAX5094C, MAX5094D, MAX5095A, MAX5095B, MAX5095C 高性能、单端、电流模式PWM控制器MAX5128 128抽头、非易失、线性变化数字电位器, 采用2mm x 2mm μDFN封装MAX5417, MAX5417L, MAX5417M, MAX5417N, MAX5417P, MAX5418, MAX5419 256抽头、非易失、I2C接口、数字电位器MAX5417LEVKIT MAX5417_, MAX5418_, MAX5419_评估板/评估系统MAX5477, MAX5478, MAX5479 双路、256抽头、非易失、I2C接口、数字电位器MAX5478EVKIT MAX5477/MAX5478/MAX5479评估板/评估系统MAX5490 100k精密匹配的电阻分压器，SOT23封装MAX5527, MAX5528, MAX5529 64抽头、一次性编程、线性调节数字电位器MAX5820 双路、8位、低功耗、2线、串行电压输出DACMAX5865 超低功耗、高动态性能、40Msps模拟前端MAX5920 -48V热插拔控制器，外置RsenseMAX5921, MAX5939 -48V热插拔控制器，外置Rsense、提供较高的栅极下拉电流MAX5932 正电源、高压、热插拔控制器MAX5932EVKIT MAX5932评估板MAX5936, MAX5937 -48V热插拔控制器，可避免VIN阶跃故障，无需RSENSEMAX5940A, MAX5940B IEEE 802.3af PD接口控制器，用于以太网供电MAX5940BEVKIT MAX5940B, MAX5940D评估板MAX5941A, MAX5941B 符合IEEE 802.3af标准的以太网供电接口/PWM控制器，适用于用电设备MAX5945 四路网络电源控制器，用于网络供电MAX5945EVKIT, MAX5945EVSYS MAX5945评估板/评估系统MAX5953A, MAX5953B, MAX5953C, MAX5953D IEEE 802.3af PD接口和PWM控制器，集成功率MOSFETMAX6640 2通道温度监视器，提供双路、自动PWM风扇速度控制器MAX6640EVKIT MAX6640评估系统/评估板MAX6641 兼容于SMBus的温度监视器，带有自动PWM风扇速度控制器MAX6643, MAX6644, MAX6645 自动PWM风扇速度控制器，带有过温报警输出MAX6678 2通道温度监视器，提供双路、自动PWM风扇速度控制器和5个GPIOMAX6695, MAX6696 双路远端/本地温度传感器，带有SMBus串行接口MAX6877EVKIT MAX6877评估板MAX6950, MAX6951 串行接口、+2.7V至+5.5V、5位或8位LED显示驱动器MAX6966, MAX6967 10端口、恒流LED驱动器和输入/输出扩展器，带有PWM亮度控制MAX6968 8端口、5.5V恒流LED驱动器MAX6969 16端口、5.5V恒流LED驱动器MAX6970 8端口、36V恒流LED驱动器MAX6977 8端口、5.5V恒流LED驱动器，带有LED故障检测MAX6978 8端口、5.5V恒流LED驱动器，带有LED故障检测和看门狗MAX6980 8端口、36V恒流LED驱动器, 带有LED故障检测和看门狗MAX6981 8端口、36V恒流LED驱动器, 带有LED故障检测MAX7030 低成本、315MHz、345MHz和433.92MHz ASK收发器, 带有N分频PLLMAX7032 低成本、基于晶振的可编程ASK/FSK收发器, 带有N分频PLLMAX7317 10端口、SPI接口输入/输出扩展器，带有过压和热插入保护MAX7319 I2C端口扩展器，具有8路输入，可屏蔽瞬态检测MAX7320 I2C端口扩展器, 带有八个推挽式输出MAX7321 I2C端口扩展器，具有8个漏极开路I/O口MAX7328, MAX7329 I2C端口扩展器, 带有八个I/O口MAX7347, MAX7348, MAX7349 2线接口、低EMI键盘开关和发声控制器MAX7349EVKIT MAX7349评估板/仿真: MAX7347/MAX7348MAX7375 3引脚硅振荡器MAX7381 3引脚硅振荡器MAX7389, MAX7390 微控制器时钟发生器, 带有看门狗MAX7391 快速切换时钟发生器, 带有电源失效检测MAX7445 4通道视频重建滤波器MAX7450, MAX7451, MAX7452 视频信号调理器，带有AGC和后肩钳位MAX7452EVKIT MAX7452评估板MAX7462, MAX7463 单通道视频重建滤波器和缓冲器MAX8505 3A、1MHz、1%精确度、内置开关的降压型调节器，带有电源就绪指示MAX8524, MAX8525 2至8相VRM 10/9.1 PWM控制器，提供精密的电流分配和快速电压定位MAX8525EVKIT MAX8523, MAX8525评估板MAX8533 更小、更可靠的12V、Infiniband兼容热插拔控制器MAX8533EVKIT MAX8533评估板MAX8545, MAX8546, MAX8548 低成本、宽输入范围、降压控制器，带有折返式限流MAX8550, MAX8551 集成DDR电源方案，适用于台式机、笔记本电脑及图形卡MAX8550EVKIT MAX8550, MAX8550A, MAX8551评估板MAX8552 高速、宽输入范围、单相MOSFET驱动器MAX8553, MAX8554 4.5V至28V输入、同步PWM降压控制器，适合DDR端接和负载点应用MAX8563, MAX8564 ±1%、超低输出电压、双路或三路线性n-FET控制器MAX8564EVKIT MAX8563, MAX8564评估板MAX8566 高效、10A、PWM降压调节器, 内置开关MAX8570, MAX8571, MAX8572, MAX8573, MAX8574, MAX8575 高效LCD升压电路，可True ShutdownMAX8571EVKIT MAX8570, MAX8571, MAX8572, MAX8573, MAX8574, MAX8575评估板MAX8576, MAX8577, MAX8578, MAX8579 3V至28V输入、低成本、迟滞同步降压控制器MAX8594, MAX8594A 5路输出PMIC，提供DC-DC核电源，用于低成本PDAMAX8594EVKIT MAX8594评估板MAX8632 集成DDR电源方案，适用于台式机、笔记本电脑和图形卡MAX8632EVKIT MAX8632评估板MAX8702, MAX8703 双相MOSFET驱动器，带有温度传感器MAX8707 多相、固定频率控制器，用于AMD Hammer CPU核电源MAX8716, MAX8717, MAX8757 交叉工作、高效、双电源控制器，用于笔记本电脑MAX8716EVKIT MAX8716评估板MAX8717EVKIT MAX8717评估板MAX8718, MAX8719 高压、低功耗线性稳压器，用于笔记本电脑MAX8725EVKIT MAX8725评估板MAX8727 TFT-LCD升压型、DC-DC变换器MAX8727EVKIT MAX8727评估板MAX8729 固定频率、半桥CCFL逆变控制器MAX8729EVKIT MAX8729评估板MAX8732A, MAX8733A, MAX8734A 高效率、四路输出、主电源控制器，用于笔记本电脑MAX8737 双路、低电压线性稳压器, 外置MOSFETMAX8737EVKIT MAX8737评估板MAX8738 EEPROM可编程TFT VCOM校准器, 带有I2C接口MAX8740 TFT-LCD升压型、DC-DC变换器MAX8743 双路、高效率、降压型控制器，关断状态下提供高阻MAX8751 固定频率、全桥、CCFL逆变控制器MAX8751EVKIT MAX8751评估板MAX8752 TFT-LCD升压型、DC-DC变换器MAX8758 具有开关控制和运算放大器的升压调节器, 用于TFT LCDMAX8758EVKIT MAX8758评估板MAX8759 低成本SMBus CCFL背光控制器MAX8760 双相、Quick-PWM控制器，用于AMD Mobile Turion 64 CPU核电源MAX8764 高速、降压型控制器，带有精确的限流控制，用于笔记本电脑MAX9223, MAX9224 22位、低功耗、5MHz至10MHz串行器与解串器芯片组MAX9225, MAX9226 10位、低功耗、10MHz至20MHz串行器与解串器芯片组MAX9483, MAX9484 双输出、多模CD-RW/DVD激光二极管驱动器MAX9485 可编程音频时钟发生器MAX9485EVKIT MAX9485评估板MAX9486 8kHz参考时钟合成器，提供35.328MHz倍频输出MAX9486EVKIT MAX9486评估板MAX9489 多路输出网络时钟发生器MAX9500, MAX9501 三通道HDTV滤波器MAX9500EVKIT MAX9500评估板MAX9501EVKIT MAX9501评估板MAX9502 2.5V视频放大器, 带有重建滤波器MAX9504A, MAX9504B 3V/5V、6dB视频放大器, 可提供大电流输出MAX9701 1.3W、无需滤波、立体声D类音频功率放大器MAX9701EVKIT MAX9701评估板MAX9702 1.8W、无需滤波、立体声D类音频功率放大器和DirectDrive立体声耳机放大器MAX9702EVSYS/EVKIT MAX9702/MAX9702B评估系统/评估板MAX9703, MAX9704 10W立体声/15W单声道、无需滤波的扩展频谱D类放大器MAX9705 2.3W、超低EMI、无需滤波、D类音频放大器MAX9705BEVKIT MAX9705B评估板MAX9710EVKIT MAX9710评估板MAX9712 500mW、低EMI、无需滤波、D类音频放大器MAX9713, MAX9714 6W、无需滤波、扩频单声道/立体声D类放大器MAX9714EVKIT MAX9704, MAX9714评估板MAX9715 2.8W、低EMI、立体声、无需滤波、D类音频放大器MAX9715EVKIT MAX9715评估板MAX9716, MAX9717 低成本、单声道、1.4W BTL音频功率放大器MAX9716EVKIT MAX9716评估板MAX9718, MAX9719 低成本、单声道/立体声、1.4W差分音频功率放大器MAX9718AEVKIT MAX9718A评估板MAX9719AEVKIT MAX9719A/B/C/D评估板MAX9721 1V、固定增益、DirectDrive、立体声耳机放大器，带有关断MAX9721EVKIT MAX9721评估板MAX9722A, MAX9722B 5V、差分输入、DirectDrive、130mW立体声耳机放大器，带有关断MAX9722AEVKIT MAX9722A, MAX9722B评估板MAX9723 立体声DirectDrive耳机放大器, 具有BassMax、音量控制和I2C接口MAX9725 1V、低功率、DirectDrive、立体声耳机放大器，带有关断MAX9728AEVKIT MAX9728A/MAX9728B评估板MAX9750, MAX9751, MAX9755 2.6W立体声音频功放和DirectDrive耳机放大器MAX9759 3.2W、高效、低EMI、无需滤波、D类音频放大器MAX9759EVKIT MAX9759评估板MAX9770, MAX9772 1.2W、低EMI、无需虑波、单声道D类放大器，带有立体声DirectDrive耳机放大器MAX9787 2.2W立体声音频功率放大器, 提供模拟音量控制MAX9850 立体声音频DAC，带有DirectDrive耳机放大器MAX9890 音频咔嗒声-怦然声抑制器MAX9951, MAX9952 双路引脚参数测量单元MAX9960 双闪存引脚电子测量/高压开关矩阵MAX9961, MAX9962 双通道、低功耗、500Mbps ATE驱动器/比较器，带有2mA负载MAX9967 双通道、低功耗、500Mbps ATE驱动器/比较器，带有35mA负载MAX9986A SiGe高线性度、815MHz至1000MHz下变频混频器, 带有LO缓冲器/开关MAXQ2000 低功耗LCD微控制器MAXQ2000 勘误表PDF: MAXQ2000A2MAXQ2000-KIT MAXQ2000评估板MAXQ3120-KIT MAXQ3120评估板MXL1543B +5V、多协议、3Tx/3Rx、软件可选的时钟/数据收发器。
无线路由器CPU 闪存 内存 芯片 列表【VIP专享】
品牌规格cpu主频闪存/内存无线芯片参考价迅捷FWR300T+Atheros AR9132400MHZ4/32AtherosAR910390水星MWR300T+（旧款长方形的）Atheros AR9132400MHZ4/32 V1版新款可能有缩水AtherosAR910390TP-LINK TL-WR941N Atheros AR9132400MHZ4/32AtherosAR9103D-LINK DIR618RealtekRTL8196B 400MHZ2/16RealtekRTL8192SE华硕RT-N56U RalinkRT3662F+RT3092500MHZ8/128主芯片集成TOTOLINK N5004BroadcomBCM4718A533 MHZ4/16主芯片集成贝尔金畅享版BroadcomBCM4718A533 MHZ8/64主芯片集成华硕RT-N16BroadcomBCM4718A533 MHZ32/128主芯片集成型号&版本CPU主频无线芯片RAMSize Flash天线数TP-LINK/MW/FWTL-WR843N AR9341200mhz32M4MTL-WR841N V8AR9341200mhz16M4M2 TL-WR841N V7AR7241-AH1A360AR928732M4M2 TL-WR740N V4AR7240400AR928532M4M1 TL-WR2543ND AR7242400AR938064M8MTL-WR1041N AR9342-AL1A550AR832732M4MTL-WR800N AR934120016MTL-WA901NDV2.xAR9132400AR541632M4MTL-WA901NDV1.xAR7240400AR928532M4MTL-WA801NDv1.1AR724x查不了AR9238-AL1A 32M4MTL-WA701ND v1AR724040032M4M MW310R V1AR934120016M4M3MW300R V4AR934120016M2M MW300R V3AR934120016M4M2 MW300r v2AR72416802 TL-WDR4310AR9344 533AR9580128M8MTL-WDR7500QCA9880[AC]600QCA9558[N]128MMW150R V8.4AR9331400D-LINKDir615-1 F2RTL8196B 400RTL8192SEDIR615 C1AR9130400AR8216DIR615L J1RTL8196C 400RTL8192SEDIR600NW A1RT3050F320腾达W811R RT3050F320N300R BCM5357C0533N308R BCM5357500N309R BCM5357500N3000BCM5357500W311R_2011RT3050F320W311R V2BCM5356333W311R V3BCM5356333A5S RT5350F360A6RT5350F360N4RT5350F360W268R RT3050F320W307R RT2880F266W837R BCM5357500磊科NW614RTL8196C400NW714RTL8196C400RTL8192CENW715P BCM5357B0533超频NW736BCM5357200NW735BCM5357200NR235W BCM5357C0300超频NW716RTL8196C400RTL8192CENW762NW765BCM5358500BCM4323NW705+ V1.1RTL8196C400RTL8188RENW705同上NW604不明牌子400 TP-link(以下均是)TL-R860+ v2.08口有线路由9vcpu 88E6218-LG01 150MHZis42s16400B-7TL 内存64MBEN29LV160AB 闪存2MBS29AL908D70TE102 不明芯片TL-WR641G Athreos AR2316 + Marvell 88E6060 TL-WR641G+ Athreos AR2318 + Marvell 88E6060 TL-WR642G Athreos AR2316 + Marvell 88E6060 TL-WR642G+ Athreos AR2318 + Marvell 88E6060 TL-WN610G Athreos AR2414TL-WN620G Athreos AR5523TL-WN650G Athreos AR2414TL-WN651G Athreos AR2414TL-WN660G Athreos AR2414TL-WN612AG Athreos AR5414TL-WN652AG Athreos AR5414TL-WN653AG Athreos AR5414TL-WN662AG Athreos AR5414TL-WR541G Athreos AR2413 + Marvell 801012 TL-WR541G+ Athreos AR2317 + Marvell 88E6060 TL-WR542G Athreos AR2317 + Marvell 88E6060 TL-WA501G Athreos AR2315 + Realtek RTL8201 TL-WN510G Athreos AR2413TL-WN550G Athreos AR2413TL-WN551G Athreos AR2413TL-WN321G Ralink RT2571WTL-WN321G Ralink RT2571WTL-WN560G Athreos AR2413TL-WN512AG Athreos AR5413TL-WN552AG Athreos AR5413TL-WN553AG Athreos AR5413TL-WN562AG Athreos AR5413TL-ANT2402A N/ATL-ANT2405C N/ATL-ANT2406A N/ATL-ANT2409A N/ATL-ANT2414A N/ATD-8610 Annex A) Broadcom BCM6338 + BCM6301TD-8610 Annex B) Broadcom BCM6338 + BCM6301TD-8810 (Annex A) Broadcom BCM6338 + BCM6301TD-8810 (Annex B) Broadcom BCM6338 + BCM6301TD-8811 (Annex A) Broadcom BCM6338 + BCM6301TD-8811 (Annex B) Broadcom BCM6338 + BCM6301TD-8840 (Annex A) Broadcom BCM6338 + BCM6301TD-8840 (Annex B) Broadcom BCM6338 + BCM6301TD-8841 (Annex A) Broadcom BCM6338 + BCM6301TD-8841 (Annex B) Broadcom BCM6338 + BCM6301TL-W8910G Atheros AR2413TL-W8920G Atheros AR2414TL-R402M Marvell 88E6218TL-R460 Marvell 88E6218TL-R860 Marvell 88E6218+Marvell 88E6060(Switch)TL-R860+ Marvell 88E6218 is42s16400B-7TL 内存64MB EN29LV160AB 闪存2MB S29AL908D70TE102不明芯片TL-R480T Intel FWIXP420BB (CPU) + Marvell 88E6063 (Switch)TL-R4000 Intel FWIXP420BB (CPU) + Marvell 88E6063 (Switch)TL-R480T+ Intel FWIXP420BB (CPU) + Marvell 88E6063 (Switch)TL-R488T Intel FWIXP425BD (CPU) + Marvell 88E6063 (Switch)TL-R4000+ Intel FWIXP425BD (CPU) +Marvell 88E6063 (Switch)TL-SG3109 Marvell 88E6185 (MAC) + 88E1145 (PHY) + 88E6218 (CPU)TL-SG3216 Marvell 98DX160 (MAC) + 88E1145 + 88E1111 + 88E1112 (PHY) + 88E6218 (CPU)TL-SG3224 Marvell 98DX240 (MAC) + 88E1145 + 88E1111 + 88E1112 (PHY) + 88E6218 (CPU)TL-SG3248 Marvell 98DX26x (MAC) + 88E1145 + 88E1111 + 88E1112 (PHY) + 88E6218 (CPU)TL-SL3428 Marvell 88E6185 + 88E6095 (MAC) + 88E1111 (PHY) + 88E6218 (CPU)TL-SL3452 Marvell 88E6185 + 88E6095 (MAC) + 88E1111 (PHY) + 88E6218 (CPU)TL-SG2109WEB Marvell 88E6182 (MAC) + 88E1145 (PHY) + 88E6218 (CPU)TL-SG2216WEB Marvell 98DX162 (MAC) + 88E1145 + 88E1111 + 88E1112 (PHY) + 88E6218 (CPU)TL-SG2224WEB Marvell 98DX242 (MAC) + 88E1145 + 88E1111 + 88E1112 (PHY) + 88E6218 (CPU)TL-SG2248WEB Marvell 98DX262 (MAC) + 88E1145 + 88E1111 + 88E1112 (PHY) + 88E6218 (CPU)TL-SL2210WEB Marvell 88E6092 (MAC) + 88E1111 (PHY) + 88E6218 (CPU)TL-SL2218WEB Marvell 88E6092 (MAC) + 88E1111 (PHY) + 88E6218 (CPU)TL-SL2428WEB Marvell 88E6182 + 88E6092 (MAC) + 88E1111 (PHY) + 88E6218 (CPU)TL-SL2452WEB Marvell 88E6182 + 88E6092 (MAC) + 88E1111 (PHY) + 88E6218 (CPU)TL-SG1005D Vitesse VSC7385TL-SG1008D Vitesse VSC7388TL-SG1008 Vitesse VSC7388TL-SG1016 Vitesse VSC7389 (MAC) + VSC8538 (PHY)TL-SG1016 Marvell 98DX161 (MAC) + 88E1149 (PHY)TL-SG1016D Marvell 98DX161 (MAC) + 88E1149 (PHY)TL-SG1024 Vitesse VSC7390 (MAC) + VSC8538 (PHY)TL-SG1024 Marvell 98DX241 (MAC) + 88E1149 (PHY)TL-SL1109 Realtek RTL8310 (MAC) + RTL8208B (PHY)TL-SL1117 Realtek RTL8318 (MAC) + RTL8208B (PHY)TL-SL1226 Realtek RTL8326(MAC)+ RTL8208-VF(PHY)+ Cicada CIS8201(PHY) TL-SL1351 Marvell 88E6182 + 88E6092 (MAC) + 88E1111 (PHY) + 88E6218 (CPU) TL-SF1005D Realtek RTL8305SCTL-SF1005D Marvell 88E6060TL-SF1008D Realtek RTL8309SBTL-SF1016D Realtek RTL8309SBTL-SF1016 Realtek RTL8316B (MAC) + RTL8208(PHY)TL-SF1016 Realtek RTL8316B (MAC) + RTL8208(PHY)TL-SF1024 Realtek RTL8324 (MAC) + RTL8208B (PHY)TL-SF1048 Realtek RTL8326 (MAC) + RTL8208-VF(PHY)TL-SM201CM Altima AC101TL-SM201CS Altima AC101TL-SM311LM N/ATL-SM311LS N/ATR-966D Realtek RTL8305SCTR-965DA Realtek RTL8305SCTR-965DB Realtek RTL8305SCTR-932D Realtek RTL8305SCTR-962D Realtek RTL8305SCTG-3269 Realtek RTL8169SCTG-3201 Marvell 88E8001TF-3239D Realtek RTL8139DTF-3239DL Realtek RTL8139DTF-5239 Realtek RTL8139CLTM-IP5600 Motorola PCI 3 (Si3052+Si3007)TM-EC5658V Intel MD5660 + MD4450 + MD1724。
亿佰特-TLSR8359 2.4GHz低功耗纯硬件SoC无线模块 E03-2G4M10S使用手册
目录第一章概述 (1)1.1 简介 (1)1.2 特点功能 (1)1.3 应用场景 (1)第二章规格参数 (1)2.1 极限参数 (1)2.2 工作参数 (2)第三章机械尺寸与引脚定义 (3)第四章基本操作 (4)4.1 硬件设计 (4)第五章常见问题 (5)5.1 传输距离不理想 (5)5.2 模块易损坏 (5)5.3 误码率太高 (5)第六章焊接作业指导 (6)6.1 回流焊温度 (6)6.2 回流焊曲线图 (6)第七章天线指南 (7)7.1 天线推荐 (7)第八章批量包装方式 (7)第一章概述1.1 简介E03-2G4M10S是基于TELINK TLSR8359无线SOC设计生产的一款小体积、低功耗、高可靠性、工作在2.4GHz 频段的模块，芯片自带32位高性能MCU，发射功率最高可达到10dBm。
TLSR8359支持硬件OTA升级和多种启动切换，方便产品的特性推出和升级,由于该模块是纯硬件类SoC模块，需要用户对其编程后方可使用。
1.2 特点功能●最大发射功率10dBm，软件多级可调；●支持全球免许可ISM 2.4GHz频段；●14位ADC与PGA,● 6通道PWM●一个正交解码器(QDEC)，●丰富和灵活的GPIO接口；●丰富的资源，512kB FLASH，64kB RAM；●支持1.8～3.6V供电，大于3.3V供电均可保证最佳性能；●工业级标准设计，支持-40～+85℃下使用；●理想条件下，通信距离可达600m；1.3 应用场景●零售/物流●专用网络●灯塔第二章规格参数2.1 极限参数2.2 工作参数第三章机械尺寸与引脚定义第四章基本操作4.1硬件设计●推荐使用直流稳压电源对该模块进行供电，电源纹波系数尽量小，模块需可靠接地；●请注意电源正负极的正确连接，如反接可能会导致模块永久性损坏；●请检查供电电源，确保在推荐供电电压之间，如超过最大值会造成模块永久性损坏；●请检查电源稳定性，电压不能大幅频繁波动；●在针对模块设计供电电路时，往往推荐保留30%以上余量，有整机利于长期稳定地工作；●模块应尽量远离电源、变压器、高频走线等电磁干扰较大的部分；●高频数字走线、高频模拟走线、电源走线必须避开模块下方，若实在需要经过模块下方，假设模块焊接在Top Layer，在模块接触部分的Top Layer铺地铜（全部铺铜并良好接地），必须靠近模块数字部分并走线在Bottom Layer；●假设模块焊接或放置在Top Layer，在Bottom Layer或者其他层随意走线也是错误的，会在不同程度影响模块的杂散以及接收灵敏度；●假设模块周围有存在较大电磁干扰的器件也会极大影响模块的性能，跟据干扰的强度建议适当远离模块，若情况允许可以做适当的隔离与屏蔽；●假设模块周围有存在较大电磁干扰的走线（高频数字、高频模拟、电源走线）也会极大影响模块的性能，跟据干扰的强度建议适当远离模块，若情况允许可以做适当的隔离与屏蔽；●通信线若使用5V电平，必须串联1k-5.1k电阻（不推荐，仍有损坏风险）；●尽量远离部分物理层亦为2.4GHz的TTL协议，例如：USB3.0；●天线安装结构对模块性能有较大影响，务必保证天线外露，最好垂直向上。
ksz8851-16mll_ds芯片手册
KSZ8851-16MLL/MLLI/MLLUSingle-Port Ethernet MAC Controllerwith 8-Bit or 16-Bit Non-PCI InterfaceRevision 2.2General DescriptionThe KSZ8851M-series is a single-port controller chip witha non-PCI CPU interface and is available in 8-bit and 16-bit bus designs. This datasheet describes the 48-pin LQFPKSZ8851-16MLL for applications requiring high-performance from single-port Ethernet Controller with 8-bitor 16-bit generic processor interface. The KSZ8851-16MLL offers the most cost-effective solution for addinghigh-throughput Ethernet connectivity to traditionalembedded systems.The KSZ8851-16MLL is a single chip, mixed analog/digitaldevice offering Wake-on-LAN technology for effectivelyaddressing Fast Ethernet applications. It consists of a fastEthernet MAC controller, an 8-bit or 16-bit generic hostprocessor interface and incorporates a unique dynamicmemory pointer with 4-byte buffer boundary and a fullyutilizable 18KB for both TX (allocated 6KB) and RX(allocated 12KB) directions in host buffer interface.The KSZ8851-16MLL is designed to be fully compliant withthe appropriate IEEE 802.3 standards. An industrialtemperature-grade version of the KSZ8851-16MLLI and aqualified AEC-Q100 Automotive version of the KSZ8851-16MLLU are also available (see “Ordering Information”section).LinkMD®Physical signal transmission and reception are enhancedthrough the use of analog circuitry. This makes the designmore efficient and allows lower-power consumption. TheKSZ8851-16MLL is designed using a low-power CMOSprocess that features a single 3.3V power supply withoptions for 1.8V, 2.5V or 3.3V VDD I/O. The deviceincludes an extensive feature set that offers managementinformation base (MIB) counters and CPU control/datainterfaces with single shared data bus timing.The KSZ8851-16MLL includes a unique cable diagnosticsfeature called LinkMD®. This feature determines the lengthof the cabling plant and also ascertains if there is an openor short condition in the cable. Accompanying softwareenables the cable length and cable conditions to beconveniently displayed. In addition, the KSZ8851-16MLLsupports Hewlett Packard (HP) Auto-MDIX therebyeliminating the need to differentiate between straight orcrossover cables in applications.Functional DiagramFigure 1. KSZ8851-16MLL/MLLI Functional DiagramFeatures•Integrated MAC and PHY Ethernet Controller fully compliant with IEEE 802.3/802.3µ standards •Designed for high performance and high throughput applications•Supports 10BASE-T/100BASE-TX•Supports IEEE 802.3x full-duplex flow control and half-duplex backpressure collision flow control •Supports DMA-slave burst data read and write transfers•Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking•Supports IPv6 TCP/UDP/ICMP checksum generation and checking•Automatic 32-bit CRC generation and checking •Simple SRAM-like host interface easily connects to most common embedded MCUs.•Supports multiple data frames for receive without address bus and byte-enable signals•Supports both Big- and Little-Endian processors •Larger internal memory with 12K Bytes for RX FIFO and 6K Bytes for TX FIFO. Programmable low, highand overrun watermark for flow control in RX FIFO •Shared data bus for Data, Address and Byte Enable •Efficient architecture design with configurable host interrupt schemes to minimize host CPU overhead and utilization•Powerful and flexible address filtering scheme •Optional to use external serial EEPROM configuration for MAC address•Single 25MHz reference clock for both PHY and MAC •HBM ESD Rating 6kVPower Modes, Power Supplies, and Packaging •Single 3.3V power supply with options for 1.8V, 2.5V and 3.3V VDD I/O•Built-in integrated 3.3V or 2.5V to 1.8V low noise regulator (LDO) for core and analog blocks •Enhanced power management feature with energy detect mode and soft power-down mode to ensurelow-power dissipation during device idle periodsComprehensive LED indicator support for link, activity and 10/100 speed (2 LEDs) - User programmable •Low-power CMOS design•Commercial Temperature Range: 0°C to +70°C •Industrial Temperature Range: –40°C to +85°C •Flexible package options available in 48-pin (7mm × 7mm) LQFP KSZ8851-16MLL or 128-pinPQFP KSZ8851-16/32MQLAdditional FeaturesIn addition to offering all of the features of a Layer 2 controller, the KSZ8851-16MLL offers:•Flexible 8-bit and 16-bit generic host processor interfaces with same access time and single bustiming to any I/O registers and RX/TX FIFO buffers •Supports to add two-byte before frame header in order for IP frame content with double word boundary •Micrel LinkMD® cable diagnostic capabilities to determine cable length, diagnose faulty cables, anddetermine distance to fault•Wake-on-LAN functionality– Incorporates Magic Packet™, wake-up frame, network link state, and detection of energy signaltechnology•HP Auto MDI-X™ crossover with disable/enable option •Ability to transmit and receive frames up to 2000 bytes Network Features•10BASE-T and 100BASE-TX physical layer support •Auto-negotiation: 10/100 Mbps full and half duplex •Adaptive equalizer•Baseline wander correctionApplications•Video/Audio Distribution Systems•High-end Cable, Satellite, and IP set-top boxes •Video over IP and IPTV•Voice over IP (VoIP) and Analog Telephone Adapters (ATA)•Industrial Control in Latency Critical Applications •Home Base Station with Ethernet Connection •Industrial Control Sensor Devices (Temperature, Pressure, Levels, and Valves)•Security, Motion Control and Surveillance Cameras •In-vehicle Diagnostics (OBD) & software download Markets•Fast Ethernet•Embedded Ethernet•Industrial Ethernet•Embedded Systems•Automotive EthernetOrdering InformationPart Number Temperature Range Package Lead Finish KSZ8851-16MLL 0°C to 70°C 48-Pin LQFP Pb-Free KSZ8851-16MLLI –40°C to +85°C 48-Pin LQFP Pb-Free KSZ8851-16MLLU(Automotive AEC-Q100 qualified)–40°C to +85°C 48-Pin LQFP Pb-Free KSZ8851-16MLL-Eval Evaluation Board for the KSZ8851-16MLLRevision HistoryRevision Date Summary of Changes1.0 06/30/2008 First released Information.1.1 2/13/2009 Improved EDS Rating up to 6KV, revised Ordering Information and Updated Table content and description.2.0 8/31/2009 Change revision ID from “0” to “1” in CIDER (0xc0) register. Update pins 8, 14 and 29 description for 1.8V VDD_IO supply. To add the command write (CMD=1) address index register in order for software to read back the CMD register value. To enable software read or write external EEPROM.2.104/30/2012 In 16-bit bus mode, the SD1 bit must set to “1” when CMD = 1 during DMA access. Remove auto-enqueue function, add the reset circuit. Update the description for the register PMECR Bits [1,0]. Add KSZ8851MLLU Automotive part. Add the description for the register TXCR bit 7. Update read/write timing diagram for Asynchronous Cycle. Add power sequence descriptions in the reset timing section.2.203/04/2014 Remove auto-enqueue function for transmit, Update the description for section of Asynchronous Interface. Update read/write timing diagram and table, add notes for timing table ,CIDER and RXFCTR registers. Update the defination for Register P1CR bit [9],P1MBCR bit [4] and RX/TX pair. Update the description in Half-Duplex Backpressure section. Change TTL to CMOS and updates min/max I/O voltage in different VDDIO.ContentsList of Figures (7)List of Tables (8)Pin Configuration (9)Pin Description (10)Pin for Strap-In Options (13)Functional Description (14)Functional Overview (14)Rx unused block disabled (14)Wake-up Packet (16)Physical Layer Transceiver (PHY) (17)Straight Cable (18)Crossover Cable (19)Access (21)Usage (21)Frame Queue (RXQ) Frame Format (29)EEPROM Interface (31)CPU Interface I/O Registers (33)I/O Registers (33)Internal I/O Registers Space Mapping (33)CIDER (37)0x887x (37)Reserved (38)Do Not Care (38)None (38)Register Map: MAC, PHY and QMU (39)Bit Type Definition (39)0x00 – 0x07: Reserved (39)Chip Configuration Register (0x08 – 0x09): CCR (39)0x0A – 0x0F: Reserved (39)Host MAC Address Registers: MARL, MARM and MARH (40)Host MAC Address Register Low (0x10 – 0x11): MARL (40)Host MAC Address Register Middle (0x12 – 0x13): MARM (40)Host MAC Address Register High (0x14 – 0x15): MARH (40)0x16 – 0x1F: Reserved (40)On-Chip Bus Control Register (0x20 – 0x21): OBCR (41)EEPROM Control Register (0x22 – 0x23): EEPCR (41)Memory BIST Info Register (0x24 – 0x25): MBIR (42)Global Reset Register (0x26 – 0x27): GRR (42)0x28 – 0x29: Reserved (42)Wakeup Frame Control Register (0x2A – 0x2B): WFCR (43)0x2C – 0x2F: Reserved (43)Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 (43)Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 (43)Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 (44)Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 (44)Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 (44)Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3 (44)0x3C – 0x3F: Reserved (44)Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 (45)Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 (45)Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 (45)Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3 (45)0x4C – 0x4F: Reserved (45)Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 (45)Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 (46)Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 (46)Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 (46)Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 (46)Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3 (46)0x5C – 0x5F: Reserved (46)Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 (46)Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 (47)Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 (47)Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 (47)Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 (47)Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3 (47)0x6C – 0x6F: Reserved (47)Transmit Control Register (0x70 – 0x71): TXCR (48)Transmit Status Register (0x72 – 0x73): TXSR (49)Receive Control Register 1 (0x74 – 0x75): RXCR1 (49)Receive Control Register 2 (0x76 – 0x77): RXCR2 (50)TXQ Memory Information Register (0x78 – 0x79): TXMIR (51)0x7A – 0x7B: Reserved (51)Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR (51)Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR (52)TXQ Command Register (0x80 – 0x81): TXQCR (52)RXQ Command Register (0x82 – 0x83): RXQCR (53)TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR (54)RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR (54)0x88 – 0x8B: Reserved (55)RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR (55)RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR (55)Interrupt Enable Register (0x90 – 0x91): IER (55)Interrupt Status Register (0x92 – 0x93): ISR (56)0x94 – 0x9B: Reserved (57)RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR (57)TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR (57)MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0 (58)MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1 (58)MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2 (58)MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3 (58)0xA8 – 0xAF: Reserved (58)Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR (58)Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR (59)Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR (59)0xB6 – 0xBF: Reserved (59)Chip ID and Enable Register (0xC0 – 0xC1): CIDER (59)0xC2 – 0xC5: Reserved (59)0xCA – 0xCF: Reserved (60)Indirect Access Data Low Register (0xD0 – 0xD1): IADLR (60)Indirect Access Data High Register (0xD2 – 0xD3): IADHR (60)Power Management Event Control Register (0xD4 – 0xD5): PMECR (61)Go-Sleep and Wake-Up Time Register (0xD6 – 0xD7): GSWUTR (62)PHY Reset Register (0xD8 – 0xD9): PHYRR (62)0xDA – 0xDF: Reserved (62)0xE0 – 0xE3: Reserved (62)PHY 1 MII-Register Basic Control Register (0xE4 – 0xE5): P1MBCR (63)PHY 1 MII-Register Basic Status Register (0xE6 – 0xE7): P1MBSR (64)PHY 1 PHY ID Low Register (0xE8 – 0xE9): PHY1ILR (64)PHY 1 PHY ID High Register (0xEA – 0xEB): PHY1IHR (64)PHY 1 Auto-Negotiation Advertisement Register (0xEC – 0xED): P1ANAR (65)PHY 1 Auto-Negotiation Link Partner Ability Register (0xEE – 0xEF): P1ANLPR (66)0xF0 – 0xF3: Reserved (66)Port 1 PHY Special Control/Status, LinkMD (0xF4 – 0xF5): P1SCLMD (66)Port 1 Control Register (0xF6 – 0xF7): P1CR (67)Port 1 Status Register (0xF8 – 0xF9): P1SR (68)0xFA – 0xFF: Reserved (69)MIB (Management Information Base) Counters (70)Absolute Maximum Ratings (73)Operating Ratings (73)Electrical Characteristics (73)Timing Specifications (75)Asynchronous Read and Write Timing (Processor read and write) (75)Selection of Isolation Transformers (80)Selection of Reference Crystal (80)Package Information (81)Acronyms and Glossary (82)Figure 2. 48-Pin LQFP (9)Figure 3. Typical Straight Cable Connection (18)Figure 4. Typical Crossover Cable Connection (19)Figure 5. Auto Negotiation And Parallel Operation (20)Figure 6. Ksz8851-16mll 8-Bit And 16-Bit Data Bus Connections (25)Figure 8. Host Rx Single Or Multiple Frames In Auto-Dequeue Flow Diagram (30)Figure 9. Phy Port 1 Near-End (Remote) And Host Far-End (Local) Loopback Paths (32)Figure 10. Asynchronous Cycle (75)Figure 11. Auto Negotiation Timing (76)Figure 12. Reset Timing (77)Figure 13. Eeprom Read Cycle Timing Diagram (78)Figure 14. Recommended Reset Circuit (79)Figure 15. Recommended Circuit For Interfacing with Cpu/Fpga Reset (79)Table 1. Internal Function Blocks Status (14)Table 2. Mdi/Mdi-X Pin Definitions (18)Table 3. Address Filtering Scheme (23)Table 4. Bus Interface Unit Signal Grouping (24)Table 5. Frame Format For Transmit Queue (26)Table 6. Transmit Control Word Bit Fields (26)Table 7. Transmit Byte Count Format (27)Table 8. Registers Setting For Transmit Function Block (27)Table 9. Frame Format For Receive Queue (29)Table 10. Registers Setting For Receive Function Block (29)Table 11. Ksz8851-16mll Eeprom Format (31)Table 12. Format Of Mib Counters (70)Table 13. Port 1 Mib Counters Indirect Memory Offsets (71)Table 14. Asynchronous Cycle Timing Parameters (75)Table 15. Auto Negotiation Timing Parameters (76)Table 16. Reset Timing Parameters (77)Table 17. Eeprom Timing Parameters (78)Table 18. Transformer Selection Criteria (80)Table 19. Qualified Single Port Magnetics (80)Table 20. Typical Reference Crystal Characteristics (80)Figure 2. 48-Pin LQFPPin Number Pin Name Type Pin Function1 P1LED1 IPU/O Programmable LED output to indicate port activity/status.LED is ON when output is LOW; LED is OFF when output is HIGH.Port 1 LED indicators1 defined as follows:Chip Global Control Register: CGCR bit [9]0 (Default) 1P1LED1 100BT ACTP1LED0 LINK/ACT LINK1. Link = LED On; Activity = LED Blink; Link/Act = LED On/Blink;Speed = LED On (100BASE-T); LED Off (10BASE-T)Config Mode: The P1LED1 pull-up/pull-down value is latched as 16/8-bit mode during power-up / reset. See “Strapping Options” section for details2 P1LED0 OPU3 PME OPU Power Management Event (default active low): It is asserted (low or high depends on polarity set in PMECR register) when one of the wake-on-LAN events is detected by KSZ8851-16MLL. The KSZ8851-16MLL is requesting the system to wake up from low power mode.4 INTRN OPU Interrupt: An active low signal to host CPU to indicate an interrupt status bit is set, this pin need an external 4.7K pull-up resistor.5 RDN IPU Read Strobe NotAsynchronous read strobe, active low to indicate read cycle.6 WRN IPU Write Strobe NotAsynchronous write strobe, active low to indicate write cycle.7 DGND GND Digital ground8 VDD_CO1.8 P 1.8V regulator output . This 1.8V output pin provides power to pins 14 (VDD_A1.8) and 29 (VDD_D1.8) for core VDD supply.If VDD_IO is set for 1.8V then this pin should be left floating, pins 14 (VDD_A1.8) and 29 (VDD_D1.8) will be sourced by the external 1.8V supply that is tied to pins 27, 38 and 46 (VDD_IO) with appropriate filtering.9 EED_IO IPD/O In/Out Data from/to external EEPROM.Config Mode: The pull-up/pull-down value is latched as with/without EEPROM during power-up / reset. See “Strapping Options” section for details10 EESK IPD/O EEPROM Serial ClockA 4µs (OBCR[1:0]=11 on-chip bus speed @ 25MHz) or 800ns (OBCR[1:0]=00 on-chip bus speed @ 125MHz) serial output clock cycle to load configuration data from the serial EEPROM.Config Mode: The pull-up/pull-down value is latched as big/little endian mode during power-up / reset. See “Strapping Options” section for details11 CMD IPD Command TypeThis command input decides the SD[15:0] shared data bus access information.When command input is low, the access of shared data bus is for data access in 16-bit mode shared data bus SD[15:0] or in 8-bit mode shared data bus SD[7:0].When command input is high, the access of shared data bus is for address A[7:2] access at shared data bus SD[7:2], byte enable BE[3:0] at SD[15:12] and the SD[11:8] is “Do Not Care” in 16-bit mode. It is for address A[7:0] access at SD[7:0] in 8-bit mode.Pin Number Pin Name Type Pin Function12 CSN IPU Chip Select NotChip select for the shared data bus access enable, active Low.13 AGND GND Analog ground14 VDD_A1.8 P 1.8V analog power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46 (VDD_IO) with appropriate filtering.15 EECS OPD EEPROM Chip SelectThis signal is used to select an external EEPROM device.16 RXP1 I/O Port 1 physical receive signal (+ differential).17 RXM1 I/O Port 1 physical receive signal (– differential).18 AGND GND Analog ground.19 TXP1 I/O Port 1 physical transmit signal (+ differential).20 TXM1 I/O Port 1 physical transmit signal (– differential).21 VDD_A3.3 P 3.3V analog VDD input power supply with well decoupling capacitors.22 ISET O Set physical transmits output current.Pull-down this pin with a 3.01K 1% resistor to ground.23 RSTN IPU Reset NotHardware reset pin (active Low). This reset input is required minimum of 10ms low after stable supply voltage 3.3V.24 X1 I 25MHz crystal or oscillator clock connection.Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a 3.3V tolerant oscillator and X2 is a no connect.Note: Clock requirement is ±50ppm for either crystal or oscillator.25 X2 O26 DGND GND Digital ground27 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.28 DGND GND Digital ground29 VDD_D1.8 P 1.8V digital power supply from VDD_CO1.8 (pin 8) with appropriate filtering. If VDD_IO is 1.8V, this pin must be supplied power from the same source as pins 27, 38 and 46 (VDD_IO) with appropriate filtering.30 SD15 I/O (PD) Shared Data Bus bit 15. Data D15 access when CMD=0. Byte Enable 3 at double-word boundary access (BE3, 4th byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.31 SD14 I/O (PD) Shared Data Bus bit 14. Data D14 access when CMD=0. Byte Enable 2 at double-word boundary access (BE2, 3rd byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.32 SD13 I/O (PD) Shared Data Bus bit 13. Data D13 access when CMD=0. Byte Enable 1 at double-word boundary access (BE1, 2nd byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.33 SD12 I/O (PD) Shared Data Bus bit 12. Data D12 access when CMD=0. Byte Enable 0 at double-word boundary access (BE0, 1st byte enable and active high) in 16-bit mode when CMD=1. This pin must be tied to GND in 8-bit bus mode.34 SD11 I/O (PD) Shared Data Bus bit 11. Data D11 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode.35 SD10 I/O (PD) Shared Data Bus bit 10. Data D10 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode.Pin Number Pin Name Type Pin Function36 SD9 I/O (PD) Shared Data Bus bit 9. Data D9 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode.37 DGND GND Digital ground38 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.39 SD8 I/O (PD) Shared Data Bus bit 8. Data D8 access when CMD=0. Do Not Care when CMD=1. This pin must be tied to GND in 8-bit bus mode.40 SD7 I/O (PD) Shared Data Bus bit 7. Data D7 access when CMD=0. Address A7 access when CMD=1.41 SD6 I/O (PD) Shared Data Bus bit 6. Data D6 access when CMD=0. Address A6 access when CMD=1.42 SD5 I/O (PD) Shared Data Bus bit 5. Data D5 access when CMD=0. Address A5 access when CMD=1.43 SD4 I/O (PD) Shared Data Bus bit 4. Data D4 access when CMD=0. Address A4 access when CMD=1.44 SD3 I/O (PD) Shared Data Bus bit 3. Data D3 access when CMD=0. Address A3 access when CMD=1.45 SD2 I/O (PD) Shared Data Bus bit 2. Data D2 access when CMD=0. Address A2 access when CMD=1.46 VDD_IO P 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors.47 SD1 I/O (PD) Shared Data Bus bit 1. Data D1 access when CMD=0. In 8-bit mode, this is address A1 access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1.48 SD0 I/O (PD) Shared Data Bus bit 0. Data D0 access when CMD=0. In 8-bit mode, this is address A0 access when CMD=1. In 16-bit mode, this is “Do Not Care” when CMD=1.Legend:P = Power supplyGND = GroundI/O = Bi-directionalI = InputO = Output.IPD = Input with internal pull-down (58K ±30%).IPU = Input with internal pull-up (58K ±30%).OPD = Output with internal pull-down (58K ±30%).OPU = Output with internal pull-up (58K ±30%).IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise. IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise. I/O (PD) = Input/Output with internal pull-down (58K ±30%).Pin for Strap-In OptionsPin Number Pin Name Type Pin Function1 P1LED1 IPU/O 8 or 16-bit bus mode select during power-up / reset: NC or Pull-up (default ) = 16-bit busPull-down = 8-bit busThis pin value is also latched into register CCR, bit 6/7.9 EED_IO IPD/O EEPROM select during power-up / reset:Pull-up = EEPROM presentNC or Pull-down (default ) = EEPROM not present This pin value is latched into register CCR, bit 9.10 EESK IPD/O Endian mode select during power-up / reset:Pull-up = Big EndianNC or Pull-down (default) = Little EndianThis pin value is latched into register CCR, bit 10.When this pin is no connect or tied to GND, the bit 11 (Endian mode selection) in RXFDPR register can be used to program either Little (bit11=0 default) Endian mode or Big (bit11=1) Endian mode.Note: IPU/O = Input with internal pull-up (58K ±30%) during power-up/reset; output pin otherwise.IPD/O = Input with internal pull-down (58K ±30%) during power-up/reset; output pin otherwise.Pin strap-ins are latched during power-up or reset.Functional DescriptionThe KSZ8851-16MLL is a single-chip Fast Ethernet MAC/PHY controller consisting of a 10/100 physical layer transceiver (PHY), a MAC, and a Bus Interface Unit (BIU) that controls the KSZ8851-16MLL via an 8-bit or 16-bit host bus interface. The KSZ8851-16MLL is fully compliant to IEEE802.3u standards.Functional OverviewPower ManagementThe KSZ8851-16MLL supports enhanced power management feature in low power state with energy detection to ensure low-power dissipation during device idle periods. There are four operation modes under the power management function which is controlled by two bits in PMECR (0xD4) register as shown below:PMECR[1:0] = 00 Normal Operation ModePMECR[1:0] = 01 Energy Detect ModePMECR[1:0] = 10 Soft Power-down modePMECR[1:0] = 11 Power-saving modeTable 1 indicates all internal function blocks status under four different power management operation modes.KSZ8851-16MLL Function BlocksPower Management Operation ModesNormal Mode Power-saving mode Energy Detect Mode Soft Power-Down ModeInternal PLL Clock Enabled Enabled Disabled DisabledTx/Rx PHY Enabled Rx unused block disabled Energy detect at Rx DisabledMAC Enabled Enabled Disabled DisabledHost Interface Enabled Enabled Disabled DisabledTable 1. Internal Function Blocks StatusNormal Operation ModeThis is the default setting bit[1:0]=00 in PMECR register after the chip power-up or hardware reset (pin 67). When KSZ8851-16MLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on and the host interface is ready for CPU read or write.During the normal operation mode, the host CPU can set the bit[1:0] in PMECR register to transit the current normal operation mode to any one of the other three power management operation modes.Energy Detect ModeThe energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8851-16MLL is not connected to an active link partner. For example, if cable is not present or it is connected to a powered down partner, the KSZ8851-16MLL can automatically enter to the low power state in energy detect mode. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851-16MLL can automatically power up to normal power state in energy detect mode.Energy detect mode consists of two states, normal power state and low power state. While in low power state, the KSZ8851-16MLL reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect mode is entered by setting bit[1:0]=01 in PMECR register. When the KSZ8851-16MLL is in this mode, it will monitor the cable energy. If there is no energy on the cable for a time longer than pre-configured value at bit[7:0] Go-Sleep time in GSWUTR register, KSZ8851-16MLL will go into a low power state. When KSZ8851-16MLL is in low power state, it will keep monitoring the cable energy. Once the energy is detected from the cable and is continuously presented for a time longer than pre-configured value at bit[15:8] Wake-Up time in GSWUTR register, the KSZ8851-16MLL will enter either the normal power state if the auto-wakeup enable bit[7] is set in PMECR register or the normal operation mode if both auto-wakeup enable bit[7] and wakeup to normal operation mode bit[6] are set in PMECR register.The KSZ8851-16MLL will also assert PME output pin if the corresponding enable bit[8] is set in PMECR (0xD4) register or generate interrupt to signal an energy detect event occurred if the corresponding enable bit[2] is set in IER (0x90) register. Once the power management unit detects the PME output asserted or interrupt active, it will power up the host CPU and issue a wakeup command which is a read cycle to read the Globe Reset Register (GRR at 0x26) to wake up the KSZ8851-16MLL from the low power state to the normal power state in case the auto-wakeup enable bit[7] is disabled. When KSZ8851-16MLL is at normal power state, it is able to transmit or receive packet from the cable.Soft Power-Down ModeThe soft power-down mode is entered by setting bit[1:0]=10 in PMECR register. When KSZ8851-16MLL is in this mode, all PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change, and the host interface is only used to wake-up this device from current soft power-down mode to normal operation mode.In order to go back the normal operation mode from this soft power-down mode, the only way to leave this mode is through a host wake-up command which the CPU issues to read the Globe Reset Register (GRR at 0x26).Power-Saving ModeThe power-saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit[1:0]=11 in PMECR register and bit [10]=1 in P1SCLMD register. When KSZ8851M is in this mode, all PLL clocks are enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by the far end to establish link, the KSZ8851M can automatically enabled the PHY power up to normal power state from power-saving mode.During this power-saving mode, the host CPU can program the bit[1:0] in PMECR register and set bit[10]=0 in P1SCLMD register to transit the current power-saving mode to any one of the other three power management operation modes. Wake-on-LANWake-up frame events are used to wake the system whenever meaningful data is presented to the system over the network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is pre-programmed by the policy owner or other software with information on how to identify wake frames from other network traffic. The KSZ8851-16MLL controller can be programmed to notify the host of the wake-up frame detection with the assertion of the interrupt signal (INTRN) or assertion of the power management event signal (PME).A wake-up event is a request for hardware and/or software external to the network device to put the system into a powered state (working).A wake-up signal is caused by:1. Detection of energy signal over a pre-configured value (bit 2 in ISR register)2. Detection of a linkup in the network link state (bit 3 in ISR register)3. Receipt of a Magic Packet (bit 4 in ISR register)4. Receipt of a network wake-up frame (bit 5 in ISR register)There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in their own way.Detection of EnergyThe energy is detected from the cable and is continuously presented for a time longer than pre-configured value, especially when this energy change may impact the level at which the system should re-enter to the normal power state. Detection of LinkupLink status wake events are useful to indicate a linkup in the network’s connectivity status.。
OptiX_OSN_8800_产品系统硬件系统、单板介绍
Page 14
OSN 8800 子架配置原则
主从子架网线连接介绍
（详细安装方法请参考《快速安装指南手册》）
8800和6800子架共柜的场景： • 上层8800子架为主子架，且只能是电层子 架（按照习惯是使用下层6800光层子架作为主子架，但
是8800 V1R1版本不支持6800作为主子架的场景。V1R2 版本可解决）
系统类单板如AUX、PIU、FAN、EFI2、EFI1、ATE等不能混插，固定槽位
TN51SCC：IU11、IU28
TN51PIU：IU39、IU40、IU45、IU46 Page 7
OSN 8800 系统类单板介绍
OSN 8800 I V1R2 版本通信接口区外观图
OSN 8800 I V100R001 版本不支持TN51AUX主备配置， 请在R1版本时单配AUX单 板，配置在41槽位，43槽位用假拉手条填充 OSN 8800 I V100R001 版本不支持STG、STI单板，V1R2版本开始支持
电层集中交叉槽位、交叉板1＋1备份 XCS-支持1.28T ODU2交叉、160G的ODU1交叉 XCH-支持1.28T ODU0/1/2+VC4交叉 XCM-支持1.28T ODU0/1/2+VC4、80G VC12交叉
Page 3
OSN 8800 I 型子架（单面）
槽位
工作
保护
32槽位，单槽位40G，1.28T-bit接入能力 1+1热备份单板有：
Page 15
机柜
OptiX OSN 6800直流配电盒PDU
分为A、B两部分 输入：A、B两区各有1路主、备-48V电源，负载分区供电 输出：A、B两区各对外提供6路输出电源，互为备份
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NOTE: Auto-Media(自动媒体), 即芯片可以自动识别出媒体为电口或光口
关于芯片内部寄存器的介绍. 请参考 Marvell 88E1340S/1340/1322 备支持三种速度下的 Auto-MDI/MDIX ，使安装更加方便降低安装成本. 支持用于诊断/测试的还回模式. 在 15×15 毫米 196 针 TFBGA 封装.
88E1340S/88E1340 操作模式: 4 个 SGMII 接电口的端口 4 个 QSGMII 接电口的端口 4 个 QSGMII 接 SGMII 的端口 4 个 QSGMII 接 电口/光口 自动媒体的端口 2 个 SGMII 接两个电口/光口 自动媒体的端口
Marvell PHY 88E1340S 韩大卫@吉林师范大学
88E1340S 千兆以太网 PHY(物理层)芯片. 88E1340S/88E1340/ 支持 10/100/1000 QSGMII(Quad-Serial Gigabit Media Independent Interface)接口. 支持 QSGMII 接口用于直连 MAC 芯片或 SWITCH 芯片. QSGMII 接口将 4 个速率为 1.25Gbps 的 SGMII 接口结合为一个速率为 5 Gbps 的差分信号. QSGMII 接口减少了接 MAC 接口的引脚数量, 降低了整体的功耗. QSGMII MAC 接口可以被当作铜轴网线(电口)或光纤(光口)使用. 88E1340S/88E1340 也可支持 SGMII 接口在接 MAC 的接口上, 用于一个 SGMII 接口接电口的应用. 88E1322 支持两个 SGMII 端口 接两个电口/光口 自动媒体的应用 88E1340S/40/22 集成了 MDI 接口的终端电阻器和电容器到 PHY 中.该电阻器的集成通过减少外部元件 的数量，简化了电路板布局和电路板的成本降低. 全新的 Marvell®校准电阻器计划将达到并超过 IEEE 80 2.3 回波损耗规格的精度要求。 88E1340S/40/22 完全兼容 IEEE 802.3 标准. 包括 PMD, PMA, PCS 子层. 执行 PAM3, 8B/10B,4B/5B, MLT-3, NRZI , Manchester 编码/解码, 数字时钟恢复, 数字自适应均衡器的接收 器的数据路径, 线发射器的脉冲整形的数字滤波, 自动协商等管理功能.