电源时序管理芯片ADM1184_cn

合集下载

esp32_ 硬件设计指南说明书

esp32_ 硬件设计指南说明书

ESP32硬件设计指南版本3.3乐鑫信息科技版权©2022关于本文档《ESP32硬件设计指南》主要提供了在使用ESP32系列产品进行电路设计和PCB布局时需注意的事项。

本文还简要介绍了ESP32系列产品的硬件信息,包括ESP32芯片、模组、开发板以及典型应用方案等。

文档版本请至乐鑫官网https:///zh-hans/support/download/documents下载最新版本文档。

修订历史请至文档最后页查看修订历史。

文档变更通知用户可以通过乐鑫官网订阅页面/zh-hans/subscribe订阅技术文档变更的电子邮件通知。

您需要更新订阅以接收有关新产品的文档通知。

证书下载用户可以通过乐鑫官网证书下载页面/zh-hans/certificates下载产品证书。

目录1产品概述12原理图设计2 2.1电源32.1.1数字电源32.1.2模拟电源52.1.3RTC电源5 2.2上电时序与复位62.2.1上电时序62.2.2复位6 2.3Flash(必选)及SRAM(可选)72.3.1SiP Flash及SiP PSRAM72.3.2外部Flash及片外RAM7 2.4时钟源72.4.1外部时钟参考(必选)82.4.2RTC时钟(可选)8 2.5射频(RF)9 2.6ADC9 2.7外置阻容10 2.8UART10 2.9SDIO11 2.10触摸传感器113版图布局12 3.1独立的ESP32模组的版图设计123.1.1版图设计通用要点123.1.2模组在底板上的位置摆放133.1.3电源143.1.4晶振163.1.5射频173.1.6Flash及PSRAM183.1.7外置阻容183.1.8UART183.1.9触摸传感器18 3.2ESP32作为从设备的版图设计20 3.3版图设计常见问题213.3.1为什么电源纹波并不大,但射频的TX性能很差?213.3.2为什么芯片发包时,电源纹波很小,但射频的TX性能不好?213.3.3为什么ESP32发包时,仪器测试到的power值比target power值要高很多或者低很多,且EVM比较差?213.3.4为什么芯片的TX性能没有问题,但RX的灵敏度不好?224开发硬件介绍235典型应用案例24 5.1ESP32智能音频平台245.1.1ESP32-LyraT音频开发板245.1.2ESP32-LyraTD-MSC音频开发板25 5.2ESP32触摸传感器方案—ESP32-Sense Kit26 5.3ESP-Mesh应用—ESP32-MeshKit27修订历史28插图1ESP32系列芯片参考设计原理图2 2四线3.3V内部flash核心电路图3 3VDD_SDIO电源管脚电路(1.8V)4 4VDD_SDIO电源管脚电路(3.3V)4 5VDD_SDIO电源管脚电路(外部电源供电)4 6ESP32系列芯片模拟电源5 7ESP32系列芯片RTC电源5 8ESP32芯片上电、复位时序图6 9ESP32晶振电路图8 10外置晶振电路图8 11外部激励信号电路图9 12ESP32射频匹配电路图9 13ESP32外置电容10 14ESP32串口11 15ESP32版图设计12 16ESP32模组在底板上的位置示意图13 17ESP32天线区域净空示意图14 18ESP32四层板电源设计15 19九宫格设计15 20ESP32两层板电源设计16 21ESP32晶振设计16 22ESP32四层板射频部分版图设计17 23ESP32两层板射频部分版图设计17 24ESP32Flash及PSRAM版图设计18 25ESP32UART设计18 26典型的触摸传感器应用19 27电极图形要求19 28传感器布局布线20 29PAD/TV Box平面位置规划框架20 30ESP32-LyraT俯视图24 31ESP32-LyraT仰视图25 32ESP32-LyraTD-MSC外观图26 33ESP32-Sense Kit开发套件26 34ESP32-MeshKit-Light灯27 35ESP32-MeshKit-Sense开发板271.产品概述ESP32是集成2.4GHz Wi-Fi和蓝牙双模的单芯片方案,采用台积电(TSMC)低功耗40纳米工艺,具有超高的射频性能、稳定性、通用性和可靠性,以及超低的功耗,满足不同的功耗需求,适用于各种应用场景。

矽力杰产品选型_恒佳兴电子专业电源IC

矽力杰产品选型_恒佳兴电子专业电源IC

Single output step down (Buck) Converter Vin max < 7VSY8018A 2.5 5.5 0.45 / 0.6 ±2% 1.5 400/200 √Ultra Low Quiescent Current DFN2x2-8 SY8030L 2.5 5.5 0.6 2.25 0.6 ±1.5% 50 300/200 DFN2x2-6 SY8078B 1.85 5.5 0.6 3 0.4 ±2% 40 350/250 DFN1.45x1-6 SY8010 2.5 5.5 1 1.5 0.6 ±1.5% 50 200/150 DFN2x2-6 SY8011A 2.5 5.5 1 1.5 0.6 ±2% 40 230/150 DFN1.5x1.5-6 SY8061A 2.5 5.5 1 1.5 0.6 ±2% 60 260/170 Auto Discharge DFN2x2-6 SY8065L 2.5 5.5 1 1.5 0.6 ±2% 90 250/200 √SOT 23-6 SY8071 2.5 5.5 1 2 0.6 ±2% 40 260/170 SOT 23-5 SY8075 2.5 6.5 1 1.5 0.6 ±2% 40 260/170 DFN2x2-6 SY8077 2.5 6.5 1 1.5 0.6 ±2% 40 260/170 SOT 23-5 SY8080 2.5 5.5 1 3 0.6 ±2% 40 270/160 SOT 23-5SY8081 2.5 5.51 2.5 0.6 ±2%40230/150 Output auto discharge DFN1.5×1.5-6SY8011B 2.5 5.5 1.5 1.5 0.6 ±2%60210/130 DFN1.5x1.5-6SY8030 2.5 5.5 1.5 2.25 0.6 ±1.5%50200/150 Ext Mode DFN2x2-6 SY8002B 2.7 5.5 1.5 1 0.6 ±2% / 110/80 √Latch off protection SOT 23-6SY8002E 2.7 5.5 2 1 0.6 ±2% / 110/80 √Force PWM SOT 23-6SY8003L 2.7 5.5 2 1 0.6 ±2% 55 120/90 √DFN2x2-8Single output step down (Buck) Converter Vin max < 7V±2%SY8089 SOT 23-52.7 5.5 2 1 0.6 55 110/80 Latch off protectionSY8003C1 2.7 5.5 3 3 0.6 ±2% 55 110/80 √DFN2x2-8SY8823 2.5 5.5 3.5 2 0.6 ±1.5% 18 55/35 √QFN2x1.5-8SY8047 2.5 5.54 1.25 0.6 ±1.5%1875/55√QFN3x3-16SY8856 2.7 5.54 3 0.6 ±1.5%6035/15 √√DFN2x2-8√±1.5%SY8003F 2.7 5.5 3 1 0.6 / 110/80 DFN2x2-8 SY8079P 2.7 6.5 0.6 ±2% 55 125/95 Non latch off OVP SOT 23-6SY8032 2.7 5.5 2.5 0.6 ±2% 80 100/80 SOT 23-6SY8032E 2.7 5.5 2.5 0.6 ±2% 100/80 Force CCM SOT 23-6SY8003 2.7 5.5 0.6 ±2% 55 110/80 Latch SCP/OVP DFN2x2-8SY8003A 2.7 5.5 0.6 ±2% 55 110/80 Non-latch off protection DFN2x2-8SY8003C 2.7 5.5 0.6 ±2% 55 100/80 DFN2x2-8 SY8003E 2.7 5.5 0.6 ±2% 110/80 Force CCM DFN2x2-8 SY8043A 2.7 5.5 1.25 0.6 ±2% 18 75/55 DFN3x3-16 SY8047L 2.5 5.5 1.25 0.6 ±2% 18 75/55 QFN3x3-16 SY8859 2.7 5.5 0.6 ±1% 40 100/50 OVP/OCP/SCP/UVLO/OTP QFN1.5x1.5-7Single output step down (Buck) Converter Vin max < 7VPart Number Vin (min)(V)Vin (max)(V)Iout (max) (A) Fsw (MHz)Vout (min)( V)VoltageAcurracySY8824B 2.6 5.5 4 1.8 / ±1% SY8824C 2.6 5.5 4 1.8 / ±1% SY8035 2.7 5.5 5 1 0.6 ±1.5% SY8805A 3 5.5 5 1 0.6 ±1.5% SY8825 2.5 5.5 5 2 0.6 ±1.5% SY8876 2.7 6.5 6 1.2 0.6 ±1.5% SY8827K 2.5 5.5 6 2.4 ±1.5% SY8868 2.7 5.56 10.6 ±1% SY8099 2.7 5.5 6 1 0.6 ±1% SY8812 2.75 5.5 12 1 ±1%80 70/40Programmable Output Voltage: 0.7625Vto 1.55V in 12.5mV/step; Default 1.15Voutput voltage8015010018606550408070/4050/4035/1555/3538/1528/1735/1530/1212/6PackageTSOT 23-8Programmable Output Voltage: 0.7625Vto 1.55V in 12.5mV steps; Default 1.05Voutput voltageTSOT 23-8EXT SS DFN3x3-10DFN2x2-8QFN2x1.5-8OCP/UVLO/OTP DFN2x2-8I2C Programmable Vout: 0.7125V~ 1.5V CSP1.56x1.96-20in 12.5mV steps, Addr: 1000001xCOT mode,max dutyHigh efficiencyP rogrammable Output Voltage: 0.6V to1.5V in 10mV stepsQFN2x2-10TSOT 23-6QFN3x3-12Dual output step down (Buck) Converter Vin max < 7VPart Number Vin(min)(V)Vin(max)(V)Iout(max)(A)Fsw (MHz) Vout (min)(V)VoltageAcurracyQuiescentCurrent(uA)MO SFET Ron H/L (m? ) Power GoodOutputFeature/ Special Function PackageSY8020 2.5 5.5 1A x2 1.5 0.6 ±2% 50 200/150 Individual EN DFN3x3-12 SY8831 2.5 5.5 1A x2 1.5 0.6 ±2% 45/55 260/180 Individual EN TSOT 23-8 SY8832 2.5 5.5 2A x2 2 0.6 ±2% 35/45 125/100 Individual EN TSOT 23-8 SY8024 3 5.5 3A x2 1 0.6 ±2% 80 105/85 Individual EN DFN3x3-12 SY8821 2.5 5.5 1A/1.5A 2 0.6 ±2% 45 125/100 Individual EN DFN2x1.5-8Single output step down (Buck) Converter, Vin max > 7VuiescentOriginal Part Number Vin(min)(V)Vin(max)(V)Iout(max)(A)Fsw (MHz) Vout( imn)(V)Fixed O utputVoltage(V)VoltageAcurracyCurrent (uA)MOSFET(RonH/L) (m ? )Power oGodOutputFeature/ Special Function PackageSY8290 5 40 0.3 2 0.6 ±2.0% 160 2000/- SOT 23-6 SY8200 6 24 0.6 0.5 0.6 ±2% 400 420/200 SOT 23-6 SY8401 4.5 50 0.8 1.2 0.6 ±1.0% 150 700/- SOT 23-6SY8201 4.527 1 0.5 0.6 ±2%400350/150 SOT 23-6SY8201C 4.527 1 1.15 0.6 ±2%400350/150 Force CCM SOT 23-6SY85017 100 1 0.2~1MHz 1.2 ±2.0%400500/240 Programmable Switching Frequency SO8ESY8291 5 40 1.2 0.8 0.6 ±2.0% 160 180/- SOT 23-6 SY8502 7 100 1.8 0.2~1MHz 1.2 ±2.0% 400 500/240 Programmable Switching Frequency SO8ESingle output step down (Buck) Converter, Vin max > 7VVin(min) Vin(max) Iout(max) Fsw Vout(min) Voltage Quiescent MO SFET(Ron Power GoodPart Number(V) (V) Iout((m A)ax)(MHz) (V) Acurracy Current (uA) H/L) (m ? ) O utputFeature/ Special Function PackageSY8121 4.5 18 2 1 0.6 ±2% 400 170/160 SOT 23-6/ DFN2x2-6 SY8121B 4.35 18 2 1.2 0.6 ±2% 170/160 1.2MHz, FCCM SOT 23-6SY8120B1 4.5 18 2 0.5 0.6 ±2% 400 130/120 SOT 23-6SY8121C 4.5 18 2 1.2 0.6 ±2% 400 130/120 SOT 23-6SY8222 4.5 23 2 0.5 0.6 ±1.5% 400 150/110 √EXT SS, Hic-cup SCP DFN3x3-10SY8292 5 40 2 0.8 0.6 ±2.0% 160 180/- SOT 23-6SY8113B 4.5 18 3 0.5 0.6 ±1.5% 100 80/40 Hic-cup SCP TSOT 23-6SY8113C 4.518 3 1 0.6 ±1.5%10080/40 Hic-cup SCP TSOT 23-6SY8113D 4.5 18 3 0.5 0.6 ±1.5% 100 80/40 √Hic-cup SCP, EXT SS TSOT 23-8SY8113G 4.518 3 0.5 0.6 ±1.5%10080/40 Hic-cup SCP, FCCM TSOT 23-6SY8203A 4.523 3 1 0.6 ±1.5%400120/85 √EXT SS DFN3x3-10SY8223 4.523 3 0.5 0.6 ±1.5%400120/85 √EXT SS, Hic-cup SCP DFN3x3-10SY8253 4.5 23 3 0.5 0.6 ±1.5% 100 105/50 √EXT SS, Hic-cup SCP TSOT 23-8SY8303 4.5 40 3 0.5~2.5MHz 0.6 ±1.5% 18 70/110 TSOT 23-8 SY8293 5 40 3 0.8 0.6 ±2.0% 160 180/-SO8EPart Number Vin(min)(V)Vin(max)(V)Iout(max)(A)Fsw (MHz) Vout(min)(V)VoltageAcurracyQuiescentCurrent (uA)MO SFET(Ron H/L)(m ? )Power Good OutputFeature/ Special Function PackageSY8502 7 85 1.2 0.2~0.5 1.2 ±2.0% / 500/240 Programmable Switching FrequencyRangeSO8ESY8120B1 4.5 18 2 0.5 0.6 ±2% 400 130/120 SOT 23-6SY8121 4.5 18 2 1 0.6 ±2% 400 170/160 SOT 23-6/ DFN2x2-6 SY8121C 4.5 18 2 1.2 0.6 ±2% 400 130/120 SOT 23-6SY8222 4.5 23 2 0.5 0.6 ±1.5% 400 150/110 √EXT SS, Hic-cup SCP DFN3x3-10SY8292 5 40 2 0.8 0.6 ±2.0% 160 180/- SOT 23-6SY8113B 4.5 18 3 0.5 0.6 ±1.5% 100 80/40 Hic-cup SCP TSOT 23-6SY8113C 4.5 18 3 1 0.6 ±1.5% 100 80/40 Hic-cup SCP TSOT 23-6SY8113D 4.5 18 3 0.5 0.6 ±1.5% 100 80/40 √Hic-cup SCP, EXT SS TSOT 23-8SY8113G 4.5 18 3 0.5 0.6 ±1.5% 100 80/40 Hic-cup SCP, FCCM TSOT 23-6SY8203A 4.5 23 3 1 0.6 ±1.5% 400 120/85 √EXT SS DFN3x3-10SY8223 4.5 23 3 0.5 0.6 ±1.5% 400 120/85 √EXT SS, Hic-cup SCP DFN3x3-10SY8253 4.523 3 0.5 0.6 ±1.5%100105/50 √EXT SS, Hic-cup SCP TSOT 23-8SY8303 4.5 40 3 0.5~2.5MHz 0.6 ±1.5% 18 70/110 TSOT 23-8SY82935 40 3 0.8 0.6 ±2.0%160180/- SO8ESY8113H 4.5 18 3 0.5 0.6 ±1.5% 160 80/40 Programmable soft-start time TSOT 23-8±1.5%SY8104A4.518 4 0.5 0.6±1.5%100 50/30Instant PWM architectureSY8105 4.5 18 5 0.5 0.6±1.5%100 50/30SY8205 4.5 30 5 0.5 0.6±1.5%200 70/40√EXT SSSY8105A 4.5 18 5 0.5 0.6±1.5%100 40/20Instant PWM architectureSY8366H 4 28 6 0.8 0.6±1.5%100 40/20√Hic-cup SCP, 12A Peak current capability,programmable output current limitSY8286A 4 23 60.6 0.6 ±1.0% 12038/19 √SY8366K428 6 0.50.6±1.5%10040/20√Hic-cup SCP,6A continuous/12A peakoutput current capabilitySY8368A42880.80.6±1%100 20/10√Hic-cup SCP, 16A Peak current capability,programmable output current limitSY8288A 4 23 8 0.5 0.6 ±1.0% 80 30/10SY8288 4 23 8 0.5 0.6 ±1.0%8030/10SY8288C5.52380.60.6±1.5%10822/11√OVP/OCPSY8210A 4 28 10 0.6 0.6±1.5%300 25/8√Mem o ry power, 10A VDDQ/1A VTT LDO, 16A Peak Current capability, Latch offUVP/OVP, Over temperature alertSY8204 4.5 30 40.50.620080/50EXT SSPackageTSOT 23-6SO8ETSOT 23-6TSOT 23-6DFN3x4-12TSOT 23-6QFN3x3-12QFN3x3-20QFN3x3-12QFN3x3-12QFN3x3-20 QFN3x3-20QFN3x3-20QFN4x3-19Part Number Vin(min)(V)Vin(max)(V)Iout(max)(A)Fsw (MHz) Vout(min)(V) Voltage AcurracyQuiescent Current (uA)MO SFET(Ron H/L) (m ? ) Power Good OutputFeature/ Special Function Package SY8182 4 18 12 0.2~1MHz 0.6 ±1.0%18/6 √QFN4x4-20SY8182L 4.5 18 12 0.2~1MHz0.6 ±1.0% 500 18/6 √ Hic-cup SCP/OVPQFN4x4-24 SY8186418160.50.6±1.5%1507.5/2.5√Hic-cup SCP, programmble outputQFN4x4-11current limitPart NumberVin(min)(V)Vin(max)(V)Ilim (A)Fsw (MHz)Vout(max)(V)Sync BoostFixed O utputVoltage (V) Acu F r B ra /c y AcurracyInput Q uiescent Current (uA)Q uiescent current from output (uA)MO SFET Ro n (L/S) (m ? )Feature/ Special Function PackageSY7060L 0.7 5 0.2 / 5.25 Y /0.5V ±3% 0.518450/800SOT-363SY7070 0.7 5 0.35 / / Y 3.3 /0.5 5.5 500/700Bypass function @ shutdown SOT 23-5SY7070A 0.7 5 0.35 / / Y 3 / 0.5 5.5 500/700SOT 23-5SY7071 0.7 5 0.35 / 5.25 Y /1.0V ±3%0.5 5 500/700 Pass-through function @ shutdown SOT-363SY7071A 0.7 5 0.35 / / Y 5 / 0.5 7 400/500Pass-through function @ shutdown SOT-363SY7060 0.7 5 0.4 / 5.25 Y /0.5V ±3% 0.5 18 450/800SOT-363SY7080 0.9 4 1.8 1.2 4 Y / 1.2V ±3%65 / 90/200 Output Disconnect @Shutdown SOT 23-6Single output step Up (Boost) Converter (Low V oltage)Part NumberVin(min)(V)Vin(max)(V)Ilim (A)Fsw (MHz)Vout(max)(V)Sync BoostFixed O utput Voltage (V)Acu F rr B a /c y Acurracy InputQuiescent Current (uA) Quies cent current from output (uA) MOSFET Ron(L/S) (m ?) Feature/ Special Function PackageSY7063 1.8 5.25 3 0.5 5.5 Y / 1.2V ±1.5% 102736/40Output Disconnect @Shutdown QFN2x2-10SY7069 2.5 5.5 3 1 5.5 Y / 1.2V±1.5% 8 32 50/90TSOT 23-6SY7088 2.3 5 3 1 5.5 Y / 1.2V ±1.5% 2 30 70/85DFN2x3-8SY7088E 2.3 5 3 1 5.5 Y / 1.2V ±1.5% / / 70/85DFN2x3-8SY7065 1.8 5.25 5 0.5 5.5 Y / 1.2V ±1.5% 10 27 20/40 Auto output discharge function QFN2x2-10SY7065A 1.8 5.25 5 0.5 5.5 Y / 1.2V ±1.5% 10 27 20/40No output discharge function QFN2x2-10SY7076 2 5.5 6 0.5 5.5 Y / 1.2V ±1.5% 10 27 20/40QFN2x2-10SY7066 1.8 5.25 6 0.5 5.5 Y / 1.2V ±1.5% 10 27 20/40 Auto output discharge function QFN2x2-10SY7066B 1.8 5.25 6 0.5 5.5 Y / 1.2V ±1.5%10 27 20/40 Selectable Forced PWM mode QFN2x2-10Single output step Up (Boost) Converter (Low V oltage)SY9701A 2.6 5.5 1.2 1 5.5 0.6V ±1.5% 60 100/100 Output Disconnect @Shutdown DFN3x3-14Single output step Up (Boost) Converter (High Voltage)PackagePart NumberVin(min)(V)Vin(max)(V)Ilim (A)Fsw (MHz) Vout (max) (V) Sync BoostFB/ AcurracyInput Q uiescent Current (uA) MO SFET (RonMain/Rectified)(m? )Disconnect FET Ron ( m ?) Power Good OutputFeature/ Special FunctionSY7208C 3 25 0.6 1 25 N0.6V ±2%100 150/-Int SS/CompSOT 23-6SY7152A 3 8 2 1 16 N0.6V ±2%100 130/-Int SS/Comp SOT 23-6SY7208L 3 25 2 1 25 N0.6V ±2%100 150/-Int SS/Comp SOT 23-6SY7302 3 33 2 1 33 N0.6V ±2% 100 200/-Int SS/Comp SOT 23-6SY7388 3.5 30 2 0.85 30 N 1V ±2%150 200/-Accurate input current limit SOT 23-6SY7102 2 6 2.5 1 6 N0.6V ±2% 200 120/-Int SS/Comp SOT 23-6SY7801 2.5 5.5 2.5 1 / N 0.6V ±2%200 120/-Int SS, with 2A 80m? Load Switch DFN3x3-12SY7104A2 6 4 1 6 N0.6V ±2% 100 90/-Int SS/Comp DFN3x3-10SY7304 3334133N 0.6V ±2%100120/-QFN3x3-10SY7205 8.6 15.9 4.5 0.5 16 N1.25V±1.5% 120 75/-Adjustable soft-start time, OVP DFN3x3-10SY7982 3 9 6 1 13 Y 1V ±2% 600 80/4040√True shutdown QFN3x3-16SY7219 3 5.5 9 / 36 N 1.25V ±2%350 65/-EXT Comp DFN3x3-10 SY721531615/18Y1V ±1.5% 22016/1818√Int SS, OVP/SCP/ True shutdown ProgrammableSwitching Frequency: 0.2~1MHz QFN4x4-18SY7215A31615/18Y 1V ±1.5%2309/1212√Int SS, OVP/SCP/ True shutdown ProgrammableSwitching Frequency: 0.2~1MHzQFN4x4-181.23VInt SS; Adjustable current limit for optical module;SY7501B2.955.50.930.480N ±2%225 800/-Current limit indicator; Accurate high-side currentQFN3x3-16monitor; 320mW maximum output powerDC-DC PWM Controller (external Switch)Original Part Number Vin(min)(V)Vin(max)(V)Fsw (MHz)V(V R)EFFunction PackageSY7901 3 25 0.5 1 Current mode DC/DC controller targeted for Boost, Sepic, Flyback and Forward applications with DC Input Current Limit DFN3x3-10 SY7902A 3 25 0.3 1 Current mode DC/DC controller targeted for both Boost and Sepic applications with DC Output Current Limit SOP10 Power ModulePart Number Vin(min)(V)Vin(max)(V)Iout(max)(A)Fsw (MHz)Fixed O utputVoltage (V)Voltage Acurracy Q uiescent Current (uA) MOSFET (Ron H/L) (m? ) Integrated Inductor PackageSY98081 2.5 5.5 0.6 3 ±2% 40 230/150 √QFN2x1.5-8 SY98001 2.5 5.5 1.2 3 ±2% 40 230/150 √QFN2.5x2-8 SY98003 2.7 5.5 3 3 ±1.5% 60 35/15 √QFN3x3-10 SY98004 2.7 5.5 4 3 ±1.5% 60 35/15 √QFN3x3-10 SY98002 2.7 5.5 2 3 ±1.5% 60 20/40 √QFN3x3-10 SY98202 4.5 23 2 2 ±1.5% 100 50/105 √QFN3x3-10 SY98195 4.5 18 5 1.5 ±1.5% 15/50 √QFN5x5-20LDO RegulatorPart Number Vin(min)(V)Vin(max)(V)Vout(V)Iout(A)Dropout Voltage (mV) Function PackageSY6340 2.3 30 Output Voltage Adjustable 0.15 300 LDO Reg SOT23-5D FN2×2-6 SY6340B 3.6 30 3.3 0.05 100 LDO Reg SOT 23-5SY6345 4 40 Adjustable 0.3 300 LDO Reg SOT 23-5SY6301 1.6 5.5 Output Voltage Adjustable 1 0.32V at I OUT =1A, V OUT =1.5V0.18V at I OUT =1A, V OUT =2.8VLDO Reg DFN3×3-6SY6307B 0.8 5.5 Output Voltage Adjustable 0.5 90 LDO Reg DFN1.2x1.2-6 Protection SwitchPart Number Package Enabl eLogic O CP O VP No. ofChannelsVin(V) Vout(V) Iout(A) Rds(on) TUV/CBCertificateULCertificateSpecial FunctionSY6280A SOT 23-5 H Y N 1 2.4~5.5 2.4~5.5 0.4~2 63m? Programmable current limit, reverse blockingSY6281A SOT 23-5 L Y N 1 2.4~5.5 2.4~5.5 0.4~2 63m? Programmable current limit, reverse blockingSY6288A SOT 23-5 H Y N 1 2.5~5.5 2.5~5.5 0.6 80m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288B SOT 23-5 L Y N 1 2.5~5.5 2.5~5.5 0.6 80m? ? ? Output discharge at shutdown Reverse Blocking,OCB indicatorSY6811 CSP0.9x0.9-4 H N N 1 1.05~1.95 1.05~1.95 1 45m?@VIN=1.2V35m?@VIN=1.8V Auto output cap discharge function, utra low inputvoltageSY6819A SO8 H Y N 1 4.5~18 4.5~18 1.2 110m?@VIN=12V Programmable blanking t ime for DFF control, Default Off when EN ONSY6819 SO8 H Y Y 1 4.5~18 4.5~18 1.2 110m?@VIN=12V Programmable blanking t ime for DFF control,Default On when EN ONSY6288C20 SOT 23-5 H Y N 1 2.5~5.5 2.5~5.5 2 65m? ? ? Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288D20 SOT 23-5 L Y N1 2.5~5.5 2.5~5.5265m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorPart Number Package EnableLogicOCP OVPNo. ofChannelsVin(V) Vout(V) Iout(A) Rds(on)TUV/CBCertificateULCertificateSpecial FunctionSY6882A DFN2x2-8 H N Y 1 3~23 3~23 2 100m?Internal Fixed Over-Voltage Protection Threshold @7.1V, Thermal Shutdown Protection&Auto RecoverySY6882B DFN2x2-8 H N Y 1 3~23 3~23 2 100m? Programmable OVP Threshold Thermal Shutdown Protection& Auto RecoverySY6883 SOT 23-6 L N Y 1 3~23 3~23 2 100m? Programmable OVP Threshold Thermal Shutdown Protection& Auto RecoverSY6822 QFN2x2-10 L Y N 1 3~6.6 3~6 2 60m? Bidirectional Current Limit SwitchSY6288C7 SOT 23-5 H Y N 1 2.5~5.5 2.5~5.5 2.5 70m? √Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288D7 SOT 23-5 L Y N 1 2.5~5.5 2.5~5.5 2.5 70m? √Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288C5 MSOP8 H Y N 1 2.5~5.5 2.5~5.5 2.5 70m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288D5 MSOP8 L Y N 1 2.5~5.5 2.5~5.5 2.5 70m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288E1 SOT 23-5 H Y N 1 2.5~5.5 2.5~5.5 3 45m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288E2 SOT 23-5 L Y N 1 2.5~5.5 2.5~5.5 3 45m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288F1 SOT 23-6 H Y N 1 2.5~5.5 2.5~5.5 3 45m? √Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288F2 SOT 23-6 L Y N 1 2.5~5.5 2.5~5.5 3 45m? √Output discharge at shutdown Reverse Blocking,OCB indicatorSY6283A DFN1.2×1.6-4 H Y N 1 2.5~5.5 2.5~5.5 3 60m? Output discharge at shutdown Reverse Blocking SY6283 DFN1.2×1.6-4 H Y N 1 2.5~5.5 2.5~5.5 3 60m? Reverse blocking output, ultra low input voltage SY6813 6 ball CSP H N N 1 1.2~5.5 1.2~5.5 3 22m? Auto output cap discharge functionPart Number Package EnableLogicOCP OVPNo. ofChannelsVin(V) Vout(V) Iout(A) Rds(on)TUV/CBCertificateULCertificateSpecial FunctionSY6288D20 SOT 23-5 L Y N 1 2.5~5.5 2.5~5.5 2 65m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6882A DFN2x2-8 H N Y 1 3~23 3~23 2 100m?Internal Fixed Over-Voltage Protection Threshold @7.1V, Thermal Shutdown Protection&Auto RecoverySY6882B DFN2x2-8 H N Y 1 3~23 3~23 2 100m? Programmable OVP Threshold Thermal Shutdown Protection& Auto RecoverySY6883 SOT 23-6 L N Y 1 3~23 3~23 2 100m? Programmable OVP Threshold Thermal Shutdown Protection& Auto RecoverSY6822 QFN2x2-10 L Y N 1 3~6.6 3~6 2 60m? Bidirectional Current Limit SwitchSY6288C7 SOT 23-5 H Y N 1 2.5~5.5 2.5~5.5 2.5 70m? √Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288D7 SOT 23-5 L Y N 1 2.5~5.5 2.5~5.5 2.5 70m? √Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288C5 MSOP8 H Y N 1 2.5~5.5 2.5~5.5 2.5 70m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288D5 MSOP8 L Y N 1 2.5~5.5 2.5~5.5 2.5 70m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288E1 SOT 23-5 H Y N 1 2.5~5.5 2.5~5.5 3 45m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6288E2 SOT 23-5 L Y N 1 2.5~5.5 2.5~5.5 3 45m? √√Output discharge at shutdown Reverse Blocking,OCB indicatorSY6283A DFN1.2× 1.6-4 H Y N 1 2.5~5.5 2.5~5.5 3 60m? Output discharge at shutdown Reverse Blocking SY6283 DFN1.2× 1.6-4 H Y N 1 2.5~5.5 2.5~5.5 3 60m? Reverse blocking output, ultra low input voltage SY6813 6 ball CSP H N N 1 1.2~5.5 1.2~5.5 3 22m? Auto output cap discharge functionPart Number Package EnableLogicOCP OVPNo. ofChannelsVin(V) Vout(V) Iout(A) Rds(on)TUV/CBCertificateULCertificateSpecial FunctionSY6823 DFN2x2-8 H N N 2 0.6~5.5 0.6~5.5 4 28m? Programmable turn-on delay& ramp-up time,integrated OTP SCPSY6818 CSP1.73x1.73-12 H N Y 1 2.5~30 2.5~20 5 R PWPT =53m? (typ) Programmable OVP with Integrated Reverse Blocking FET, acurrate current level indicatorSY6874 DFN3x3-10 H Y Y 1 2.5~30 2.5~14 4 50m? Programmable softstart&current limit,3.3V/5V/12V selectable clamping outputSY6875A DFN3x3-10 H Y Y 1 2.5~30 2.5~14 5 40m? Programmable softstart&current limit,3.3V/5V/12V selectable clamping outputSY6875C DFN3x3-10 H Y Y 1 2.5~30 2.5-14 5 40m? Programmable softstart&current limit, 3.3V/5V/12V selectable clamping outputSY6875D DFN3x3-10 H Y Y 1 2.5~30 2.5-14 5 40m? Programmable softstart&current limit, 3.3V/5V/9V selectable clamping outputSY6875F DFN3x3-10 H Y Y 1 2.5~30 2.5-14 5 50m? Programmable softstart&current limit,3.3V/5V/12V selectable clamping outputSY6895A DFN3x3-10 H Y Y 1 2.5~12 2.5~6.5 5 40m? Fixed Current Limit, Prog.SS SY6895C DFN3x3-10 H Y Y 1 2.5~12 2.5~6.5 5 40m? Fixed Current Limit, Prog.SSSY6880C CSP1.8x2-12 H N Y 1 2.5~28 0~7 5A continous,8A peak38m?Fixed intenal OVP@6.8V, Reverse block, Surgeprotection up to 80VSY6880A CSP1.8x2-12 H N Y 1 2.5~28 0~7 5A continous,8A peak 38m?SY6829 CSP0.79x0.79-4 H N Y 1 2.5~6 0~7 1 96m? Precise clamping output voltageSwitching ChargerPart Number Function Vin (V)Max. ChargeCurrent (A)Fsw (MHz) Series Cells Cell Voltage Special Function PackageSY6903A Single-Cell Bi-directional Power Bank 4.5-5.5 2 0.5 Single Cell 4.2V adaptive current limit, 2.4A Boost QFN3x3-16 SY6923 Single-Cell with USB-OT G 4~6 1.55 3 Single Cell 3/5~4.44V Compliance with USB and USB OT G, MTK reference design CSP 1.93x2.05-20 SY6923D Single-Cell with USB-OT G 4~6 1.55 3 Single Cell 3.5~4.44V Compliance with USB and USB OTG CSP 1.93x2.05-20 SY6923D1 Single-Cell with USB-OT G 3.5- 4.44 1.25/1.55 3 Single Cell 4.2V Compliance with USB and USB OTG CSP 1.93x2.05-20SY6932 Multi-cell Charger Step Down Reg. 4~23 2 0.8 1-3 Cells 4.2VProg. Charge Current&Timer,Output Power PathManagementQFN4x4-16SY6952A Single-cell Charger Step Down Reg. 4~23 2 0.8 Single Cell 4.2V,4.35V Power Path Management and Adaptive Input Current Limit QFN4x4-16 SY6952C Single-cell Charger Step Down Reg. 4~23 2 0.8 Single Cell 4.2V, 4.35V Power Path Management and Adaptive Input Current Limit DFN3x3-12 SY6952B1 Single-cell Charger Step Down Reg. 4~23 2 0.8 Single Cell 4.1V, 4.4V Adaptive Input Current Limit SO8ESY6982C 2 cell Boost Li-Ion Baterry Charger 3.6~5.5 2 1 2 Cells 4.2V, 4.35V Prog. Charge Current&T imer,Adaptive Input Current Limit QFN3x3-16SY6982C1 2 cell Boost Li-Ion Baterry Charger 3.6~5.52 12 Cells 4.1V, 4.25V Prog. Charge Current&T imer,Adaptive Input Current Limit QFN3x3-16 SY6982D 2 cell Boost Li-Ion Baterry Charger 3.6~5.5 2 1 2 Cells 4.1V, 4.2V, 4.3V, 4.35V Prog. Charge Current&T imer,Adaptive Input Current Limit QFN3x3-16SY6982E2 cell Boost Li-Ion Baterry Charger 3.6~5.52 12 Cells 4.2V, 4.35VProg. Charge Current&T imer,Adaptive Input Current LimitQFN3x3-16SY6982E12 cell Boost Li-Ion Baterry Charger 3.6~5.52 12 Cells 4.25V, 4.4VProg. Charge Current&T imer,Adapter and BAT IN IndicatorQFN3x3-16SY6982F 2 cell Boost Li-Ion Baterry Charger 3~5.5 2 1 2 Cells 4.2V Prog. Charge Current&T imer,Adapter and BAT IN Indicator QFN3x3-16 SY6903 Single-Cell Bi-directional Power Bank 4.5~5.35 2 0.5 Single Cell 4.2V 3in1, Adaptive current limit, 2.4A Boost QFN3x3-16 SY6903B Single-Cell Bi-directional Power Bank 4.5~5.3520.5 Single Cell 4.35V 3in1, Adaptive current limit, 2.4A Boost QFN3x3-16Part Number Function Vin (V)Max. ChargeCurrent (A)Fsw (MHz) Series Cells Cell Voltage Special Function PackageSY6908 Single-Cell Bi-directional Power Bank 4.5~5.35 2 0.5 Single Cell 4.2V 3in1, Adaptive current limit, 2.5A Boost QFN3x3-16SY6908A Single-Cell Bi-directional Power Bank 4.5~5.5 2 0.5 Single Cell 4.2V 3in1, Adaptive current limit, 2.5A Boost QFN3x3-16 SY6908B Single-Cell Bi-directional Power Bank 4.5~5.35 2 0.5 Single Cell 4.35V 3in1, Adaptive current limit, 2.5A Boost QFN3x3-16 SY6908D Single-Cell Bi-directional Power Bank 4.5~5.35 2 0.5 Single Cell 4.2V 3in1, Adaptive current limit, >10000mAH BAT, 2.5A Boost QFN3x3-16 SY6908E Single-Cell Bi-directional Power Bank 4.5~5.35 2 0.5 Single Cell 4.35V 3in1, Adaptive current limit, >10000mAH BAT, 2.5A Boost QFN3x3-16 SY6918 Single-Cell Bi-directional Power Bank 4.5~5.35 2 0.5 Single Cell 4.2V,4.35V Prog. current limit, 18V input voltage surge QFN3x3-16 SY6918A Single-Cell Bi-directional Power Bank 4.5~5.35 2 0.5 Single Cell 4.2V,4.35V Prog. current limit, 18V input voltage surge QFN3x3-16SY6918B Single-Cell Bi-directional Power Bank 4.5-5.3520.5 Single Cell 4.2V, 4.35V Prog. current limit, 18V input voltage surge QFN3x3-16SY6990 Single-Cell Bi-directional Power Bank 4~13.5 5 0.5 Single Cell 4.1V,4.2V,4.25V,4.4VI2C controlled, USB Complianced, 5V/3A&12V/1.2A Boost QFN4x4-24SY6992 Single-Cell Bi-directional Power Bank 4~13.5 5 0.5, 0.3 Single Cell 4.1V,4.2V,4.25V,4.4V I2C controlled, USB Complianced, 5V/4A&12V/1.5A Boost QFN4x4-20SY6993 Single-Cell Bi-directional Power Bank 4~13.5 5 0.5, 0.3 Single Cell 4.1V,4.2V,4.25V,4.4VI2C controlled, USB Complianced, 5V/4A&12V/1.5A Boost QFN4x4-20 SY6935 High Current Step-down Charger 4~14 3.5 1 1-2 Cells 4.2V, 4.35V Adaptive input current limit, Blocking FET integrated QFN3x3-16 SY7994 Synchronous Boost converter with QC3.0 3~4.5 NA 0.3, 0.5 Single Cell NA QC3.0 Compliance QFN4x4-20Power Management I CsPart Number Vin(min)(V)Vin(max)(V)Num ber ofChannelsPackage Application Integrated FunctionSY8675 9.3 18 3 SO8E TV power system 1 synchronous buck, 1 sy cnh ronous buck, 1 load switchSY8670 8 25 6 QFN5X5-32 TV Power System 4-Channel Step-Down onCve rter, 2-Channel LDOSY8632A 4.5 18 3 QFN5x5-32 TCON Power System I2C controlled 3-channel Buck RegulatorsSY6401A 4 18 1 DFN3x3-10 SSD Programmable charging current Automatic bi-directional energy flowSY6402 2.7 16 1 QFN3x4-19 SSD Input-side current limit switch Bi-directional DC-DC Regulator wit disconnhe ct switch: Boost Charging Mode and Buck Discharging Mode SY8645 3.4 5.5 8 QFN5x5-32 POS 4 Buck Converter, 2 LDO, one MOS switch, one load switch&one voltage detector.SY7630 2.5 5.5 3 QFN4x4-24 Monitor/NB LCD Panel Power AVDD Boost, VGH/VGL charge pump, VCOM OPAMP, GPMSY7630B 2.3 5.5 3 QFN4x4-24 Monitor/NB LCD Panel Power AVDD Boost, VGH/VGL charge pump, VCOM OPAMP, GPMSY8671 9.1 14.7 6 QFN6X6-40 TV LCD Panel Power 1 AVDD Boost, 1 HAVDD Buck, 2 Buck, 1 VON Boost, 1 VOFF Buck-BoostSY8673 8 18 5 QFN7x7-48 TV LCD Panel Power AVDD Boost, VGH/VGL charge pump, VCOM OPAMP, GPM, DVDD, Gammar reference LDOSY7615 8 18 2 DFN3x3-10 wer supply and control for satellite set t Boost, LNB BlogSY7615A8 18 2 DFN3x3-10 LNB power supply and control for s at elliteset top boxesBoost, LNB BlogSY8631 2.5 5.5 6 QFN4x4-24 Camera module Step Down Buck Regulators,3 Low Dropout LDO and 1 Channel RESET OutputSY86304 20 3DFN3x3-12 Security CCD Camera power supply 2 Buck converters and 1 Boost converterSY86412 5 5QFN3x3-16 3D Glass 1 Boost output with analog switches for 3D glassesSY8660C 2.7 5.5 1 DFN3x3-14 U SB Powered Devices Buck converter with programmable current limit switchSY8689 4.5 18 3 QFN4x4-24 TV Power/USB Ports and Hubs/Set-Top Dual synchronous buck regulator and an N-channel back-to-back power MOSFET switch。

AD转换芯片介绍

AD转换芯片介绍
l???????ADS7816?12位高速微功率采样模数转换器
l???????ADS7812?低功耗串行12位采样模数转换器
l???????ADS7810?12位800kHz采样CMOS模数转换器
l???????ADS7800?12位3us采样模数转换器
l???????ADS574??兼容微处理器的采样CMOSA/D转换器?
l???????THS1007?10位6MSPS同步采样四路通道ADC;包含并行DSP/uPI/F通道自动扫描?
l???????ADS901??10位20MSPSADC,具有单端/差动输入、外部参考和可调节全范围?
l???????ADS900??10位20MSPSADC,具有单端/差动输入、内部基准和可调节全范围?
l???????ADS822?10位40MSPSADC,具有单端/差动输入、内/外基准和断电、引脚符合ADS823/6/8?
l???????ADS821?10位40MSPSADC,单端/差动输入具有内部基准和9.3位ENOB?
l???????ADS820?10位20MSPSADC,单端/差动输入具有内部基准和9.5位ENOB?
l???????TLC3545?14位200KSPSADC,具有串行输出、自动断电和伪差动输入?
l???????TLC3544?14位、5V、200KSPS、4通道单级性ADC
l???????TLC3541?14位200KSPSADC系列输出、自动断电、单端输入?
l???????THS1403?14位、3MSPSADC单通道、差动输入、DSP/uPIF、可编程增益放大器、内部S&H?
l???????TLC4541?16位200KSPSADC,具有串行输出、自动断电和单端输入

EG1182芯片数据手册说明书

EG1182芯片数据手册说明书

版本变更记录版本号日期描述V1.0 2013年04月12日EG1182数据手册初稿V1.1 2020年05月19日EG1182芯片2脚电容改成10uF目录1. 特性 (1)2. 描述 (1)3. 应用领域 (1)4. 引脚 (2)4.1 引脚定义 (2)4.2 引脚描述 (2)5. 结构框图 (3)6. 典型应用电路 (3)7. 电气特性 (5)7.1 极限参数 (5)7.2 典型参数 (6)8. 应用设计 (7)8.1Vin输入电容 (7)8.2Vcc储能电容 (7)8.3启动过程 (7)8.4振荡器CT电容的开关频率计算 (7)8.5输出峰值限流 (7)8.6输出短路保护 (8)8.7输出电感 (8)8.8续流二极管 (8)8.9输出电容 (8)8.10输出电压调节端(ADJ)设置 (8)9. 封装尺寸 (9)EG1182芯片数据手册V1.11. 特性⏹宽电压输入电压范围:20V至60V⏹外接元件少,无需外围补偿网络能达到稳定工作⏹保护功能:●过流保护●短路保护⏹外接一个电容可设置工作频率(10KHz-100KHz)⏹UVLO欠压锁定功能:●Vcc引脚端的开启电压6.5V●Vcc引脚端的关闭电压3.5V●UVLO迟滞电压为3V⏹无需外接启动电阻⏹内置高压功率管⏹可外部扩展高压功率管应用于输出大电流场合⏹外接一个小功率电阻可控制峰值电流⏹逐周限流控制⏹封装形式:ESOP-82. 描述EG1182是一款48V电池供电降压型DC-DC电源管理芯片,内部集成基准电源、振荡器、误差放大器、过热保护、限流保护、短路保护等功能,非常适合高压60V场合应用。

EG1182应用在电动车48V控制器系统中,能直接替代LM317、LM7815或电阻型降压线性稳压器,具有高效率,高可靠性等特性,能大大降低整体控制器的温度,使整个系统能够更可靠工作。

3. 应用领域⏹电动摩托车控制器⏹电动自行车控制器⏹高压模拟/数字系统⏹工业控制系统⏹电信48V电源系统⏹以太网P O E⏹便携式移动设备⏹逆变器系统4. 引脚4.1 引脚定义图4-1. EG1182管脚定义4.2 引脚描述5. 结构框图PK C图5-1. EG1182内部电路图6. 典型应用电路Vout=+15V≤350mA图6-1. EG1182典型应用电路图图6-2. EG1182 LED恒流350mA驱动7. 电气特性7.1 极限参数注:超出所列的极限参数可能导致芯片内部永久性损坏,在极限的条件长时间运行会影响芯片的可靠性。

CPU224CN介绍

CPU224CN介绍

CPU224CN介绍返回TOP CPU 224 CN 技术规范描述CPU 224 CN DC/DC/DC CPU 224 CN AC/DC/继电器物理特性尺寸(W X H X D) 重量功耗120.5 x 80 x 62 mm360g7 W120.5 x 80 x 62 mm410g10W存储器特性程序存储器在线程序编辑时非在线程序编辑时数据存储器装备(超级电容) (可选电池) 8192 bytes12288 bytes8192 bytes100小时/典型值(40°C时最少70小时)200天/典型值8192 bytes12288 bytes8192bytes100小时/典型值(40°C时最少70小时)200天/典型值I/O特性本机数字量输入本机数字量输出本机模拟量输入本机模拟量输出数字I/O映象区模拟I/O映象区允许最大的扩展I/O模块允许最大的智能模块脉冲捕捉输入高速计数器14 输入10 输出无无256 (128输入/128输出)64(32输入/32输出)7个模块7个模块146个14 输入10 输出无无256 (128输入/128输出)64(32输入/32输出)7个模块7个模块146个总数单相计数器两相计数器脉冲输出6,每个30KHz4,每个20KHz2个20KHz(仅限于DC输出)6,每个30KHz4,每个20KHz2个20KHz(仅限于DC输出)定时器总数1ms10ms100ms计数器总数内部存储器位掉电保持时间中断边沿中断模拟电位器布尔量运算执行时间时钟卡件选项256个4个16个236个256(由超级电容或电池备份)256(由超级电容或电池备份)112(存储在EEPROM)2个1ms分辨率4个上升沿和/或4个下降沿2个8位分辨率0.22us内置存储卡和电池卡256个4个16个236个256(由超级电容或电池备份)256(由超级电容或电池备份)112(存储在EEPROM)2个1ms分辨率4个上升沿和/或4个下降沿2个8位分辨率0.22us内置存储卡和电池卡接口PPI,DP/T波特率自由口波特率每段最大电缆长度最大站点数最大主站数点到点(PPI主站模式) MPI连接1个RS-485接口9.6,19.2和187.5kbaud1.2kbaud 至115.2kbaud使用隔离的中继器:187.5kbaud可达1000米,38.4kbaud可达1200米未使用隔离中继器:50米每段32个站,每个网络126个站32是(NETR / NETW)共4个,2个保留(1个给PG,1个给OP)1个RS-485接口9.6,19.2和187.5kbaud1.2kbaud 至115.2kbaud使用隔离的中继器:187.5kbaud可达1000米,38.4kbaud可达1200米未使用隔离中继器:50米每段32个站,每个网络126个站32是(NETR / NETW)共4个,2个保留(1个给PG,1个给OP)输入电源输入电压输入电流20.4 至28.8 VDC110mA (仅CPU,24 VDC)700mA (最大负载,24VDC)85 至264 VAC(47 至63Hz)60/30mA (仅CPU,120/240 VAC)200/100mA (最大负载,120/240 VAC)冲击电流隔离(现场与逻辑) 保持时间(掉电)保险(不可替换) 12A,28.8 VDC时不隔离10ms,24 VDC时3A,250V时慢速熔断20A ,264 VAC时1500 VAC20 / 80ms,120/240 VAC时2A,250V时慢速熔断传感器电压电流限定纹波噪声隔离(传感器与逻辑) L+ 减5V1.5A峰值,终端限定非破坏性来自输入电源非隔离20.4 至28.8 VDC1.5A峰值,终端限定非破坏性小于1 V峰分值非隔离本机集成数字量输入点数输入类型额定电压最大持续允许电压浪涌电压逻辑1信号(最小)逻辑0信号(最大)输入延迟连接2线接近开关传感器(Bero)允许漏电流最大隔离(现场与逻辑)光电隔离隔离组高速输入速率高速计数器逻辑1=15 – 30 VDC高速计数器逻辑1=15 – 26 VDC同时接通的输入电缆长度最大屏蔽非屏蔽14输入漏型/源型(IEC类型1/漏型)24V DC,4mA典型值时30V DC35V DC,0.5秒15V DC,2.5mA5V DC,1mA可选(0.2至12.8ms)1mA是500V AC1分钟见接线图20KHz(单相)10KHz(两相)30KHz(单相)20KHz(两相)所有500米(标准输入)50米(高速计数器输入)300米(标准输入)14输入漏型/源型(IEC类型1/漏型)24V DC,4mA典型值时30V DC35V DC,0.5秒15V DC,2.5mA5V DC,1mA可选(0.2至12.8ms)1mA是500V AC,1分钟见接线图20KHz(单相)10KHz(两相)30KHz(单相)20KHz(两相)所有500米(标准输入)50米(高速计数器输入)300米(标准输入)本机集成数字量输出点数输出类型额定电压电压范围10输出固态- MOSFET(源型)24V DC20.4至28.8V DC10输出干触点24V DC或250V AC5至30V DC或5至250V浪涌电流(最大)逻辑1(最小)逻辑0(最大)每点额定电流(最大) 每个公共端的额定电流(最大)漏电流(最大)灯负载(最大)感性嵌位电压接通电阻(接点)隔离光电隔离(现场到隔离) 逻辑到接点电阻(逻辑到接点)隔离组8A,100ms20V DC,最大电流0.1V DC,10KΩ 负载0.75A6 A10μA5 WL+ 减48V DC1W功耗0.3Ω典型值(0.6Ω最大值)500V AC,1分钟--见接线图AC5A,4s (10%工作率时)--2.0A10A-30W DC;200W AC-0.2 Ω(新的时候最大值)-1500V AC,1分钟100 MW见接线图延时(最大)断开到接通接通到断开切换脉冲频率(最大) 机械寿命周期触点寿命同时接通的输出两个输出并联电缆长度(最大) 屏蔽非屏蔽2μs(Q0.0, Q0.1),15μs(其它)10μs(Q0.0, Q0.1),130μs(其它)-20KHz(Q0.0和Q0.1)--55°C时,所有的输出(水平安装)45°C时,所有的输出(垂直安装)是,仅输出同组时500米150米--10ms1Hz10,000,000(无负载)100,000(额定负载)55°C时,所有的输出(水平安装)45°C时,所有的输出(垂直安装)否500米150米返回TOPCPU 224 CN DC/DC/DC 连接器端子图CPU 224 CN 尺寸图。

MAX1184ECM-TD中文资料

MAX1184ECM-TD中文资料

General DescriptionThe MAX1184 is a 3V, dual 10-bit analog-to-digital con-verter (ADC) featuring fully-differential wideband track-and-hold (T/H) inputs, driving two pipelined, 9-stage ADCs. The MAX1184 is optimized for low-power, high-dynamic performance applications in imaging, instru-mentation, and digital communication applications. This ADC operates from a single 2.7V to 3.6V supply, con-suming only 105mW while delivering a typical signal-to-noise ratio (SNR) of 59.5dB at an input frequency of 7.5MHz and a sampling rate of 20Msps. The T/H driven input stages incorporate 400MHz (-3dB) input amplifiers.The converters may also be operated with single-ended inputs. In addition to low operating power, the MAX1184features a 2.8mA sleep mode as well as a 1µA power-down mode to conserve power during idle periods.An internal 2.048V precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of the internal or an externally derived reference, if desired for applications requiring increased accuracy or a different input voltage range.The MAX1184 features parallel, CMOS-compatible three-state outputs. The digital output format is set to two’s complement or straight offset binary through a sin-gle control pin. The device provides for a separate out-put power supply of 1.7V to 3.6V for flexible interfacing.The MAX1184 is available in a 7mm x 7mm, 48-pin TQF P package, and is specified for the extended industrial (-40°C to +85°C) temperature range.Pin-compatible higher speed versions of the MAX1184are also available. See Table 2 at end of data sheet for a list of pin-compatible versions. Refer to the MAX1180data sheet for 105Msps, the MAX1181 data sheet for 80Msps, the MAX1182 data sheet for 65Msps, and the MAX1183 data sheet for 40Msps. In addition to these speed grades, this family includes a 20Msps multi-plexed output version (MAX1185), for which digital data is presented time-interleaved on a single, parallel 10-bit output port.ApplicationsHigh-Resolution Imaging I/Q Channel Digitization Multchannel IF Undersampling Instrumentation Video ApplicationFeatures♦Single 3V Operation♦Excellent Dynamic Performance:59.5dB SNR at f IN = 7.5MHz 74dB SFDR at f IN = 7.5MHz ♦Low Power:35mA (Normal Operation)2.8mA (Sleep Mode)1µA (Shutdown Mode)♦0.02dB Gain and 0.25°Phase Matching (typ)♦Wide ±1V P-P Differential Analog Input Voltage Range♦400MHz -3dB Input Bandwidth♦On-Chip 2.048V Precision Bandgap Reference ♦User-Selectable Output Format—Two’s Complement or Offset Binary♦48-Pin TQFP Package with Exposed Paddle for Improved Thermal Dissipation ♦Evaluation Kit AvailableMAX1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC withInternal Reference and Parallel Outputs________________________________________________________________Maxim Integrated Products1Pin Configuration19-2174; Rev 1; 7/06Ordering InformationFor pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .*EP = Exposed paddle.+Denotes lead-free package.M A X 1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel Outputs 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS(V DD = 3V, OV DD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through aStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.V DD , OVDD to GND...............................................-0.3V to +3.6V OGND to GND.......................................................-0.3V to +0.3V INA+, INA-, INB+, INB- to GND...............................-0.3V to V DD REFIN, REFOUT, REFP, REFN, CLK,COM to GND..........................................-0.3V to (V DD + 0.3V)OE , PD, SLEEP, T/B, D9A–D0A,D9B–D0B to OGND.............................-0.3V to (OV DD + 0.3V)Continuous Power Dissipation (T A = +70°C)48-Pin TQFP-EP (derate 30.4mW/°C above+70°C).......................................................................2430mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-60°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC withInternal Reference and Parallel Outputs_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS (continued)(V DD = 3V, OV DD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k Ωresistor, V IN = 2V P-P (differential with respect to COM), C L = 10pF at digital outputs (Note 1), f CLK = 20MHz, T A = T MIN to T MAX ,unless otherwise noted. Typical values are at T A = +25°C.) (Note 2)M A X 1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel Outputs 4_______________________________________________________________________________________ELECTRICAL CHARACTERISTICS (continued)(V DD = 3V, OV DD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a 10k Ωresistor, V IN = 2V P-P (differential with respect to. COM), C L = 10pF at digital outputs (Note 1), f CLK = 20MHz, T A = T MIN toMAX1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC withInternal Reference and Parallel Outputs_______________________________________________________________________________________5ELECTRICAL CHARACTERISTICS (continued)(V DD = 3V, OV DD = 2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through aNote 2:Specifications at ≥+25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.Note 3:SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scaleinput voltage range.Note 4:Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is6dB or better, if referenced to the two-tone envelope.Note 5:Digital outputs settle to V IH , V IL . Parameter guaranteed by design.Note 6:With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.M A X 1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel Outputs 6_______________________________________________________________________________________-100-80-90-60-70-40-50-30-10-200023415679810FFT PLOT CHA (DIFFERENTIAL INPUT,8192-POINT DATA RECORD)ANALOG INPUT FREQUENCY (MHz)A M P L I T U D E (d B )f CLK = 20.0006MHz f INA = 5.9743MHz f INB = 7.5344MHz A INA = -0.525dBFSHD3HD2CHA-100-80-90-60-70-40-50-30-10-200023415679810FFT PLOT CHB (DIFFERENTIAL INPUT,8192-POINT DATA RECORD)ANALOG INPUT FREQUENCY (MHz)A M P L I T U D E (d B )f CLK = 20.0006MHz f INA = 5.9743MHz f INB = 7.5244MHz A INB = -0.462dBFSHD3HD2CHB-100-80-90-60-70-40-50-30-10-200023*********FFT PLOT CHA (DIFFERENTIAL INPUT,8192-POINT DATA RECORD)ANALOG INPUT FREQUENCY (MHz)A M P L I T U D E (dB )-100-80-90-60-70-40-50-30-10-20023415679810FFT PLOT CHB (DIFFERENTIAL INPUT,8192-POINT DATA RECORD)ANALOG INPUT FREQUENCY (MHz)A M P L I T U D E (dB )f CLK = 20.0006MHz f INA = 7.5344MHz f INB = 11.9852MHz A INB = -0.471dBFSHD3HD2CHB-100-80-90-60-70-40-50-30-10-20004682101214181620TWO-TONE IMD PLOT DIFFERENTIAL INPUT, 8192-POINT DATA RECORDANALOG INPUT FREQUENCY (MHz)A M P L I T U D E (dB )57565958606101020304050SIGNAL-TO-NOISE RATIO vs.ANALOG INPUT FREQUENCYANALOG INPUT FREQUENCY (MHz)S N R (d B )61605958575601020304050SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCYANALOG INPUT FREQUENCY (MHz)S IN A D (d B )-73-75-77-71-67-69-65-63TOTAL HARMONIC DISTORTION vs.ANALOG INPUT FREQUENCYANALOG INPUT FREQUENCY (MHz)T H D(d B c )1020304050606472687680SPURIOUS-FREE DYNAMIC RANGE vs.ANALOG INPUT FREQUENCYANALOG INPUT FREQUENCY (MHz)S F D R (d B c )1020304050Typical Operating Characteristics(V DD = 3V, OV DD = 2.5V, V REFIN = 2.048V, differential input at -0.5dBFS, f CLK = 20MHz, C L ≈10pF, T A = +25°C, unless otherwise noted.)MAX1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC withInternal Reference and Parallel Outputs_______________________________________________________________________________________7-8-4-60-24261101001000FULL-POWER INPUT BANDWIDTH vs.ANALOG INPUT FREQUENCY, SINGLE-ENDEDANALOG INPUT FREQUENCY (MHz)G A I N (d B )-8-4-60-24261101001000SMALL-SIGNAL INPUT BANDWIDTH vs.ANALOG INPUT FREQUENCY, SINGLE-ENDEDANALOG INPUT FREQUENCY (MHz)G A I N (d B)35454055506065-200SIGNAL-TO-NOISE RATIO vs.ANALOG INPUT POWER (f IN = 7.5344MHz)ANALOG INPUT POWER (dBFS)S N R (d B )-12-16-8-435454055506065-20SIGNAL-TO-NOISE PLUS DISTORTION vs.ANALOG INPUT POWER (f IN = 7.5344MHz)ANALOG INPUT POWER (dBFS)S I N A D (d B )-12-16-8-4-20-12-16-8-4TOTAL HARMONIC DISTORTION vs.ANALOG INPUT POWER (f IN = 7.5344MHz)ANALOG INPUT POWER (dBFS)504060807090100-20-12-16-8-4SPURIOUS-FREE DYNAMIC RANGE vs.ANALOG INPUT POWER (f IN = 7.5344MHz)ANALOG INPUT POWER (dBFS)S F D R (d B c )-0.3-0.2-0.100.10.20.302561283845126407688961024INTEGRAL NONLINEARITYM A X 1184 t o c 16DIGITAL OUTPUT CODEI N L (L S B )-0.3-0.2-0.100.10.20.302561283845126407688961024DIFFERENTIAL NONLINEARITYM A X 1184 t o c 17DIGITAL OUTPUT CODED N L (L S B )-0.10.100.30.20.40.50.6-4085GAIN ERROR vs. TEMPERATURETEMPERATURE (°C)G A I N E R R O R (%F S )10-153560Typical Operating Characteristics (continued)(V DD = 3V, OV DD = 2.5V, V REFIN = 2.048V, differential input at -0.5dBFS, f CLK = 20MHz, C L ≈10pF, T A = +25°C, unless otherwise noted.)M A X 1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel Outputs 8_______________________________________________________________________________________-0.4-0.2-0.30-0.10.1-4085OFFSET ERROR vs. TEMPERATURETEMPERATURE (°C)O F F S E T E R R O R (%F S )10-1535603132343335362.703.002.853.15 3.303.453.60ANALOG SUPPLY CURRENT vs.ANALOG SUPPLY VOLTAGEM A X 1184 t o c 20V DD (V)I V D D (m A )283034323638-4010-15356085ANALOG SUPPLY CURRENT vs.TEMPERATUREM A X 1184 t o c 21TEMPERATURE (°C)I V D D (m A )00.040.120.080.160.202.703.002.853.15 3.303.453.60ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY VOLTAGEV DD (V)I V D D (µA )50566862748035404550556065SNR/SINAD, -THD/SFDR vs.CLOCK DUTY CYCLECLOCK DUTY CYCLE (%)S N R /S I N A D , -T H D /S F D R (d B , d B c )2.00402.00502.00702.00602.00802.00902.703.002.853.15 3.303.453.60INTERNAL REFERENCE VOLTAGE vs. ANALOG SUPPLY VOLTAGEM A X 1184 t o c 24V DD (V)V R E F O U T (V )Typical Operating Characteristics (continued)(V DD = 3V, OV DD = 2.5V, V REFIN = 2.048V, differential input at -0.5dBFS, f CLK = 20MHz, C L ≈10pF, T A = +25°C, unless otherwise noted.)MAX1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC withInternal Reference and Parallel Outputs_______________________________________________________________________________________91.9902.0001.9952.0052.0102.015-4085INTERNAL REFERENCE VOLTAGEvs. TEMPERATURETEMPERATURE (°C)V R E O U T (V )10-15356021,00014,0007,00028,00035,00042,00049,00056,00063,00070,000OUTPUT NOISE HISTOGRAM (DC INPUT)DIGITAL OUTPUT CODEC O U N T SNN-1N+1N+2N-2Typical Operating Characteristics (continued)(V DD = 3V, OV DD = 2.5V, V REFIN = 2.048V, differential input at -0.5dBFS, f CLK = 20MHz, C L ≈10pF, T A = +25°C, unless otherwise noted.)M A X 1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel Outputs 10______________________________________________________________________________________Detailed Description The MAX1184 uses a 9-stage, fully-differential pipelined architecture (F igure 1) that allows for high-speed conversion while minimizing power consump-tion. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Counting the delay through the output latch, the clock-cycle latency is five clock cycles.1.5-bit (2-comparator) flash ADCs convert the held-input voltages into a digital code. The digital-to-analog converters (DACs) convert the digitized results backinto analog voltages, which are then subtracted fromthe original held input signals. The resulting error sig-nals are then multiplied by two and the residues are passed along to the next pipeline stages, where the process is repeated until the signals have been processed by all nine stages. Digital error correction compensates for ADC comparator offsets in each of these pipeline stages and ensures no missing codes.MAX1184Dual 10-Bit, 20Msps, 3V, Low-Power ADC with Internal Reference and Parallel OutputsFigure 1. Pipelined Architecture—Stage BlocksM A X 1184Figure 2 displays a simplified functional diagram of the input track-and-hold (T/H) circuits in both track-and-hold mode. In track mode, switches S1, S2a, S2b, S4a,S4b, S5a, and S5b are closed. The fully differential cir-cuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a andS2b set the common mode for the amplifier input, and open simultaneously with S1, sampling the input wave-form. Switches S4a and S4b are then opened before switches S3a and S3b, connect capacitors C1a and C1b to the output of the amplifier, and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers are used to charge capacitors C1a and C1b to the same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the MAX1184 to track-and-sample/hold analog inputs of high frequencies (>Nyquist). The ADC inputs (INA+, INB+, INA-, and INB-)can be driven either differentially or single-ended.Match the impedance of INA+ and INA-, as well as INB+ and INB- and set the common-mode voltage to midsupply (V DD /2) for optimum performance.Analog Inputs and ReferenceConfigurationsThe full-scale range of the MAX1184 is determined by the internally generated voltage difference between REF P (V DD /2 + V REFIN /4) and REF N (V DD /2 - V REFIN /4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose.REFOUT, REFP, COM (V DD /2), and REFN are internally buffered low-impedance outputs.The MAX1184 provides three modes of reference operation: • Internal reference mode• Buffered external reference mode • Unbuffered external reference mode In internal reference mode, connect the internal refer-ence output REFOUT to REFIN through a resistor (e.g.,10k Ω) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise filtering purposes, bypass REF IN with a >10nF capacitor to GND. In internal reference mode, REF OUT, COM,REFP, and REFN become low-impedance outputs.In buffered external reference mode, adjust the refer-ence voltage levels externally by applying a stable and accurate voltage at REF IN. In this mode, COM, REF P,and REFN become outputs. REFOUT may be left open or connected to REFIN through a >10k Ωresistor.In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REF P, COM, and REF N. With their buffers shut down, these nodes become high impedance and may be driven through separate external reference sources.Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel OutputsMAX1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC withInternal Reference and Parallel OutputsClock Input (CLK)The MAX1184’s CLK input accepts CMOS-compatible clock signals. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). In particular,sampling occurs on the rising edge of the clock signal,requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR perfor-mance of the on-chip ADCs as follows:where f IN represents the analog input frequency and t AJ is the time of the aperture jitter.Clock jitter is especially critical for undersampling applications. The clock input should always be consid-ered as an analog input and routed away from any ana-log input or other digital signal lines.The MAX1184 clock input operates with a voltage thresh-old set to V DD /2. Clock inputs with a duty cycle other than 50%, must meet the specifications for high and low peri-ods as stated in the Electrical Characteristics .System Timing RequirementsF igure 3 depicts the relationship between the clock input, analog input, and data output. The MAX1184samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. F igure 4 also determines the relationship between the input clock parameters and the valid output data on channels A and B.Digital Output Data, Output Data FormatSelection (T/B), Output Enable (OE )All digital outputs, D0A–D9A (Channel A) and D0B–D9B (Channel B), are TTL/CMOS logic-compati-ble. There is a five-clock-cycle latency between anyparticular sample and its corresponding output data.Figure 3. System Timing DiagramM A X 1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel Outputs Table 1. MAX1184 Output Codes For Differential InputsThe output coding can be chosen to be either straightoffset binary or two’s complement (Table 1) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two’s complement output coding.The capacitive load on the digital outputs D0A–D9A and D0B–D9B should be kept as low as possible (<15pF) to avoid large digital currents that could feed back into the analog portion of the MAX1184, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the MAX1184,small-series resistors (e.g., 100Ω) may be added to the digital output paths close to the MAX1184.F igure 4 displays the timing relationship between out-put enable and data output valid as well as power-down/wake-up and data output valid.Power-Down (PD) and Sleep (SLEEP) ModesThe MAX1184 offers two power-save modes—sleep and full power-down mode. In sleep mode (SLEEP = 1), only the reference bias circuit is active (both ADCs are dis-abled), and current consumption is reduced to 2.8mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to the power down. Pulling OE high forces the digital outputs into a high-impedance state.Applications InformationF igure 5 depicts a typical application circuit containing two single-ended to differential converters. The internal reference provides a V DD /2 output voltage for level-shift-ing purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per ADC suppresses some of the wideband noise associated with high-speed op amps follows the amplifiers. The user may select the R ISO and C IN values to optimize the filter per-formance, to suit a particular application. For the applica-tion in F igure 5, a R ISO of 50Ωis placed before the capacitive load to prevent ringing and oscillation. The 22pF C IN capacitor acts as a small bypassing capacitor.Figure 4. Output Timing DiagramMAX1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC withInternal Reference and Parallel OutputsFigure 5. Typical Application for Single-Ended to Differential ConversionM A X 1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel OutputsFigure 7: Using an Op Amp for Single-Ended, AC-Coupled Input DriveUsing Transformer CouplingA RF transformer (Figure 6) provides an excellent solu-tion to convert a single-ended source signal to a fully differential signal, required by the MAX1184 for opti-mum performance. Connecting the center tap of the transformer to COM provides a V DD /2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, may also improve the over-all distortion.In general, the MAX1184 provides better SF DR and THD with fully-differential input signals than single-ended drive, especially for very high input frequencies.In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to a single-ended mode.Single-Ended AC-Coupled Input SignalFigure 7 shows an AC-coupled, single-ended applica-tion. Amplifiers like the MAX4108 provide high speed,high bandwidth, low noise, and low distortion to main-tain the integrity of the input signal.Figure 6. Transformer-Coupled Input DriveMAX1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC withInternal Reference and Parallel OutputsTypical QAM Demodulation ApplicationThe most frequently used modulation technique for digi-tal communications applications is probably the quadra-ture amplitude modulation (QAM). Typically found in spread-spectrum-based systems, a QAM signal repre-sents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent up-conversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q)carrier component, where the Q component is 90 degree phase-shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into it’s I and Q components, essentially representing the modula-tion process reversed. F igure 8 displays the demodula-tion process performed in the analog domain, using the dual matched 3V, 10-bit ADC (MAX1184), and the MAX2451 quadrature demodulator to recover and digi-tize the I and Q baseband signals. Before being digitized by the MAX1184, the mixed down-signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters, which remove any unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference.Grounding, Bypassing, andBoard LayoutThe MAX1184 requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum induc-tance. Bypass V DD , REF P, REF N, and COM with twoparallel 0.1µF ceramic capacitors and a 2.2µF bipolar capacitor to GND. Follow the same rules to bypass the digital supply (OV DD ) to OGND. Multilayer boards with separated ground and power planes produce the high-est level of signal integrity. Consider the use of a split ground plane arranged to match the physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC’s package. The two ground planes should be joined at a single point such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location of this connec-tion can be determined experimentally at a point along the gap between the two ground planes, which pro-duces optimum results. Make this connection with a low-value, surface-mount resistor (1Ωto 5Ω), a ferrite bead,or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is suf-ficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk.Keep all signal lines short and free of 90 degree turns.Static Parameter DefinitionsIntegral Nonlinearity (INL)Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static lin-earity parameters for the MAX1184 are measured using the best straight-line fit method.M A X 1184Dual 10-Bit, 20Msps, 3V , Low-Power ADC with Internal Reference and Parallel Outputs Differential Nonlinearity (DNL)Differential nonlinearity is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.Dynamic Parameter DefinitionsAperture JitterF igure 9 depicts the aperture jitter (t AJ ), which is the sample-to-sample variation in the aperture delay.Aperture DelayAperture delay (t AD ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 9).Signal-to-Noise Ratio (SNR)F or a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantiza-tion error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N-Bits):SNR dB[max]= 6.02 x N + 1.76In reality, there are other noise sources besides quanti-zation noise (e.g. thermal noise, reference noise, clock jitter, etc.). SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spec-tral components minus the fundamental, the first five harmonics, and the DC offset.Signal-to-Noise Plus Distortion (SINAD)SINAD is computed by taking the ratio of the RMS sig-nal to all spectral components minus the fundamental and the DC offset.Total Harmonic Distortion (THD)THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself.This is expressed as:where V 1is the fundamental amplitude, and V 2throughV 5are the amplitudes of the 2nd- through 5th-order harmonics.Spurious-Free Dynamic Range (SFDR)SF DR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal compo-nent) to the RMS value of the next largest spurious component, excluding DC offset.Intermodulation Distortion (IMD)The two-tone IMD is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter-modulation products. The individual input tone levelsbacked off by 6.5dB from full scale.Figure 9. T/H Aperture TimingTable 2. Pin-Compatible Versions。

ADI电路笔记 CN-0359说明书

ADI电路笔记 CN-0359说明书

电路笔记CN-0359Circuits from the Lab® reference designs are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit /CN0359.连接/参考器件AD825310 MHz、20 V/μs、G = 1、10、100、1000、i CMOS可编程增益仪表放大器ADuCM360集成双通道Σ-Δ型ADC和ARM Cortex-M3的低功耗精密模拟微控制器ADA4627-1 30 V、高速、低噪声、低偏置电流JFET运算放大器AD8542CMOS轨到轨通用放大器ADA4000-1 低成本、精密JFET输入运算放大器ADP2300 1.2 A、20 V、700 kHz/1.4 MHz异步降压型稳压器ADA4638-1 30 V、零漂移、轨到轨输出精密放大器ADP1613 650 kHz/1.3 MHz升压PWM DC-DC开关转换器ADA4528-2 精密、超低噪声、RRIO、双通道、零漂移运算放大器ADG1211低电容、低电荷注入、±15 V/+12 V iCMOS四通道单刀单掷开关ADA4077-2 4 MHz、7 nV/√Hz、低失调和漂移、高精度放大器ADG1419 2.1 Ω导通电阻、±15 V/+12 V/±5 V、iCMOS单刀双掷开关AD8592 CMOS、单电源、轨到轨输入/输出运算放大器,具有关断功能ADM3483 3.3 V限摆率、半双工、RS-485/RS-422收发器全自动高性能电导率测量系统Rev. 0Circuits from the Lab® reference designs from Analog Devices have been designed and built by AnalogDevices engineers. Standard engineering practices have been employed in the design andconstruction of each circuit, and their function and performance have been tested and veri ed in a labenvironment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2015 Analog Devices, Inc. All rights reserved.评估和设计支持电路评估板CN-0359电路评估板(EVAL-CN0359-EB1Z)设计和集成文件原理图、源代码、布局文件、物料清单电路功能与优势图1中的电路是一个完全独立自足、微处理器控制的高精度电导率测量系统,适用于测量液体的离子含量、水质分析、工业质量控制以及化学分析。

龙芯 2K1000LA 处理器 用户手册说明书

龙芯 2K1000LA 处理器 用户手册说明书

龙芯2K1000LA处理器用户手册V1.02022年5月龙芯中科技术股份有限公司版权声明本文档版权归龙芯中科技术股份有限公司所有,并保留一切权利。

未经书面许可,任何公司和个人不得将此文档中的任何部分公开、转载或以其他方式散发给第三方。

否则,必将追究其法律责任。

免责声明本文档仅提供阶段性信息,所含内容可根据产品的实际情况随时更新,恕不另行通知。

如因文档使用不当造成的直接或间接损失,本公司不承担任何责任。

龙芯中科技术股份有限公司Loongson Technology Corporation Limited地址:北京市海淀区中关村环保科技示范园龙芯产业园2号楼Building No.2, Loongson Industrial Park, Zhongguancun Environmental Protection Park电话(Tel):************传真(Fax):************阅读指南《龙芯2K1000LA处理器用户手册》主要介绍龙芯2K1000LA架构与寄存器描述,对芯片系统架构、主要模块的功能与配置、寄存器列表及位域进行详细说明。

版本信息手册信息反馈: *******************。

目录目录....................................................................................................................................... I 图目录 ................................................................................................................................. I X 表目录 .................................................................................................................................. X 1 概述 . (1)1.1体系结构框图 (1)1.2芯片主要功能 (2)1.2.1 处理器核 (2)1.2.2 内存接口 (2)1.2.3 PCIE接口 (3)1.2.4 GPU (3)1.2.5 显示控制器 (3)1.2.6 SATA控制器 (3)1.2.7 USB2.0 控制器 (3)1.2.8 GMAC控制器 (3)1.2.9 VPU解码器 (4)1.2.10 CAMERA控制器 (4)1.2.11 HDA控制器 (4)1.2.12 I2S控制器 (4)1.2.13 NAND控制器 (5)1.2.14 SPI控制器 (5)1.2.15 UART (5)1.2.16 I2C总线 (5)1.2.17 PWM (6)1.2.18 HPET (6)1.2.19 RTC (6)1.2.20 Watchdog (6)1.2.21 中断控制器 (6)1.2.22 CAN (6)1.2.23 ACPI功耗管理 (6)1.2.24 GPIO (7)1.2.25 加解密模块 (7)1.2.26 SDIO控制器 (7)2 引脚定义 (8)2.1约定 (8)2.2DDR3接口 (8)2.3PCIE接口 (9)2.4DVO显示接口 (9)2.5GMAC接口 (11)2.6SATA接口 (12)2.7USB接口 (12)2.8CAMERA接口 (12)2.9HDA接口 (13)2.10SPI接口 (14)2.11I2C接口 (14)2.12UART接口 (14)2.13CAN接口 (15)2.14NAND接口 (16)2.15SDIO接口 (16)2.16GPIO (16)2.17PWM (17)2.18PLL电源接口 (17)2.19电源管理接口 (17)2.20测试接口 (18)2.21JTAG接口 (18)2.22时钟信号 (18)2.23RTC相关信号 (18)2.24系统相关信号 (19)2.25外设功能复用表 (20)3 时钟结构 (21)3.1NODE PLL (21)3.2PIX PLL (21)3.3DDR PLL (22)3.4DC PLL (22)3.5内部PLL配置方法 (23)3.5.1 硬件配置 (23)3.5.2 软件配置 (23)3.6BOOT时钟 (24)3.7USB参考时钟 (24)3.8PCIE参考时钟 (24)3.9SATA参考时钟输入 (24)4 电源管理 (25)4.1电源管理模块介绍 (25)4.2电源级别 (25)4.3控制引脚说明 (25)5 芯片配置寄存器 (27)5.1通用配置寄存器0 (34)5.2通用配置寄存器1 (36)5.3通用配置寄存器2 (37)5.4APBDMA配置寄存器 (39)5.5USB PHY0/1配置寄存器 (40)5.6USB PHY2/3配置寄存器 (44)5.7SATA配置寄存器 (45)5.8NODE PLL低64位配置寄存器 (46)5.9NODE PLL高64位配置寄存器 (47)5.10DDR PLL低64位配置寄存器 (47)5.11DDR PLL高64位配置寄存器 (48)5.12DC PLL低64位配置寄存器 (48)5.13DC PLL高64位配置寄存器 (49)5.14PIX0PLL低64位配置寄存器 (49)5.15PIX0PLL高64位配置寄存器 (50)5.16PIX1PLL低64位配置寄存器 (51)5.17PIX1PLL高64位配置寄存器 (51)5.18FREQSCALE配置寄存器 (52)5.19PCIE0配置寄存器0 (52)5.20PCIE0配置寄存器1 (53)5.21PCIE0PHY配置控制寄存器 (54)5.22PCIE1配置寄存器0 (54)5.23PCIE1配置寄存器1 (55)5.24PCIE1PHY配置控制寄存器 (56)5.25DMA命令控制寄存器(DMA_ORDER) (56)5.26PCICFG2_RECFG寄存器 (57)5.27PCICFG30_RECFG寄存器 (57)5.28PCICFG31_RECFG寄存器 (58)5.29PCICFG40_RECFG寄存器 (59)5.30PCICFG41_RECFG寄存器 (59)5.31PCICFG42_RECFG寄存器 (60)5.32PCICFG5_RECFG寄存器 (60)5.33PCICFG6_RECFG寄存器 (61)5.34PCICFG7_RECFG寄存器 (61)5.35PCICFG8_RECFG寄存器 (62)5.36PCICFG F_RECFG寄存器 (63)5.37PCICFG10_RECFG寄存器 (63)5.38PCICFG11_RECFG寄存器 (64)6 地址空间分配 (65)6.1一级交叉开关 (66)6.2二级交叉开关 (66)6.3IO互连网络 (69)6.3.1 IO设备的配置空间 (70)6.3.2 APB配置头 (77)6.3.3 GMAC0/1 配置头 (78)6.3.4 USB OTG配置头 (78)6.3.5 USBEHCI配置头 (79)6.3.6 USB OHCI 配置头 (79)6.3.7 GPU配置头 (79)6.3.8 DC配置头 (80)6.3.9 HDA配置头 (80)6.3.10 SATA配置头 (81)6.3.11 PCIE配置头 (81)6.3.12 DMA配置头 (82)6.3.13 VPU配置头 (82)6.3.14 CAMERA配置头 (83)6.3.15 N/A处理 (83)6.4IODMA请求 (83)6.5APB设备路由 (86)7 处理器核间中断与通信 (88)8 温度传感器 (90)8.1实时温度采样 (90)8.2高低温中断触发 (90)8.3高温自动降频设置 (91)9 I/O中断 (93)9.1中断触发类型 (94)9.2中断分发模式 (94)9.3中断相关寄存器描述 (94)9.4GPIO中断 (99)9.5MSI中断 (99)9.6硬件中断负载均衡功能举例 (100)10 SPI控制器 (103)10.1访问地址 (103)10.2SPI控制器结构 (103)10.3配置寄存器 (103)10.3.1 控制寄存器(SPCR) (103)10.3.2 状态寄存器(SPSR) (104)10.3.3 数据寄存器(TxFIFO/RxFIFO) (104)10.3.4 外部寄存器(SPER) (104)10.3.5 参数控制寄存器(SFC_PARAM) (105)10.3.6 片选控制寄存器(SFC_SOFTCS) (105)10.3.7 时序控制寄存器(SFC_TIMING) (105)10.4接口时序 (106)10.4.1 SPI主控制器接口时序 (106)10.4.2 SPI Flash访问时序 (106)10.5软件编程指南 (107)10.5.1 SPI主控制器的读写操作 (107)10.5.2 硬件SPI Flash读 (107)10.5.3 混合访问SPI Flash和SPI主控制器 (108)11 LocalIO控制器 (109)11.1访问地址及引脚复用 (109)11.2L OCAL IO控制器功能概述 (109)12 DDR3控制器 (111)12.1访问地址 (111)12.2DDR3SDRAM控制器功能概述 (111)12.3DDR3SDRAM读操作协议 (111)12.4DDR3SDRAM写操作协议 (112)12.5DDR3控制器寄存器 (112)13 GPIO (116)13.1GPIO方向控制 (116)13.2GPIO输出设置 (116)13.3GPIO输入采样 (116)13.4GPIO中断使能 (116)13.5GPIO复用关系 (117)14 APB设备(Dev 2) (119)14.1内部设备地址路由 (119)15 UART控制器 (121)15.1概述 (121)15.2访问地址及引脚复用 (121)15.3控制器结构 (121)15.4寄存器描述 (122)15.4.1 数据寄存器(DAT) (122)15.4.2 中断使能寄存器(IER) (122)15.4.3 中断标识寄存器(IIR) (123)15.4.4 FIFO控制寄存器(FCR) (123)15.4.5 线路控制寄存器(LCR) (124)15.4.6 MODEM控制寄存器(MCR) (124)15.4.7 线路状态寄存器(LSR) (125)15.4.8 MODEM状态寄存器(MSR) (126)15.4.9 分频锁存器 (126)16 CAN (127)16.1访问地址及引脚复用 (127)16.2标准模式 (127)16.2.1 控制寄存器(CR) (128)16.2.2 命令寄存器(CMR) (129)16.2.3 状态寄存器(SR) (129)16.2.4 中断寄存器(IR) (130)16.2.5 验收代码寄存器(ACR) (130)16.2.6 验收屏蔽寄存器(AMR) (130)16.2.7 发送缓冲区列表 (131)16.2.8 接收缓冲区列表 (131)16.3扩展模式 (131)16.3.1 模式寄存器(MOD) (134)16.3.2 命令寄存器(CMR) (134)16.3.3 状态寄存器(SR) (135)16.3.4 中断寄存器(IR) (135)16.3.5 中断使能寄存器(IER) (136)16.3.6 仲裁丢失捕捉寄存器 (136)16.3.7 错误警报限制寄存器(EMLR) (137)16.3.8 RX错误计数寄存器(RXERR) (138)16.3.9 TX错误计数寄存器(TXERR) (138)16.3.10 验收滤波器 (138)16.3.11 RX信息计数寄存器(RMCR) (138)16.4公共寄存器 (138)16.4.1 总线定时寄存器0(BTR0) (138)16.4.2 总线定时寄存器1(BTR1) (139)16.4.3 输出控制寄存器(OCR) (139)17 I2C控制器 (140)17.1概述 (140)17.2访问地址及引脚复用 (140)17.3I2C控制器结构 (140)17.4I2C控制器寄存器说明 (141)17.4.1 分频锁存器低字节寄存器(PRERlo) (141)17.4.2 分频锁存器高字节寄存器(PRERhi) (141)17.4.3 控制寄存器(CTR) (141)17.4.4 发送数据寄存器(TXR) (142)17.4.5 接受数据寄存器(RXR) (142)17.4.6 命令控制寄存器(CR) (142)17.4.7 状态寄存器(SR) (143)18 PWM控制器 (144)18.1概述 (144)18.2访问地址及引脚复用 (144)18.3寄存器描述 (144)18.4功能说明 (145)18.4.1 脉宽调制功能 (145)18.4.2 脉冲测量功能 (145)18.4.3 防死区功能 (146)19 HPET控制器 (147)19.1概述 (147)19.2访问地址 (147)19.3寄存器描述 (147)20 NAND控制器 (151)20.1NAND控制器结构描述 (151)20.2访问地址及引脚复用 (151)20.3NAND寄存器配置描述 (151)20.3.1 命令寄存器NAND_CMD (偏移地址0x00) (151)20.3.2 页内偏移地址寄存器ADDR_C (偏移地址0x04) (152)20.3.3 页地址寄存器ADDR_R (偏移地址0x08) (152)20.3.4 时序寄存器NAND_TIMING (偏移地址0x0C) (152)20.3.5 ID寄存器ID_L (偏移地址0x10) (153)20.3.6 ID和状态寄存器STATUS & ID_H (偏移地址0x14) (153)20.3.7 参数配置寄存器NAND_PARAMETER (偏移地址0x18) (153)20.3.8 操作数量寄存器NAND_OP_NUM (偏移地址0x1C) (153)20.3.9 映射寄存器CS_RDY_MAP (偏移地址0x20) (154)20.3.10 DMA读写数据寄存器DMA_ADDRESS (偏移地址0x40) (154)20.4NAND ADDR说明 (154)20.5NAND-FLASH读写操作举例 (157)20.6NAND ECC说明 (157)20.7支持NAND型号 (159)21 电源管理模块 (160)21.1概述 (160)21.2访问地址 (160)21.3寄存器描述 (160)22 RTC (170)22.1概述 (170)22.2访问地址 (170)22.3寄存器描述 (170)22.3.1 寄存器地址列表 (170)22.3.2 SYS_TOYWRITE0 (171)22.3.3 SYS_TOYWRITE1 (171)22.3.4 SYS_TOYREAD0 (171)22.3.5 SYS_TOYREAD1 (171)22.3.6 SYS_TOYMATCH0/1/2 (172)22.3.7 SYS_RTCCTRL (172)22.3.8 SYS_RTCWRITE (173)22.3.9 SYS_RTCREAD (173)22.3.10 SYS_RTCMA TCH0/1/2 (173)23 加解密 (174)23.1DES (174)23.1.1 DES功能概述 (174)23.1.2 DES访问地址: (174)23.1.3 DES寄存器描述 (174)23.2AES (175)23.2.1 AES功能概述 (175)23.2.2 AES访问地址: (176)23.2.3 AES寄存器描述 (176)23.3RSA (178)23.3.1 RSA访问地址: (178)23.4RNG (178)23.4.1 RNG访问地址: (178)24 SDIO控制器 (179)24.1功能概述 (179)24.2访问地址及引脚复用 (179)24.3SDIO协议概述 (179)24.4寄存器描述 (180)24.5软件编程指南 (186)24.5.1 SD Memory卡软件编程说明 (186)24.5.2 SDIO卡软件编程说明 (188)24.6支持SDIO型号 (189)25 I2S控制器 (190)25.1概述 (190)25.2访问地址及引脚复用 (190)25.3接口协议 (190)25.4专用寄存器 (191)25.5配置操作 (192)26 GMAC控制器(Dev 3) (194)26.1访问地址及引脚复用 (194)27 OTG控制器(Dev 4, Fun 0) (195)27.1概述 (195)27.2访问地址 (195)28 USB控制器(Dev 4, Fun 1/2) (196)28.1总体概述 (196)28.2访问地址 (196)29 图形处理器(Dev 5) (198)29.1访问地址 (198)30 显示控制器(Dev 6) (199)30.1概述 (199)30.2访问地址及引脚复用 (199)31 HDA控制器(Dev 7) (200)31.1功能概述 (200)31.2访问地址 (200)32 SATA控制器(Dev 8) (201)32.1SATA总体描述 (201)32.2访问地址 (201)32.3SATA控制器内部寄存器描述 (201)33 PCIE控制器(Dev 9/A/B/C/D/E) (203)33.1总体结构 (203)33.2访问地址 (203)33.3地址空间划分 (204)33.4软件编程指南 (205)33.4.1 PCIE控制器使能 (205)33.4.2 PCIE配置头访问 (205)33.4.3 PCIE链路建立(Linkup) (205)33.4.4 TYPE1类型配置访问 (206)33.4.5 PCIE PHY配置方法 (206)33.5常用例程 (206)34 DMA控制器(Dev F) (209)34.1DMA控制器结构描述 (209)34.2访问地址 (209)34.3DMA控制器与APB设备的交互 (210)34.4DMA描述符 (210)34.4.1 DMA_ORDER_ADDR_LOW (210)34.4.2 DMA_SADDR (210)34.4.3 DMA_DADDR (211)34.4.4 DMA_LENGTH (211)34.4.5 DMA_STEP_LENGTH (211)34.4.6 DMA_STEP_TIMES (212)34.4.7 DMA_CMD (212)34.4.8 DMA_ORDER_ADDR_HIGH (213)34.4.9 DMA_SADDR_HIGH (213)35 VPU控制器(Dev 16) (214)35.1访问地址 (214)36 CAMERA接口控制器(Dev 17) (215)36.1功能概述 (215)36.2访问地址 (215)图1-1 龙芯2K1000结构图 (2)图3-1 NODE PLL结构图 (21)图3-2 PIX PLL结构图 (22)图3-3 DDR PLL结构图 (22)图3-4 DC PLL结构图 (23)图3-5 BOOT时钟结构图 (24)图6-1 二级交叉开关地址路由示意图 (66)图6-2 IO互连结构图 (70)图6-3 64位配置访问地址格式 (70)图6-4 32位配置访问地址格式 (71)图9-1 龙芯2K1000处理器中断路由示意图 (93)图10-1 SPI主控制器接口时序 (106)图10-2 SPI Flash标准读时序 (106)图10-3 SPI Flash快速读时序 (106)图10-4 SPI Flash双向I/O读时序 (107)图11-1 LocalIO读时序 (109)图11-2 LocalIO写时序 (110)图12-1 DDR3 SDRAM读操作协议 (112)图12-2 DDR3 SDRAM写操作协议 (112)图15-1 UART控制器结构 (122)图17-1 I2C主控制器结构 (141)图18-1 防死区功能 (146)图24-1 SD卡多块写操作示意图 (180)图24-2 SD卡多块读操作示意图 (180)图24-3 SD Memory卡初始化流程示意图 (187)图25-1 I2S传输协议 (191)图28-1 USB主机控制器模块图 (196)图33-1 PCIE控制器结构 (203)表2-1 信号类型代码 (8)表2-2 DDR3SDRAM控制器接口信号 (8)表2-3 PCIE总线信号 (9)表2-4 DVO接口信号 (9)表2-5 DVO接口RGB对应关系 (10)表2-6 DVO0与LIO复用关系 (10)表2-7 DVO0与UART复用关系 (10)表2-8 GMAC接口信号 (11)表2-9 GMAC1与GPIO复用关系 (11)表2-10 SATA接口信号 (12)表2-11 SATA与GPIO复用关系 (12)表2-12 USB接口信号 (12)表2-13 CAMERA接口信号 (12)表2-14 CAMERA与DVO1复用关系 (13)表2-15 HDA接口信号 (13)表2-16 HDA与I2S复用关系 (13)表2-17 HDA与GPIO复用关系 (13)表2-18 SPI接口信号 (14)表2-19 I2C接口信号 (14)表2-20 I2C与GPIO复用关系 (14)表2-21 UART接口信号 (14)表2-22 UART接口复用关系 (15)表2-23 CAN接口信号 (15)表2-24 CAN与GPIO复用关系 (15)表2-25 NAND接口信号 (16)表2-26 NAND与GPIO复用关系 (16)表2-27 SDIO接口信号 (16)表2-28 SDIO与GPIO复用关系 (16)表2-29 GPIO信号 (17)表2-30 PWM信号 (17)表2-31 PWM与GPIO复用关系 (17)表2-32 PLL电源接口 (17)表2-33 电源管理接口 (17)表2-34 测试接口 (18)表2-35 JTAG接口 (18)表2-36 时钟信号 (18)表2-37 时钟信号 (18)表2-38 系统相关信号 (19)表2-39 外设功能复用表 (20)表3-1 PLL硬件配置 (23)表4-1 ACPI状态说明 (25)表4-2 控制引脚说明 (25)表5-1 芯片配置寄存器列表 (27)表5-2 通用配置寄存器0 (34)表5-3 通用配置寄存器1 (36)表5-4 通用配置寄存器2 (37)表5-5 APBDMA配置寄存器 (39)表5-6 USB 0/1 PHY配置寄存器 (40)表5-7 USB 2/3 PHY配置寄存器 (44)表5-8 SATA配置寄存器 (45)表5-9 NODE PLL低64位配置寄存器 (46)表5-10 NODE PLL高64位配置寄存器 (47)表5-11 DDR PLL低64位配置寄存器 (47)表5-12 DDR PLL高64位配置寄存器 (48)表5-13 DC PLL低64位配置寄存器 (48)表5-14 DC PLL高64位配置寄存器 (49)表5-15 PIX0 PLL低64位配置寄存器 (49)表5-16 PIX0 PLL高64位配置寄存器 (50)表5-17 PIX1 PLL低64位配置寄存器 (51)表5-18 PIX1 PLL高64位配置寄存器 (51)表5-19 FRESCALE配置寄存器 (52)表5-20 PCIE0配置寄存器0 (52)表5-21 PCIE0配置寄存器1 (53)表5-22 PCIE0 PHY配置寄存器 (54)表5-23 PCIE1配置寄存器0 (54)表5-24 PCIE1配置寄存器1 (55)表5-25 PCIE1 PHY配置寄存器 (56)表5-26 DMA命令控制寄存器 (56)表5-27 PCICFG2_RECFG配置寄存器 (57)表5-28 PCICFG30_RECFG配置寄存器 (57)表5-29 PCICFG31_RECFG配置寄存器 (58)表5-30 PCICFG40_RECFG配置寄存器 (59)表5-31 PCICFG41_RECFG配置寄存器 (59)表5-32 PCICFG42_RECFG配置寄存器 (60)表5-33 PCICFG5_RECFG配置寄存器 (60)表5-34 PCICFG6_RECFG配置寄存器 (61)表5-35 PCICFG7_RECFG配置寄存器 (61)表5-36 PCICFG8_RECFG配置寄存器 (62)表5-37 PCICFGf_RECFG配置寄存器 (63)表5-38 PCICFG10_RECFG配置寄存器 (63)表5-39 PCICFG11_RECFG配置寄存器 (64)表6-1 芯片地址空间划分 (65)表6-2 一级交叉开关路由规则 (66)表6-3 二级交叉开关处标号与所述模块的对应关系 (67)表6-4 MMAP字段对应的该空间访问属性 (67)表6-5 二级交叉开关地址窗口转换寄存器表 (67)表6-6 各个设备的配置头访问对应关系 (71)表6-7 Type0类型配置头 (72)表6-8 Type0的配置头寄存器 (72)表6-9 Type1类型配置头 (74)表6-10 Type1的配置头寄存器 (75)表6-11 APB总线控制器的配置头缺省值 (77)表6-12 GMAC0控制器的配置头缺省值 (78)表6-13 USB-OTG控制器的配置头缺省值 (78)表6-14 USB-EHCI控制器的配置头缺省值 (79)表6-15 USB-OHCI控制器的配置头缺省值 (79)表6-16 GPU控制器的配置头缺省值 (80)表6-17 DC控制器的配置头缺省值 (80)表6-18 HDA控制器的配置头缺省值 (80)表6-19 SATA控制器的配置头缺省值 (81)表6-20 PCIE0 Port0的配置头缺省值 (81)表6-21 DMA控制器的配置头缺省值 (82)表6-22 VPU解码器的配置头缺省值 (82)表6-23 CAMERA控制器的配置头缺省值 (83)表6-24 MMAP字段对应的该空间访问属性 (84)表6-25 IO设备DMA访存地址转换寄存器表 (84)表6-26 APB设备地址译码 (86)表7-1 处理器核间中断相关的寄存器及其功能描述 (88)表7-2 0号处理器核核间中断与通信寄存器列表 (88)表7-3 1号处理器核的核间中断与通信寄存器列表 (88)表8-1 温度采样寄存器说明 (90)表8-2 高低温中断寄存器说明 (91)表8-3 高温降频控制寄存器说明 (92)表9-1 中断控制寄存器属性 (94)表9-2 中断控制寄存器地址 (96)表9-3 中断路由寄存器的说明 (97)表9-4 中断路由寄存器地址 (97)表9-5 GPIO中断 (99)表9-6 MSI中断相关寄存器 (100)表10-1 SPI控制器地址空间分配 (103)表10-2 SPI配置寄存器列表 (103)表10-3 SPI控制寄存器(SPCR) (103)表10-4 SPI状态寄存器(SPSR) (104)表10-5 SPI数据寄存器(TxFIFO/RXFIFO) (104)表10-6 SPI外部寄存器(SPER) (104)表10-7 SPI分频系数 (104)表10-8 SPI参数控制寄存器(SFC_PARAM) (105)表10-9 SPI片选控制寄存器(SFC_SOFTCS) (105)表10-10 SPI时序控制寄存器(SFC_TIMING) (105)表11-1 LocalIO地址空间分配 (109)表12-1 内存控制器地址空间分配 (111)表12-2 DDR3控制器配置寄存器 (112)表13-1 GPIO配置寄存器 (116)表13-2 GPIO方向控制 (116)表13-3 GPIO输出设置 (116)表13-4 GPIO输入采样 (116)表13-5 GPIO中断使能 (116)表13-6 GPIO复用关系 (117)表14-1 APB配置访问信息 (119)表14-2 APB设备地址译码 (119)表15-1 UART控制器物理地址构成 (121)表15-2 UART数据寄存器 (122)表15-3 UART中断使能寄存器 (123)表15-4 UART中断标识寄存器 (123)表15-5 UART中断控制功能表 (123)表15-6 UART的FIFO控制寄存器 (124)表15-7 UART线路控制寄存器 (124)表15-8 UART的MODEM控制寄存器 (125)表15-9 UART线路状态寄存器 (125)表15-10 UART的MODEM状态寄存器 (126)表15-11 UART分频锁存器1 (126)表15-12 UART 分频锁存器2 (126)表16-1 CAN内部寄存器物理地址构成 (127)表18-1 PWM寄存器列表 (144)表18-2 PWM控制寄存器设置 (144)表25-1 寄存器定义 (191)表25-2 标识寄存器 (191)表25-3 配置寄存器 (191)表25-4 控制寄存器 (192)表34-1 DMA ORDER寄存器 (209)1概述龙芯2K1000LA处理器(简称龙芯2K1000)主要面向于网络应用,兼顾平板应用及工控领域应用。

  1. 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
  2. 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
  3. 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。
VIN2 REF = 0.6V INTERNAL LOGIC REF = 0.6V PWRGD VIN4 REF = 0.6V
07352-001
功能框图
VCC
ADM1184VIN1 REF= 0.6VPOWER AND REF = 0.6V REFERENCE GENERATOR OUT1
OUT2
−20 0.5952
0.6000
VCC = 2.7 V, ISINK = 2 mA VCC = 1 V, ISINK = 100 µA 所有输出均保证为低电压,或提供从VCC = 1 V 开始的有效输出电平 参见图18和图19中的时序图。 VCC = 3.3 V VCC = 3.3 V VCC = 3.3 V
−1 1
30 30 190
280
µs µs ms
Rev. 0 | Page 3 of 12
ADM1184 绝对最大额定值
除非另有说明,TA = 25°C。 表2.
参数 VCC引脚 VINx引脚 OUTx,PWRGD引脚 存储温度范围 工作温度范围 引脚焊接(10秒)温度 结温 额定值 -0.3 V至+6 V -0.3 V至+6 V -0.3 V至+6 V −65°C至+125°C -40°C至+85°C 300°C 150°C
ADI中文版数据手册是英文版数据手册的译文,敬请谅解翻译中可能存在的语言组织或翻译错误,ADI不对翻译中存在的差异或由此产生的错误负责。如需确认任何词语的准确性,请参考ADI提供 的最新英文版数据手册。
ADM1184 目录
特性 .................................................................................................... 1 应用 .................................................................................................... 1 功能框图 ........................................................................................... 1 概述 .................................................................................................... 1 修订历史 ........................................................................................... 2 规格 .................................................................................................... 3 绝对最大额定值 .............................................................................. 4 热阻 .............................................................................................. 4 ESD警告 ....................................................................................... 4 引脚配置和功能描述 ..................................................................... 5 典型工作特性 .................................................................................. 6 工作原理 ........................................................................................... 9 输入配置 ...................................................................................... 9 输出配置 ...................................................................................... 9 电压监控和时序控制应用 ..................................................... 11 外形尺寸 ......................................................................................... 12 订购指南 .................................................................................... 12
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Speci cations subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
应用
监控和报警功能 电信 微处理器系统 个人计算机/服务器
OUT3
VIN3
GND
概述
ADM1184是一款集成式4通道电压监控器件。其供电引脚 为VCC引脚,电源电压为2.7 V至5.5 V。 四个精密比较器监控着四个电压轨。每个比较器均有0.6 V 的基准电压,最差精度为 0.8% 。 VIN1、 VIN2、 VIN3 和 VIN4四个引脚的外部电阻网络设置被监控供电轨的跳变 点。 ADM1184 有四个开漏输出。 OUT1 至 OUT3 用于使能电 源,PWRGD则是普通的电源正常输出。
注意,超出上述绝对最大额定值可能会导致器件永久性损 坏。这只是额定应力值,不表示在这些条件下或者在任何 其它超出本技术规范操作章节中所示规格的条件下,器件 能够正常工作。长期在绝对最大额定值条件下工作会影响 器件的可靠性。
Rev. 0 | Page 4 of 12
ADM1184 引脚配置和功能描述
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
GND 1 VIN1 2 VIN2 3 VIN3 4 VIN4 5
10
VCC OUT1 OUT2 PWRGD
07352-002
ADM1184
TOP VIEW (Not to Scale)
9 8 7 6
OUT3
图2. 引脚配置
表4. 引脚功能描述
引脚编 1 2 3 4 5 6 7 8 9 10 引脚名称 GND VIN1 VIN2 VIN3 VIN4 PWRGD OUT3 OUT2 OUT1 VCC 描述 芯片接地引脚。 比较器1的同相输入。该引脚电压为相对于0.6 V基准电压的值。可通过电阻分压器监控电压轨。 比较器2的同相输入。该引脚电压为相对于0.6 V基准电压的值。可通过电阻分压器监控电压轨。 比较器3的同相输入。该引脚电压为相对于0.6 V基准电压的值。可通过电阻分压器监控电压轨。 比较器4的同相输入。该引脚电压为相对于0.6 V基准电压的值。可通过电阻分压器监控电压轨。 高电平有效,开漏输出。每个VINx输入上的电压超过0.6 V时,PWRGD会在190 ms延迟后置位。PWRGD置 位后,如果VIN1、VIN2、VIN3或VIN4监控的电压降至0.6 V以下,PWRGD输出会立即解除置位。 高电平有效,开漏输出。VIN3上的电压超过0.6 V时,OUT3会置位。OUT3会保持置位,直到VIN3监控的电 压降至0.6 V以下,然后会被拉低。 高电平有效,开漏输出。VIN2上的电压超过0.6 V时,OUT2会置位。OUT2会保持置位,直到VIN2监控的电 压降至0.6 V以下,然后会被拉低。 高电平有效,开漏输出。VIN1上的电压超过0.6 V时,OUT1会置位。OUT1会保持置位,直到VIN1监控的电 压降至0.6 V以下,然后会被拉低。 正电源输入引脚。工作电源电压范围为2.7 V至5.5 V。
热阻
θJA针对最差条件,即器件焊接在电路板上实现表贴封装。 表3. 热阻
封装类型 10引脚MSOP封装 θJA 137.5 单位 °C/W
ESD警告
ESD(静电放电)敏感器件。
带电器件和电路板可能会在没有察觉的情况下放电。 尽管本产品具有专利或专有保护电路,但在遇到高 能量ESD时,器件可能会损坏。因此,应当采取适当 的ESD防范措施,以避免器件性能下降或功能丧失。
相关文档
最新文档