equivalence-relations, 159-162 FIFO queues, 165-171 first-class, 177-186
线性代数术语中英文对照_第一章
线性代数术语中英⽂对照_第⼀章Chapter 1linear equation [P2] 线性⽅程coefficient [P2] 系数constant term [讲义‐P1] 常数（项）systems of linear equations (linear system) [P3] 线性⽅程组solution [P3] 解solution set [P3] 解集tuple [P3] 数组equivalent [P3] 等价equivalent system [P3] 等价系统，等价⽅程组 consistent [P4] 相容inconsistent [P4] 不相容consistent linear system 相容（有解）的线性⽅程组inconsistent linear system 不相容（⽆解）的线性⽅程组coefficient matrix [P5] 系数矩阵augmented matrix [P5] 增⼴矩阵elementary operations [P7] 初等变换elementary row operation [P7] 初等⾏变换row equivalent [P7] ⾏等价（矩阵） equivalent matrix [讲义‐P3] 等价矩阵Leading entry [P14] 先导元素entry of matrix 矩阵的元素echelon form (row echelon form) [P14] 阶梯形reduced echelon form (reduced row echelon form) [P14] 简化阶梯形Gaussian elimination [P14]脚注⾼斯消元法the elimination of variables 消元法row reduced [P15] ⾏化简pivot position [P16] 主元位置pivot column [P16] 主元列pivot [P17] 主元forward phase [P20] ⾃上（向下）阶段 backward phase [P20] ⾃下（向上）阶段basic variable [P20] 基本变元free variable [P20] ⾃由变元general solution [P21] ⼀般解，通解back‐substitution [P22] 回代法，侧转代⼊vector [P28] 向量，⽮量scalar [P28] 数量，纯量，⽆向量 parallelogram rule [P30] 平⾏四边形法则linear combination [P32] 线性组合generated (spanned) [P35] ⽣成(张成)product [P45] 乘积homogeneous systems [P50] 齐次系统，齐次线性⽅程组 trivial solution [P50] 平凡解，零解nontrivial solution [P51] ⾮平凡解，⾮零解 parametric vector form [P52] 参数向量形式 nonhomogeneous systems [P50] ⾮齐次线性⽅程组linear independent [p65] 线性相关linearly independent [P65] 线性⽆关linear transformation [P73] 线性变换domain [P73] 值域shear transformation [P76] 剪切变换contraction [P77] 压缩变换dilation [P77] 拉伸变换。
74HC
74HC/LS/HCT/F系列芯片的区别1、LS是低功耗肖特基，HC是高速COMS。
LS的速度比HC略快。
HCT输入输出与LS兼容，但是功耗低；F是高速肖特基电路；2、LS是TTL电平，HC是COMS电平。
3、LS输入开路为高电平，HC输入不允许开路， hc 一般都要求有上下拉电阻来确定输入端无效时的电平。
LS却没有这个要求4、LS输出下拉强上拉弱，HC上拉下拉相同。
5、工作电压不同，LS只能用5V，而HC一般为2V到6V；6、电平不同。
LS是TTL电平，其低电平和高电平分别为0.8和V2.4，而CMOS在工作电压为5V时分别为0.3V和3.6V，所以CMOS可以驱动TTL，但反过来是不行的7、驱动能力不同，LS一般高电平的驱动能力为5mA，低电平为20mA；而CMOS的高低电平均为5mA；8、 CMOS器件抗静电能力差，易发生栓锁问题，所以CMOS的输入脚不能直接接电源。
74系列集成电路大致可分为6大类：. 74××（标准型）；.74LS××（低功耗肖特基）；.74S××（肖特基）；.74A LS××（先进低功耗肖特基）；.74AS××（先进肖特基）；.74F××（高速）。
近年来还出现了高速CMOS电路的74系列，该系列可分为3大类：. HC为COMS工作电平；. HCT为TTL工作电平，可与74LS系列互换使用；.HCU适用于无缓冲级的CMOS电路。
这9种74系列产品，只要后边的标号相同，其逻辑功能和管脚排列就相同。
根据不同的条件和要求可选择不同类型的74系列产品，比如电路的供电电压为3V就应选择74HC系列的产品系列电平典型传输延迟ns 最大驱动电流(-Ioh/Lol)mAAHC CMOS 8.5 -8/8AHCT COMS/TTL 8.5 -8/8HC COMS 25 -8/8HCT COMS/TTL 25 -8/8ACT COMS/TTL 10 -24/24F TTL 6.5 -15/64A LS TTL 10 -15/64LS TTL 18 -15/24LVCACSLC注：同型号的74系列、74HC系列、74LS系列芯片，逻辑功能上是一样的。
数据结构与算法常用词汇
数据结构与算法常用词汇数据结构与算法Data Structures第一节绪论Section 1 Introduction数据元素data element数据对象data object数据类型data type抽象abstract*数据结构data structure*逻辑结构logical structure*物理结构physical structure*存储结构storage structure*顺序(存储结构)sequential / （storage structure）*链式(存储结构) linked （storage structure）算法分析analysis of an algorithm *渐进分析asymptotic analysis渐进复杂度asymptotic complexity 问题规模problem scope 基本语句basic statement*大O记法Big-O notation正确性correctness可读性readability鲁棒性robustness频度frequency count计算理论computability theory计算复杂性理论computational complexity theory1.*抽象数据类型abstract data type(ADT): Abstract Data Type(ADT) defines the domain and structure of the data, along with a collection of operations that access the data. It creates a user-defined data type whose operations specify how a client may manipulate the data.抽象数据类型定义了数据取值范围和表现结构，以及对数据的操作。
计算理论导论(英文版)数学基础
N-ary relation
1-ary relation 2-ary relation 3-ary relation
unary relations binary relations ternary relations
16
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5 composition
QR= {(a,b): for some c, (a,c)Q and (c,b) R }
Composition of f: AB and g:B C is a function h from A to C such that h(a)=g(f(a)).
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6 special types of binary relations
directed graph
Node Edges Notes: do not allow “parallel arrows”.
2
written
Listing Refer to other sets and properties
3
4
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Set operations
Union: AB Intersection: AB Complement: A Difference: A-B Disjoint Sets: AB=Null
29
A path in a binary relation R is a sequence (a1,..,an) for some n1 such that (ai, ai+1)R for i=1, …, n-1; this path is said to be from a1 to an. The length of a path (a1,..,an) is n. The path (a1,..,an) is a cycle if the ai’s are all distinct and also (an, a1) R .
FM1702SL中文说明书
14 接收电路 _____________________________________________________67
14.1 概述 ________________________________________________________67 14.2 信号接收过程 ________________________________________________67
7 FIFO _________________________________________________________51
7.1 概述 _______________________________________________________51 7.2 访问规则 ____________________________________________________51 7.3 控制 FIFO___________________________________________________52 7.4 FIFO 状态信息 _______________________________________________52
10.1 10.2 10.3 10.4
HARD POWER DOWN 模式 _____________________________________60 SOFT POWER DOWN 模式 _______________________________________61 STAND BY 模式 _______________________________________________61
4 数字接口 ______________________________________________________10
FPGA可编程逻辑器件芯片EP4CE15F17I8N中文规格书
LP E VENT C ONTROLInterrupt SignalsEach link port has two dedicated interrupt lines registered with the System Event Controller—a datarequest interrupt and a status interrupt. Data request interrupts are asserted with respect to FIFO condi-tions for data transfer and status interrupts are asserted when a service request status or an overflow status is set. Each of these interrupts are explained below.•Data Request Interrupt. Asserted if the FIFO is not full in transmission mode and the FIFO is not empty in reception mode. This serves as a core triggered interrupt in non-DMA mode and as the DMA interrupt request in DMA mode. Generation of this interrupt is tied to the LP_STAT.FFST (link portbuffer status bit).•Link Port Transmit Service Request Interrupt (LTRQ). Allow a disabled link port to generate an interrupt when an external access is attempted. When a link port is configured as transmitter, thetransmit service request interrupt is enabled by setting the LP_CTL.TRQMSK bit. When set, an externalreceiver can indicate to the disabled transmitter that it needs to receive data through the connected linkport. The receiver does so by driving a high level on the LP_ACK line. When the LP_ACK of the disabledtransmitter link port is detected high, a LP_STAT.LTRQ interrupt in is generated, and the transmittercan enable itself for data transfer with the receiver. Note that a pull-down on LP_ACK is required forproper function of this feature.•Link Port Receive Service Request Interrupt (LRRQ). When a link port is configured as receiver, this interrupt is enabled by setting the LP_CTL.RRQMSK bit. When set, an external transmitter can indicateto the disabled receiver that it needs to receive data through the connected link port. The transmitterdoes so by driving the first data out. When the LP_CLK of the disabled receiver link port is detected high,a LP_STAT.LRRQ interrupt in is generated, and the receiver can further enable itself for data transferwith the transmitter. Note that a pull-down on the LP_CLK signal is required for proper function of thisfeature.•Link Port Receive Overflow Interrupt (LPOVF). Generated when the receiver FIFO overflows and is enabled by setting the LP_CTL.ROVFMSK bit. This may happen if the transmitter continues to transmitdata even though the receiver has de asserted LP_ACK signal causing the receive FIFO to overflow. Enabling Link Port InterruptsA data request interrupt is fed to the System Event Controller directly and can be controlled separatelyfrom the application.Service interrupts and the overflow interrupt can be masked by setting the corresponding mask bits in LP_ CTL register, as these are OR’ed and fed to the SIC as a single LP_STAT interrupt. These interrupts are latched and stored in the associated bits of LP_STAT register. If an LP_STAT interrupt occurs, in the ISR, programs should read the LP_STAT register bits to determine the type of interrupt. Note that these bits are write-one-to-clear (W1C); writing one to the bit resets the bit and disables the corresponding interrupt.LP P ROGRAMMING M ODEL2.Install interrupt handlers for DMA and for transfer status (service request interrupt).3.Configure the link port to transmit by setting the LP_CTL bit and enable the transmit request interruptmask by setting the LP_CTL.TRQMSK bit.4.Program the link port clock divider by writing a value to the LP_DIV register.5.If using DMA stop mode/auto buffer mode, program the appropriate DMA registers.A DDITIONAL I NFORMATION:An example configuration is: DMA_ADDRSTART, DMA_XCNT, DMA_XMOD and DMA_CFG registers (Stop/Auto, Psize=1, Msize=4, interrupt generation and memory read).6.Wait for the link port receiver (connected externally) to be enabled. The application can wait for thetransmit service request interrupt to assert.7.Clear the transmit service request interrupt status by writing 1 to the LP_STAT.LTRQ bit.8.Enable DMA by setting the DMA_CFG.EN bit.9.Enable the link port by setting the LP_CTL.EN bit.10.Wait for DMA to assert a transfer completion interrupt.11.Clear the DMA interrupt source by writing 1 to the DMA_STAT.IRQDONE bit.Setting Up a DMA Receive OperationThis section describes the typical steps for using the link ports in DMA receive mode.1.Enable the link port pins in GPIO port mux using the appropriate PORT_FER and PORT_MUX registers.2.Install interrupt handlers for DMA and for transfer status (service request interrupt).3.Configure the link port for reception (clear the LP_CTL.TRAN bit) and enable the receive request inter-rupt mask by setting the LP_CTL.RRQMSK bit.4.If using DMA stop mode/auto buffer mode, program the DMA registers.A DDITIONAL I NFORMATION:An example configuration is: DMA_ADDRSTART, DMA_XCNT, DMA_XMOD and DMA_CFG registers (Stop/Auto, Psize=1, Msize=4, interrupt generation and memory write).5.If using DMA array mode/list mode, create DMA configuration data structures filled with components.A DDITIONAL I NFORMATION:An example configuration is: DMA_ADDRSTART, DMA_XCNT, DMA_XMOD and DMA_CFG registers (Array/List, Psize=1, Msize=4, Interrupt generation, memory write and fetch=4/5) andDMA_DSCPTR_NXT register (if list mode). Further program DMA configuration register (Array/List,Psize=1, Msize=4, Memory Write and Fetch=4/5) and program the DMA_DSCPTR_NXT register (if listmode).ADSP-BF60X LP R EGISTER D ESCRIPTIONS3.Configure link port for reception (clear LP_CTL.TRAN bit) and enable receive request interrupt mask(set LP_CTL.RRQMSK bit).4.Wait for the link port transmit (connected externally) to be enabled with subsequent transmission ofdata. Application can wait for receive service request interrupt to be asserted.5.Clear the receive service request interrupt status by writing 1 to the LP_STAT.LRRQ bit.6.Enable the link port by setting the LP_CTL.EN bit.7.The data request interrupt is asserted whenever there is free space in the FIFO. The application can readfrom the LP_RX register based on the FIFO conditions (1 or 2 or 3 data available) which is reflected inthe LP_STAT.FFST bit field.ADSP-BF60x LP Register DescriptionsLink Port (LP) contains the following registers.Table 28-6:ADSP-BF60x LP Register ListName DescriptionLP_CTL Control RegisterLP_STAT Status RegisterLP_DIV Clock Divider ValueLP_TX Transmit BufferLP_RX Receive BufferLP_TXIN_SHDW Shadow Input Transmit BufferLP_TXOUT_SHDW Shadow Output Transmit BufferControl RegisterThe LP_CTL register provides LP interrupt masking, selection of transfer direction, and link port enable.。
HiSIM_HV_1.2.1_Users_Manual
10
4 Charges
12
5 Drain Current
15
6 Threshold Voltage Shift
16
6.1 (I) Short-Channel Effects . . . . . . . Байду номын сангаас . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
References
80
4
HiSIM HV 1.2.1 Copyright c 2010 Hiroshima University & STARC: confidential
1 LDMOS/HVMOS Structures
HiSIM (Hiroshima-university STARC IGFET Model) is the first complete surface-potential-based MOSFET model for circuit simulation based on the drift-diffusion theory [1], which was originally developed by Pao and Sah [2]. The model has been extended for power MOSFETs by considering the resistance effect explicitly, which is named HiSIM HV. There are two types of structures commonly used for high voltage applications. One is the asymmetrical laterally diffused structure called LDMOS and the other is originally the symmetrical structure, which we distinguish by referring to it as HVMOS. However, the asymmetrical HVMOS structure is also possible. HiSIM HV is valid for modeling all these structure types [3, 4]. The most important features of LDMOS/HVMOS devices, different from the conventional MOSFET, are originating from the drift region introduced to achieve the sustainability of high voltages. By varying the lengh as well as the dopant concentration of the drift region, various devices with various operating biase conditions are realized as shown in Fig. 1 for the LDMOS structure.
模糊关系及推论
的兩個
其 中 t(. , .) 是 的 運 算 子 。 那 麼 用 “ 最 大 - 最 小 合 成 (max-min operation)”的運算子可將 P 及 Q 合成為
R X 1
x1
0.8
x2
1
x3
R Y 0.9
y1
0.5
y2
0.8
y3
1
y4
1
y5
1 1 1 1 1 ( R X ) ( X Y ) 0.8 0.8 0.8 0.8 0.8 1 1 1 1 1 0.9 0.5 0.8 1 1 ( R Y ) ( X Y ) 0.9 0.5 0.8 1 1 0.9 0.5 0.8 1 1
模糊集合與模糊關係的合成
• 令 A 是定義在 X 上的一個模糊集合，R 是定義在 X Y 上的一個 模糊關係，則我們以符號 B A R 代表模糊集合 A 與模糊關係 R 的合成，定義為：
B ( y ) maxmin A ( x ), R ( x, y )
xX
max(0.9,0.4,1,0) = 1 max(0,0,0.7,0.8) = 0.8
• 令R12*為將 R12 柱狀擴充至 ( X1 X 2 X 3 ) 所形成的關係，R*3 為 將 R3 柱狀擴充至 ( X1 X 2 X 3 ) 所形成的關係，亦即：
* * R12 R12 ( X 1 X 2 X 3 ) R3 R3 ( X 1 X 2 X 3 ) R* ( x1 , x2 , x3 ) R* ( x1 , x2 , x3 ) ( x1, x2 , x3 )
离散数学北京邮电大学
• §3.5: Primes and Greatest Common Divisors • §3.6: Integers & Algorithms
– Alternate bases, algorithms for basic arithmetic
Algorithm Characteristics
Some important general features of algorithms: • Input. Information or data that comes in. • Output. Information or data that goes out. • Definiteness. Algorithm is precisely defined. • Correctness. Outputs correctly relate to inputs. • Finiteness. Won‟t take forever to describe or run. • Effectiveness. Individual steps are all do-able. • Generality. Works for many possible inputs. • Efficiency. Takes little time & memory to run.
– Example assignment statement: v := 3x+7 (If x is 2, changes v to 13.)
• In pseudocode (but not real code), the expression might be informally stated:
天龙DENON AVR-1705 1685 AV环绕接收机服务手册
(2) Playback the color-bar 75% of the Test Disc (Title 12) using the DVD Video Player, and check that Y and C levels of the S terminal output are within the specified output levels. If they are out of the specified levels, adjust with the variable resister inside of the unit.
(7) Adjust the Variable Resistors of other channels in the same way.
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IndexAbstractdatatype(ADT),127-195abstractclasses,163classes,129-136collectionsofitems,137-139creating,157-164defined,128duplicateitems,173-176equivalence-relations,159-162FIFOqueues,165-171first-class,177-186genericoperations,273indexitems,177insert/removeoperations,138-139modularprogramming,135polynomial,188-192priorityqueues,375-376pushdownstack,138-156stubs,135symboltable,497-506ADTinterfacesarray(myArray),274complexnumber(Complex),181existencetable(ET),663fullpriorityqueue(PQfull),397indirectpriorityqueue(PQi),403item(myItem),273,498key(myKey),498polynomial(Poly),189point(Point),134priorityqueue(PQ),375queueofint(intQueue),166
stackofint(intStack),140symboltable(ST),503textindex(TI),525union–find(UF),159Abstractin-placemerging,351-353Abstractoperation,10Accesscontrolstate,131Actualdata,31Adapterclass,155-157Adaptivesort,268Address,84-85Adjacencylist,120-123depth-firstsearch,251-256Adjacencymatrix,120-122Ajtai,M.,464Algorithm,4-6,27-64abstractoperations,10,31,34-35analysisof,6average-/worst-caseperfor-mance,35,60-62big-Ohnotation,44-47binarysearch,56-59computationalcomplexity,62-64efficiency,6,30,32empiricalanalysis,30-32,58exponential-time,219implementation,28-30logarithmfunction,40-43mathematicalanalysis,33-36,58primaryparameter,36probabilistic,331recurrences,49-52,57recursive,198runningtime,34-40search,53-56,498stepsin,22-23SeealsoRandomizedalgorithmAmortizationapproach,557,627Arithmeticoperator,177-179,188,191Array,12,83binarysearch,57dynamicallocation,87
andlinkedlists,92,94-95merging,349-350multidimensional,117-118references,86-87,89sorting,265-267,273-276andstrings,119two-dimensional,117-118,120-124vectors,87visualizations,295SeealsoIndex,arrayArrayrepresentationbinarytree,381FIFOqueue,168-169linkedlists,110polynomialADT,191-192priorityqueue,377-378,403,406pushdownstack,148-150randomqueue,170symboltable,508,511-512,521Asymptoticexpression,45-46Averagedeviation,80-81Average-caseperformance,35,60-61AVLtree,583
Btree,584,692-704external/internalpages,6954-5-6-7-8tree,693-704Markovchain,701remove,701-703search/insert,697-701select/sort,701Balancedtree,238,555-598Btree,584bottom-up,576,584-585height-balanced,583indexedsequentialaccess,690-692performance,575-576,581-582,595-598randomized,559-564red–black,577-585skiplists,587-594splay,566-571
7277282-3,5842-3-4,572-576,584,593-594Batcher’sodd–evenmergesort,455-459networks,461-466shuffling,464-466Bayer,R.,692-693Bentley,J.L.,336Bernoullitrial,87-88Big-Ohnotation.SeeO-notationBin,428Binarylogarithm,40-42Binaryrepresentation,50-51,602,636Binarysearch,56-59,682asdivide-and-conqueralgo-rithm,216-217indeximplementations,527-530interpolationsearch,522-523symboltables,519-523,527-530text-stringindex,682Binarysearchtree(BST),249,531-536countfield,547,551-552,596defined,531digital,637-640duplicatekeys,536insertion,542-546,560,573-575,580-582join,550-552,563-564memory,552-553nonrecursive,535-536partitioning,547-548pathlength,538perfectlybalanced,555-557performance,537-541andquicksort,536randomized,559-564,595-598red–black,577-585remove,548-551,563-564rotation,543-544,566-569search/insert,531,533-539,545,561-562select,547-548sort,534-535splay,566-571,595-598text-stringindex,681-682andTSTs,6762-3,5842-3-4,572-576,584,593-594visit,535worst-case,539-540,555SeealsoBalancedtree;SymboltableBinarytree,230-233binarysearchcomparisons,522-523complete,239,381-382andhashing,633heap-ordered,381,393,406-408joinoperation,407-408linksin,230-231mathematicalproperties,236-239operations,232pathlength,237printing,247recursivealgorithms,246-251tournamentconstruction,248-249SeealsoBinarysearchtree;TrieBinomialdistribution,43Binomialqueue,406-415defined,408insert,409-410join,411-413performance,413-415removethemaximum,413-415Binomialtree,407Bin-spanheuristic,433Birthdayproblem,612Bit,71,420binaryquicksort,424-426bottom-upmergesort,362bitmethod,635-636,661Bitonicsequence,352Blocksorting,488-489Booleandatatype,71Boundingafunction,47,48upper/lowerbound,62-64Breadth-firstsearch,253,256-257Brent,R.,631Bubblesort,288-289,290-294Bucket,428Bug.SeeErrorButterflynetwork,465Byte,417,419-420Bytecode,34
Cache,688,719Cast,type,72,155Ceilingfunction,43Characterdatatype,71-72Childnode,229Circularlist,92,102-104headandtailconventions,102Josephuselection,95-96memoryallocation,109mergesort,367-368Class,70,74-83,129-136abstract,163adapter,155-157concretedatatypes,134-135extended,82instantiation,75members,76-77public/privatemembers,129sortmethods,272Classpaths,161-162Client,81,108-110implementations,128-129,162-164interface,141,158Cloning,182-185Closest-pointcomputation,90Cluster,617-620,623Coin-flippingsimulation,87-88Combine-and-conquerapproach,215mergesort,361-363Comparator,460-461,488compareTomethod,530Complex(complexnumber)ADTinterface,181Complexnumber,178-182Complexrootsofunity,179-180Computationalcomplexity,62-64Connectivityproblem,7-11,158-161