Signed Digit Counters with Neural Networks

Signed Digit Counters with Neural NetworksSorin Cotofana and Stamatis VassiliadisDelft University of TechnologyElectrical Engineering DepartmentMekelweg4,2628CD DelftThe Netherlandsemail:Sorin,Stamatis@Plato.ET.TUDelft.NLAbstract:In this paper we investigate no learning based neural networks for signed digit counters.Wefirst assume radix-signed digit inputs and prove that a can be implemented with a depth-neural network with at most neural gates and the maximum weight and fan-in values in the order of.Under the same assumption we investigate counters and we propose an explicit depth-(implicit depth-)neural network for such counters.Finally we assume radix-signed digit input representation and we prove that a counter can be implemented with an explicit depth-neural network with the size measured in terms of neural gates in the order of and with the maximum weight and fan-in values both in the order of.1IntroductionMultiplication schemes for VLSI implementations can be divided broadly in two categories,namely array and parallel multiplication schemes[1].Both schemes reduce a matrix of partial products to a single row representing the product via counters[1].Thus far counters have been mainly implemented with Boolean gates[2,3,4,5,6,7]. Currently other possibilities exist in VLSI for the imple-mentation of Boolean functions using neural threshold devices in CMOS technology[8,9,10].Such a threshold device corresponds to the Boolean output neuron intro-duced in the the McCulloch-Pitts neural model[11,12] and computes a Boolean function such that:sgn if ifwhere the set of input variables and weights are defined respectively by,andassociated with the inputs.It is well known that an arbitrary Boolean function can be computed using AND,OR and NOT logical gates with no restriction in size.Given that the McCulloch-Pitts neuron model can also compute the logical AND, OR and NOT[13],it can be used as the functional ele-ment for feed-forward multi-layer neural networks[13]to compute deterministically and with no learning the out-put of Boolean functions.A number of investigations have been reported regarding the neural networks imple-mentation with no learning of arithmetic operations such as addition,multiplication,see for example[14,15,16], present in most hardwired computational engines.Re-cently counters implemented with neural gates have been proposed in[17]and it has been shown that for com-mon dimension of operands neural multipliers,based on such counters,outperform neural multiplication schemes based on multi operand addition[18]in network size for equal delay.In this paper we investigate neural network implement-ations of parallel counters which assume signed digit[19] inputs and produce signed digit outputs.The main contri-butions of the paper can be summarized by the following:A radix-signed digit counter can beimplemented with a depth-neural network with at most neural gates.The maximum weight and fan-in values are in the order of.A radix-signed digit counter can be implemen-ted with an explicit depth-neural network built with neural gates.The maximum weight is and the maximum fan-in is.A radix-signed digit counter can be imple-mented with an implicit depth-neural network built with neural gates.The maximum weight is and the maximum fan-in is.Assuming radix-signed digit inputs acounter can be implemented with an explicit depth-neural network with the size measured in terms ofneural gates in the order of.The maximumweight value is the order of and the maximumfan-in value is in the order of.It should be noted that the neural gates our schemesrequire are readily implementable in currently availabletechnologies[10].The implication here is that all of theTable1:Digit Codification forschemes we present are not only theoretical but also real-istic from the implementation point of view.The paper is organized as follow:First we assumeradix-signed digit inputs and in Section2we introducecounters and in Section3explicit depth-and implicit depth-counters.The Section4con-cludes the presentation by investigating the more generalissue of signed digit counters assuming a representa-tion radix higher than.2Signed Digit Coun-tersA counter is a circuit which assumesinputs and produces out-puts.In the case of Boolean inputsthe counter outputs provide the binary codification of thevalue of the input sum.Given that in our in-vestigation we assume radix-signed digit inputs,i.e.,gates.On the second level we needone gate per each counter output and because each out-put is represented by two Boolean signals this will countup to neural gates on the second level.Con-sequently the entire network can be constructed with atmost neural gates.Obviously the weightand fan-in values are in the order of.Remark1It is also possible to implementradix-signed digit counters with the implementationmethod we introduced in[23]for periodical symmetricBoolean functions.In this case the network depth in-creases to but the network size decreases toneural gates.In the following we present as an example,to be uselatter on in the signed digit counter design,the neuralnetwork implementation of a counter with radix-Table2:Truth Table of Signed Digit Counter signed digit inputs.A truth table1of such a counter is presented in the Table2under the assumption that the signed digits are represented as in the Table1.From the Table2we can deduce the following equa-tions for the counter outputs2:(3)(4)(5)(6)(7)(8)(9)(10) These equations can be implemented in depth-with the method described in the Lemma1.The neural network implementation is graphically represented in the Figure1. Note that the counter is implemented with neural gates, the maximum fan-in is and the maximum weight value is.The logarithmic depth and size implementation of the radix-signed digit counter is pictorially described in the Figure2.We note here that this counter imple-mentation which requires a delay which logarithmically depends on can be very attractive from the implementa-tion point of view if the network size is the most important design issue.and,refer to signals that need to be computed by one neural gate in the digit position,with being the neural value and being the counter type for which the signals are computed.The straightforward implementation of this two stages signed digit counter scheme with the receipt in the Theorem1leads to a depth-network.However we can reduce the network depth to if the counter cascading is done using implicit computations.Lemma2Any Boolean symmetric functiondescribed as being equal with if,,and with otherwise can be implemented by an implicit depth-feed-forward neural circuit with the size measured in terms of neural gates in the order of as follows:(11)Proof:To verify Equation(11)it will be shown thatis indeed when the sum lies inside an in-terval for a specific and that is when there is no such that for all,. Case1:for a specific,.In this case for,for,for,andfor.Therefore, i.e.,is as needed.Case2:There is no,such that. In this case there are three possibilities:for a given,,,and.We will prove that in all of them is as needed.In thefirst sub-case for,for,for,and for.Therefore,i.e., is.In the second sub-case forand for.Consequently, i.e.,is.In the last sub-case forand for.Consequently, i.e.,is.Given that any can be obtained with a neural gate com-puting and any with a neural gate com-puting the entire network is built with neural gates,i.e.,the implementation cost is in the order of.All the input weights are and the fan-in for all the gates is.The following theorem introduce a depth-implementa-tion of the radix-signed digit counter.Theorem2The Sum and the Carry of a radix-signed digit counter at digit position are determ-ined by the following neural network:sgnsgnsgnsgnwithsgnsgnsgnsgnsgnsgnsgnsgnProof:From the equations describing the behavior of the signed digit counter outputs at the digit position we can derive the following implicit depth-implementation:Generally speaking the equations describing the sum and the carry of the signed digit counter are:sgnsgnsgnsgnGiven that inside the signed digit counter the signed digit counter is receiving as inputs the im-plicitly computed signals,and,the Equations in the theorem enun-ciation follow with proper substitutions.Remark2The implementation of the radix-signed digit counter presented in the Theorem2is explicit depth-. The network cost is neural gates.The maximum weight is and the maximum fan-in is.Remark3The scheme can be transformed into an impli-cit depth-as follow:The implicit depth-network implementing the signed digit counter has a cost of neural gates.This im-plicit scheme leads to an increase in the fan-in and weight values of the counter which takes as input the sum digit because the value of the sum is carried by signals instead of.There is also a neural value to be carried between different levels of counters.In the worst case scenario the next counter will get as inputs sum digits and carries.In this case the maximum weight is and the maximum fan-in is.4Signed Digit CountersThefinal issue to be addressed in this paper is the con-struction of the general case of signed digit counters with being an arbitrary integer number.The construc-tion idea is to assumesfirst a a signed digit counter reduction in a single level.The outputs of this counter are fed into a second counter to produce the twooutput signals.Given that by augmenting the number ofinputs the number of outputs also increases,after in-put counters it is not possible to construct a signeddigit counter in two levels.As it was stated before the signed digit counter is implemented as a cascade of two counters,namely a signed digit counter and asigned digit counter.As a matter of fact each one of this internal counters implements a logarithmic compression of its inputs in one level of neural gates.The implement-ation technique proposed for the implicit calculation of the outputs of the signed digit counter can be easily generalized to any signed digit counter.Given that a logarithmic compression can be achieved in one level of gates,the delay for a signed digit counter can be expressed as:(12) By recursive application of this technique we can compute the delay that corresponds to the implementation of the general signed digit counter.However it might be of practical and theoretical interest to provide an answer to the following research question:Is there any other possibility to implement the gen-eral signed digit counter always in explicit depth-?In the remaining of this section we prove that such an explicit depth-implementation can be always achieved if a representation radix“big enough”is assumed for the counter input digits.First we have tofind out what does “big enough”representation radix means and in order to do so we have to investigate the following issue: How big has to be the representation radix we have to assume for the inputs in order to be able to perform-digit“totally parallel”addition?Avizienis investigated this issue in[19]but from thedual point of view,i.e.,he started with a given radix-and investigated the maximum number of digits that can be ad-ded in“totally parallel”mode within that radix-signed digit representation.In our case the number of digits is given by the number of inputs and we want tofind out the minimum value for the radix-that would aloud the sim-ultaneous addition of signed digits into a“totally par-allel”mode.We answer to this question in the following lemma.Lemma3The simultaneous addition of signed digitscan be done in a“totally parallel”mode by assuming a representation radix greater or equal with.Proof:The simultaneous addition of signed digits can be done in a way that is very much alike the addi-tion of two digits.Therefore in order to add the digitsin a“totally parallel”mode we havefirst to produce an intermediate sum digit and a transport digit that satisfy the Equation(13)and also the constraint that the subsequent addition in the Equation(14)that gives the real value of the sum digit in the position can be done anytime without generating a carry-out.(13)(14)We have tofind not only the value of the radix for which the computation in the Equations(13,14)can be done,but also the maximum absolute values that we can allow for the intermediate sum digit and the transport digit.Speaking in greatest absolute values the digit po-sition is irrelevant than we can skip it in the following. In order to have data consistency we have to assume thatand.Therefore,if mapped in absolute maximal values, the Equations(13,14)become:(15)(16) From the Equations(15,16)we can derive the following inequalities:.This two assumptions together with the Equation(17)and depending if we assume an odd radix or an even one,lead to or. Therefore in order to perform simultaneous addition ofsigned digits in a“totally parallel”mode we have to use a representation radix greater or equal with.As follows from the Lemma3if a radix of is assumed we can represent the sum of all the input digits on two output digits.Note that in this case there will be no carries transmitted between the counters applied at adjacent digit position.We introduce the depth-signed digit counter scheme in the following theorem. Theorem3Assuming radix-signed digit repres-entation the counter can be implemented with an ex-plicit depth-neural network with the size measured in terms of neural gates in the order of.The maximum weight value is the order of and the maximum fan-in value is in the order of.Proof:Assume that the radix-signed digit in-puts of the counter are and all the digits ,can take value within the symmet-ric digit setGiven that the radix-allows for“totally paral-lel”addition of signed digits we can compute the sum of the input digits as being equal with.Obviously both and depend on the value of.The maximum absolute value that can be assumed by can be derived under the as-sumption that all the digits are.This will lead to and consequently to a variation domain for equal to.Because the digits involved into the computation of belong to the set we need bits for their's complement codification[1].Under this codific-ation each digit is represented by a-tuple.Each of this bits will take part into the computation of with a weight that correspond to its position inside the digit representation and following the's complement codific-ation convention.With this assumption the expression of becomeAssuming all of these the sum digit and the carry di-git can be expressed function of.Because of the weighted manner we did the computation of the sum, the functions and are symmetric in all of the input variables3and consequently they can be implemen-ted using the method described in the Lemma1with a depth-neural network.Because can assume any digit value in the set we need bits for its codification. Therefore in order to compute we have to computesymmetric Boolean functions,.For the implementation of each symmetric Boolean function we need neural gates in thefirst layer of the network,being the num-ber of intervals in the definition domain where as-sume the value of,and neural gate in the second layer. Consequently the computation of the function can be done with:(18)neural gates.The definition domain for is.Given that the changes of the values of can appear only in certainfixed spots common for all of them we can use the gate sharing concept we in-troduced in[22].In this way the gates associated to the upper limit of the intervals can be shared between the net-works implementing the Boolean functions.This fact leads to an upper bound of3The number of input Boolean variables is given by the product of the number of digits involved into the computation and the number of bits we need in order to represent a digit in,i.e.,.network.The second level of the network has to con-tain one gate for each,i.e.,bit position in the's complement representation of,then it can be built withgates.Therefore the network computing the sum digit as can be built with at most.Asymptotically speaking this leads to an implementa-tion of the signed digit counter with a depth-network having the number of neural gates in the order of.The maximum weight value is upper bounded by the dimension of the definition domain,i.e.,, and consequently it is in the order of.The maximum fan-in value is imposed by the gates in the second level of the network which take as inputs all the bits participating into the computation,i.e.,,and some outputs of the gates in thefirst level. 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