BSS84中文资料

handbook, halfpage
−600
MLD196
handbook, halfpage
60
MLD198
ID (mA) −400
RDSon (Ω) 40
VGS = −2.5 V −3 V −4 V −5 V
−200
20 −7.5 V −10 V
0 0
−2
−4
−6
−8 −10 VGS (V)
0 −1
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDS VGSO ID IDM Ptot Tstg Tj PARAMETER drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature operating junction temperature Tamb ≤ 25 °C; note 1 open drain CONDITIONS − − − − − −65 − MIN. MAX. −50 ±20 −130 −520 250 +150 150
Marking code: SP g
handbook, halfpage
BSS84
PINNING - SOT23 PIN 1 2 3 SYMBOL g s d DESCRIPTION gate source drain
3 d
s 1 Top view 2
MAM188
Fig.1 Simplified outline and symbol.
1997 Jun 18
4
元器件交易网
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
BSS84
handbook, halfpage
1.2
handbook, halfpage
(1)
1.8
MLD194
k
k
(2)
1.0
1.4
0.8
1.0
0.6 −50
0
50
100
Tj (°C)
150
0.6
−50
0
50
100
Tj (°C)
150
V GSth at T j k = ------------------------------------V GSth at 25 ° C ID = −1 mA; VDS = VGS.
Pδ=tp T NhomakorabeaDC
100 ms
tp
0 0 50 100 150 200 Tamb (°C)
t T
−1
−1
−10
VDS (V)
−102
δ = 0.01. Tamb = 25 °C. (1) RDSon limitation.
Fig.4 Power derating curve.
Fig.5 DC SOAR.
R DSon at T j k = ---------------------------------------R DSon at 25 ° C (1) ID = −130 mA; VGS = −10 V. (2) ID = −20 mA; VGS = −2.4 V.
Fig.10 Temperature coefficient of gate-source threshold voltage.
Fig.3 Input and output waveforms.
handbook, halfpage
300
MLD199
−103 handbook, halfpage ID (mA) −102 (1)
MLD251
Ptot (mW)
tp = 10 µs 100 µs 1 ms
200
10 ms
100
−10
VGS = 0; Tj = 25 °C; f = 1 MHz. Tj = 25 °C.
Fig.6
Capacitance as a function of drain source voltage; typical values.
Fig.7 Typical output characteristics.
80
MLD191
handbook, halfpage
−600 ID
MLD197
C (pF) 60
VGS = −10 V −7.5 V
−6 V
(mA) −400 −5 V
40 Ciss 20 Coss
−200
−4 V
−3 V
Crss 0 0 −10 −20 VDS (V) −30
−2.5 V 0 0 −2 −4 −6 −8 −10 −12 VDS (V)
元器件交易网
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
FEATURES • Low threshold voltage • Direct interface to C-MOS, TTL, etc. • High-speed switching • No secondary breakdown. APPLICATIONS • Line current interrupter in telephone sets • Relay, high speed and line transformer drivers. DESCRIPTION P-channel enhancement mode vertical D-MOS transistor in a SOT23 SMD package. CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. QUICK REFERENCE DATA SYMBOL VDS VGSO VGSth ID RDSon Ptot PARAMETER drain-source voltage (DC) gate-source voltage (DC) gate-source threshold voltage drain current (DC) drain-source on-state resistance total power dissipation ID = −130 mA; VGS = −10 V Tamb ≤ 25 °C open drain ID = −1 mA; VDS = VGS CONDITIONS − − −0.8 − − − MIN.
−10
−102
ID (mA)
−103
Tj = 25 °C. VDS = −10 V; Tj = 25 °C.
Fig.9 Fig.8 Typical transfer characteristics.
Drain-source on-state resistance as a function of drain current; typical values.
BSS84
UNIT V V mA mA mW °C °C
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient CONDITIONS note 1 VALUE 500 UNIT K/W
MAX. −50 ±20 −2 −130 10 250
UNIT V V V mA Ω mW
1997 Jun 18
2
元器件交易网
Philips Semiconductors
Product specification
P-channel enhancement mode vertical D-MOS transistor
BSS84
handbook, halfpage
VDD = −40 V
handbook, halfpage
10 %
INPUT 90 %
10 %
0V −10 V ID 50 Ω
MLD189
OUTPUT 90 % ton toff
MBB690
Fig.2 Switching time test circuit.
Note to the Limiting values and Thermal characteristics 1. Device mounted on a printed-circuit board. CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL V(BR)DSS VGSth IDSS PARAMETER drain-source breakdown voltage gate-source threshold voltage drain-source leakage current CONDITIONS VGS = 0; ID = −10 µA VDS = VGS ; ID = −1 mA VGS = 0; VDS = −40 V VGS = 0; VDS = −50 V VGS = 0; VDS = −50 V; Tj = 125 °C IGSS RDSon yfs Ciss Coss Crss ton toff gate leakage current drain-source on-state resistance forward transfer admittance input capacitance output capacitance reverse transfer capacitance VDS = 0; VGS = ±20 V VGS = −10 V; ID = −130 mA VDS = −25 V; ID = −130 mA VGS = 0; VDS = −25 V; f = 1 MHz VGS = 0; VDS = −25 V; f = 1 MHz VGS = 0; VDS = −25 V; f = 1 MHz VGS = 0 to −10 V; VDD = −40 V; ID = −200 mA VGS = −10 to 0 V; VDD = −40 V; ID = −200 mA MIN. −50 −0.8 − − − − − 50 − − − − − TYP. − − − − − − − − 25 15 3.5 MAX. − −2 −100 −10 −60 ±10 10 − 45 25 12 − − UNIT V V nA µA µA nA Ω mS pF pF pF