A 0.8V 64×64 CMOS imager with integrated sense-and-stimulus pixel for artificial retina

A 0.8V 64x64 CMOS Imager with Integrated Sense-and-Stimulus Pixel for Artificial Retina ApplicationsChih-Lin Lee and Chih-Cheng HsiehSignal Sensing and Application LaboratoryDepartment of Electrical Engineering, National Tsing Hua UniversityHsinchu, Taiwan, R.O.CEmail: g9761571@.twAbstract —A 0.8V 64x64 CMOS Image Sensor (CIS) array with integrated sense-and-stimulus (SAS) pixel is presented in this paper. The in-pixel photon-to-biphasic-current converter (sense) and balanced current-mode stimulator (stimulus) are proposed to achieve a high integration and low power solution for high-resolution vision recovery. Two operation modes as programming (PG) mode and implanted (IP) mode are integrated in this design for multiple purposes. In PG mode, the output pattern of current stimulator array is programmable with external addresses for patterned electrical stimulus experiments of retina. In IP mode, the chip is fully functional with minimized number of I/O as 4 optimized for implant operation. A 64x64 SAS pixel array with 30x30 um2 pixel size has been designed and fabricated in TSMC 0.18um CIS technology. Measurement results show a 0.01uA/lux conversion gain and the maximum driving capability of biphasic neural stimulation current pulse is 10μA with a 10kΩ electrode model. It achieves the highest array resolution as 4096 pixels operated at 0.8V, 19.5fps, and 9.6mW.I.I NTRODUCTIONOR the blind people with age related macular degeneration (AMD) and retinitis pigmentosa (RP), blindness results from loss of photoreceptors, but other retinal neurons maintain an active connection to the brain [1]. In previous works, MOS image sensors based on epiretinal and subretinal implants to restore useful eyesight have been proposed and applied for helping blind disease. Over 1000 pixels with an area less than 5x5mm2 are needed to provide a useful vision. A retinal stimulator needs several key features in order to be useful: low power consumption, small size, long lifetime, reliability and few external components [2]. The goal is to stimulate the healthy retinal neurons for reconstructing the vision patterns using a biphasic current pulses. The pulse frequency modulation (PFM) photo sensor has many advantages such as asynchronous operation, digital output, wide dynamic range and low voltage operation [3]. A inverter-based PFM sensor with in-pixel biphasic current driver has been reported in [4]. Lower power supply voltage provides longer battery life and less heat generates which can protect the eye ball.In this work, a 64×64 pixels comparator-based PFM CIS array with in-pixel biphasic current output, which can replace the function of damaged retinal cell, has been proposed. For image sensors, the pulse-modulation-based (PM) readout circuit, such as the pulse-frequency-modulation (PFM) image sensor, converts the photo-generated charge difference of sensor node to modulated output. After that, the in-pixel biphasic current pulses generator and electrode will be implemented to achieve an on-chip photon-to-biphasic current conversion for neural stimulation application. The comparator-based PFM CIS comparison is designed to achieve a better uniformity compared to previous design of inverter-based PFM CIS [4]. Another advantage of comparator-based PFM CIS is that adjusting the reference voltage node of the comparator also can easily control the gain response of the PFM CIS. The block diagram of proposed chip and the signal conversion in the pixel are shown in Fig.1.The outline of this paper is as follow. In section II, the architecture of the pixel is described. In section III, functions of the chip’s operation mode are being described. Then, the measurement results are summarized in section IV. Finally, the conclusions are drawn in section V.II.C HIP A RCHITECTURE AND O PERATION M ODEThe proposed CIS chip provides two operation modes as programming (PG) mode for the stimulus experiment and implanted (IP) mode for the in vivo operation. The detailed descriptions are as follow:A.Programming ModeAn example with programming pattern “heart” is shown in Fig.2. In PG mode, the sensor block is disabled and the biphasic current output stage is keep enable. The pixels of arbitrary pattern are addressed by programming external signal. The H and V decoder in PG mode are used to program the pattern. It consists of shift register arrays to carry the programming data in sequentially accordance with a clock signal. The proposed PG mode provides an effective solution of patterned electrical stimulus experiments of retina. The amplitude of the biphasic current pulse is also adjustable by varying the external bias level.F IEEE Asian Solid-State Circuits ConferenceNovember 14-16, 2011 / Jeju, KoreaBlock diagram of a pixel circuit for biphasic current pulse stimulationBiphasic Current driverElectrodeOutputFig.1 Block diagram of the proposed chipFig.2 An example of programming modeB. Implantation ModeFor the applications of artificial retina, in vivo operation is inevitable. Therefore, a retina chip has to be realized with a minimum number of input/output (I/O) nodes. In IP mode, all signals such as digital control clocks, addressing, and analog biasing voltages are generated internally on chip. Thus, only four I/Os (power, ground, system clock, and biphasic-reference voltage) need to be connected to the chip. For power limitation of in vivo operation, the stimulus currents output single row at a time progressively. The total I/O numbers for different modes are summaries in Table I. With proper sharing design of interface, the proposed chip is fully functional with only 4 I/Os, that is, 4 external wires in IP mode.TABLE IPG Mode IP Mode I/O number 14 4III. SAS P IXEL A RCHITECTURE AND C IRCUITA 0.8V 64x64 CMOS Image Sensor (CIS) array with integrated sense-and-stimulus (SAS) pixel is presented. The pixel consists of two components: comparator-based PFM photo sensor and biphasic current generator which includes a frequency-to-voltage converter.A. Comparator-based PFM photosensorThe schematic of the proposed PFM photo sensor cell is shown in Fig. 3. It is composed of a photodiode, a comparator, a reset transistor Mr, and a feedback loop with a delay chain (inverter chain). The comparator converts the difference between the local luminance signal V pd and threshold terminal V th to the PFM circuit’s output. When V pd is lower than V th , the output changes the state and is feedback through a delay chain to reset the sensor node. It results in a pulse generation and the frequency is proportional to the light intensity. The delay chain is used to implement the necessary reset pulse width and maintain the oscillation condition of the loop. Since the full-well of sensor node is self-reset and re-used through the feedback loop, the dynamic range of PFM sensor is much higher than the conventional image sensor. The ultra-low voltage operation feature of the inverter-based PFM image sensor has been demonstrated in [4], where it was operated under a 0.6-V power supply voltage. But the output frequency of inverter-based PFM depends the threshold of the inverter which leads to the possibility mismatch errors. The comparator-based design generates output frequency with a better uniformity relied on amplifier’s gain instead of device’s threshold voltage, but it requires a higher operational supply as 0.8V. A tunable front-stage gain is also achieved by adjusting the voltage of V th . With this front-stage tunable gain, the dynamic range and sensor SNR can be optimized depends on applications.Biphasic current generatorAn in-pixel frequency-to-voltage (F-V) converter followed by a voltage-to-biphasic-current generator is proposed to provide the electric stimulus. As shown in Fig. 3, the F-V converter switches the current I sw and integrates the charge on the capacitor C int. An adjustable integration slope on capacitor C int is achieved by scaling the current I sw. Through the level shifter (M psf), the converted voltage is then fed to the voltage controlled current source. The generated current is then mirrored to as a current sink and a source of electrode, respectively. Optimized matching between the negative and positive current level is important to deliver a good charge balance [5]. Charge balancing is a major concern in functional electrical stimulation, since any excess charge accumulation over time leads to electrolysis with electrode dissolution and tissue destruction [6]. The biphasic pulse width, polarity, and output rate are adjustable by controlling the timing of the φ1 and φ2. After stimulation, the electrode potential value is then pullback to the reference voltage V ref by turning on the switch SW ref through the clock φ3. It removes the charge residue on the electrode after every stimulation cycle to avoid the neuron memory effect and possible physiological damage.IV.P ROTOTYPE C HIP AND M EASUREMENT R ESULTThe microphotograph of the fabricated chip (3 mm × 3 mm) in TSMC 0.18 μm CMOS image sensor (CIS) technology is shown in Fig. 4. The pixel layout is shown in Fig. 5. Each 30x30 μm2 pixel size contains a 300μm2 n-diffusion/p-substrate photodiode results in a 33.3% fill factor. An in-pixel electrode pad window is embedded for further electrode formation.Figure 6 shows the measured sensitivity of the comparator-based PFM sensor operated at 1.8V and 0.8V, respectively . The response between input light intensity (lux) and output frequency (Hz) is linear as expectation. It shows a higher lux-to-Hz gain at 0.8V due to the lower reset level and smaller signal range fed to comparator. The measured conversion gain (frequency/illumination) is 13.8 (Hz/lux) and 8 (Hz/lux) at 0.8V and 1.8V supply voltage, respectively. Fig. 7 shows the output current of the biphasic current generator with an electrode model (10kΩ) under illumination. The supply voltage determines the available swing range of the biphasic pulse. The maximum driving capability of biphasic neural stimulation currents are ±50μA and ±10μA at 1.8V and 0.8V supply (with 10kΩ loading), respectively. The reconstructed images from biphasic current output level is shown in Fig. 8.It shows that the output pattern is quite clear which potentially help restoring vision with high resolution. The image of 0.8V operation is quite noisy due to the small available signal swing. The measured results of the fabricated prototype chip are summarized in Table II. The image quality, power consumption, and driving capability of biphasic current output are all tradeoff between 1.8V and 0.8V operationFig.4 Microphotograph of the fabricated chipFig. 5 Pixel layoutBasic circuit of the SAS pixelFig. 6 Sensitivity of the PFM photosensorFig. 8 The captured image from prototype chip (a) Vdd=1.8V (b)Vdd=0.8VV. C ONCLUSIONWe are developing a retinal chip in hopes of restoring vision to the patients. The design of a 4096 pixels comparator-based PFM CMOS image sensor array with in-pixel biphasic current pulse driver has been presented. The main work is a photon-to-biphasic current conversion system on chip operated at 1.8V and 0.8V supply voltage. A tunable front-gain by adjusting the reference voltages of comparator is implemented. The resulting biphasic pulse width, polarity, and output rate are all tunable depends on applications and environments.TABLE IISpecificationsTechnology TSMC CIS 0.18-umSupply voltage 1.8V0.8VNumber of pixels64x64 Pixel size30 μm × 30 μmFill factor 33.3% Frame rate19.5fps PFM output frequency100Hz~18kHzPower consumptionPixel (without current driver)4.2uW 2.2uW Full chip @ Implantation mode>20mW >9.6mWPFM conversion gain 8 Hz/lux 13.8 Hz/luxBiphasic current(with 10k Ω loading) ±50μA±10μAA CKNOWLEDGMENTThe authors would like to thank Prof. L.S. Fan, Prof. K.T. Tang, S.F. Yeh, and M.T. Chung for supporting this work.R EFERENCES[1] L. Theogarajan, J. Wyatt, J. Rizzo, B. Drohan, M. Markova, S. Kelly, G.Swider, M. Raj, D. Shire, M. Gingerich, J. Lowenstein, B. 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