Digital AGC Based on Coherent Adjustment Cycle for DSSS Receiver
GNSS软件接收机中频信号数据分析
点击输入扼要文字内容，文字 内容需概括精炼。
输入标题
点击输入扼要文字内容，文字 内容需概括精炼。
输入标题
点击输入扼要文字内容，文字 内容需概括精炼。
添加标题内容
45%
44%
35%
66%
输入标题
点击输入您的内容，或者通过复制您的文本后，再此框中 挑选粘贴。请言简意赅，简单说明即可，不必繁琐。
此框中挑选粘贴。
输入标题
点击此处输入您的内容，或 者通过复制您的文本后，再
此框中挑选粘贴。
输入标题
点击此处输入您的内容，或 者通过复制您的文本后，再
此框中挑选粘贴。
输入标题
点击此处输入您的内容，或 者通过复制您的文本后，再
此框中挑选粘贴。
添加标题内容
输入标题
点击输入扼要文字内容，文字 内容需概括精炼。
标题
点击输入您的内容，或者通过复制您的文本 后，再此框中挑选粘贴。请言简意赅，简单 说明即可，不必繁琐。
标题
点击输入您的内容，或者通过复制您的文本 后，再此框中挑选粘贴。请言简意赅，简单 说明即可，不必繁琐。
PART T WO
ADD TITLE CONTENT
添加标题
点击输入您的内容，或通过复制您的文本后，到 此框中挑选粘贴。请言简意赅
沟通能力培训
点击输入您的内容，或通过复制您的文本后，到此框中挑选粘贴。请言简意赅，简单说明 即可，不必繁琐。点击输入您的内容
汇报人：XXX
汇报时间：XX.XX
目录
1 • 点击添加标题 2 • 点击添加标题 3 • 点击添加标题 4 • 点击添加标题
PART ONE
ADD TITLE CONTENT
基于最大输出信噪比的L-DACS1接收机盲自适应波束形成算法
基于最大输出信噪比的L-DACS1接收机盲自适应波束形成算法WANG Lei;LI Guangxue;LI Dongxia;LIU Haitao【摘要】由于L频段数字航空通信系统1(L-band digital aeronautical communication system1,L-DACS1)和民航测距机(distance measuring equipment,DME)系统的频谱有部分重叠,因此在L-DACS1接收机中需要考虑DME干扰的抑制问题.提出了基于最大输出信噪比的干扰抑制和盲波束形成算法.由于DME脉冲干扰的功率较大,首先采用子空间跟踪算法来得到干扰子空间,然后将接收数据向干扰子空间的正交补空间进行投影以抑制DME干扰.干扰抑制后,接收数据中只剩下正交频分复用(orthogonal frequency division multiplexing,OFDM)信号和噪声了.为了充分利用阵列天线的优势,采用了输出信噪比最大准则来进行波束形成,将天线方向图的主瓣对准OFDM信号来向,以提高接收机输出信号的信噪比.仿真表明,该方法不需要先验信息就能够在抑制干扰的同时进行盲波束形成,在OFDM信号来向上获得高增益的主瓣,进而提高输出信噪比;另外,所提的波束形成方法在输入信噪比较低的环境下依然能够形成稳定的波束,将主瓣对准信号来向.【期刊名称】《系统工程与电子技术》【年(卷),期】2018(040)012【总页数】6页(P2839-2844)【关键词】L频段数字航空通信系统1;测距机;最大输出信噪比;盲波束形成【作者】WANG Lei;LI Guangxue;LI Dongxia;LIU Haitao【作者单位】;;;【正文语种】中文【中图分类】TN965;TN91.70 引言L波段数字航空通信系统(L-band digital aeronautical communication system,L-DACS)是民用航空未来沿陆地航路部署的新一代空地蜂窝通信系统,为陆地航路、终端区、机场等区域飞行的航空器提供空中交通管制、航空运营管理等业务服务[1-2]。
基于钟差检验的GNSS授时欺骗检测与识别
摘 要：针对牵引式欺骗对授时接收机危害性强且难以检测的问题，基于授时欺骗的实施原理分析了授时解 的变化规律，利用欺骗实施后钟差必然累积异常的特点，提出了一种钟差构造检验统计量的授时欺骗检测与识别 方法。分析了该方法的检测性能，并通过蒙特卡罗仿真验证了理论的正确性。最后使用软件接收机对 ＴＥＸＢＡＴ （Ｔｅｘａｓｓｐｏｏｆｉｎｇｔｅｓｔｂａｔｔｅｒｙ）授时欺骗场景数据进行测试验证了该方法的有效性。由于不需要接收机添加额外 的硬件且在无位置信息辅助的情况下该算法依然能够检测欺骗，因此对全球卫星导航系统授时安全具有较高的 应用价值。
针对牵引式欺骗对授时接收机危害性强且难以检测的
式 ρ狊狀狆
中分：别ρ狀犪狌是和欺ρ骗狀犪狌分信别号是引真起烅烄烆实的ρρ狀狀＝伪信ρ＝犪狀ρ狌距号狀犪＋狌和对ρ＋狊狀ρ伪狆应狊狀狆距的率伪偏距差和。伪
距
率
（５） ；ρ狊狀狆 和
由式（１）、式（２）和式（５）可得观测 犖 颗欺骗卫星所组
成的系统测量方程如下：
ρρρ犪犪犪１２犖狌狌狌
燀ρ犪犖狌
＋＋＋＋ρρρρ狊狊狊狊１２犖犖狆狆狆狆燅＝燀狋犳犳狌狌狌燅＋燀（（（狏狏狏犖１２狓－－－犖狏狏狏－狊狊狊狌狌狌狓）））狊···狌 １１１１２犖燅＋燀犫犖－－－－ｃｃｃ犳犳犳ｃ狋狊狊狊犖１２犖燅＋燀εεεε犖ρρρ１２犖ρ燅
１ 授时欺骗原理
（６） 式中：狓狊狌、狏狊狌分别表示欺骗后的位置和速度。
伪 表
距 示
观 伪
测 距
接收机的速度和钟漂解基于伪距率观测量，伪距率观
测方程如下：
式中：狏狌
表示接ρ狀收＝机（狏真狀－实狏狌速）１度狀＋；犳犮狌犳表狌－示犮犳接狊狀＋收ε机ρ狀
AD9122器件手册
Dual, 16-Bit, 1230 MSPS,TxDAC+® Digital-to-Analog ConverterAD9122 Rev. AInformation furnished by Analresponsibility is assumed by Ana rights of third parties that may re license is granted by implication T rademarks and registered trad MA 02062-9106, U.S.A. Inc. All rights reserved.og Devices is believed to be accurate and reliable. However, nolog Devices for its use, nor for any infringements of patents or other sult from its use. Specifications subject to change without notice. No or otherwise under any patent or patent rights of Analog Devices. emarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, Tel: 781.329.4700Fax: 781.461.3113 ©2010 Analog Devices,FEATURESFlexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, R L = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidthGain and phase adjustment for sideband suppression Multiple chip synchronization interfacesHigh performance, low noise PLL clock multiplierDigital inverse sinc filterLow power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full operating conditions72-lead, exposed paddle LFCSPAPPLICATIONSWireless infrastructureW-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTEDigital high or low IF synthesisTransmit diversityWideband communications: LMDS/MMDS, point-to-point GENERAL DESCRIPTIONThe AD9122 is a dual 16-bit, high dynamic range, digital-to-analog converter (DAC) that provides a sample rate of 1200 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9122 comes in a 72-lead LFCSP.PRODUCT HIGHLIGHTS1.Ultralow noise and intermodulation distortion (IMD)enable high quality synthesis of wideband signals frombaseband to high intermediate frequencies.2. A proprietary DAC output switching technique enhancesdynamic performance.3.The current outputs are easily configured for varioussingle-ended or differential circuit topologies.4.Flexible LVDS digital interface allows the standard 32-wirebus to be reduced to ½ or ¼ of the width.TYPICAL SIGNAL CHAINCOMPLEX BASEBANDDC COMPLEX IFf IFRFLO – f IF8281-1 Figure 1.AD9122Rev. A | Page 2 of 60TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 6 Digital Input Data Timing Specifications ................................. 6 AC Specifications .......................................................................... 7 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 17 Differences Between the AD9122R1 and AD9122R2 ............... 18 Theory of Operation ...................................................................... 19 Serial Port Operation ................................................................. 19 Data Format ................................................................................ 19 Serial Port Pin Descriptions ...................................................... 19 Serial Port Options ..................................................................... 20 Device Configuration Register Map and Descriptions ......... 21 LVDS Input Data Ports .................................................................. 33 Word Interface Mode ................................................................. 33 Byte Interface Mode ................................................................... 33 Nibble Interface Mode ............................................................... 33 FIFO Operation .......................................................................... 33 Interface Timing ......................................................................... 35 Digital Datapath .............................................................................. 37 Premodulation ............................................................................ 37 Interpolation Filters ................................................................... 37 NCO Modulation ....................................................................... 40 Datapath Configuration ............................................................ 40 Determining Interpolation Filter Modes ................................ 41 Datapath Configuration Example ............................................ 42 Data Rates vs. Interpolation Modes ......................................... 43 Coarse Modulation Mixing Sequences .................................... 43 Quadrature Phase Correction ................................................... 44 DC Offset Correction ................................................................ 44 Inverse Sinc Filter ....................................................................... 44 DAC Input Clock Configurations ................................................ 45 DAC Input Clock Configurations ............................................ 45 Analog Outputs............................................................................... 47 Transmit DAC Operation .......................................................... 47 Auxiliary DAC Operation ......................................................... 48 Baseband Filter Implementation .............................................. 49 Driving the ADL5375-15 .......................................................... 49 Reducing LO Leakage and Unwanted Sidebands .................. 50 Device Power Dissipation .............................................................. 51 Temperature Sensor ................................................................... 52 Multichip Synchronization ............................................................ 53 Synchronization with Clock Multiplication ............................... 53 Synchronization with Direct Clocking .................................... 54 Data Rate Mode Synchronization ............................................ 54 FIFO Rate Mode Synchronization ........................................... 55 Additional Synchronization Features ...................................... 55 Interrupt Request Operation ........................................................ 57 Interrupt Service Routine .......................................................... 57 Interface Timing Validation .......................................................... 58 SED Operation ............................................................................ 58 SED Example .............................................................................. 58 Example Start-Up Routine ........................................................ 59 Outline Dimensions ....................................................................... 60 Ordering Guide .. (60)AD9122Rev. A | Page 3 of 60REVISION HISTORY3/10—Rev. 0 to Rev. AChanges to Reflect Differences Between R1 and R2Silicon................................................................................... Universal Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 6 Changes to Table 5 ............................................................................ 7 Change to IOVDD Rating in Table 6 .............................................. 8 Changes to Table 8 ............................................................................ 9 Changes to Figure 10 to Figure 15 ................................................ 12 Added Differences Between the AD9122R1 and AD9122R2 Section, Added Figure 36 and Figure 37; RenumberedSequentially ...................................................................................... 18 Changes to Table 10 ........................................................................ 21 Changes to Table 11 ........................................................................ 23 Changes to FIFO Operation Section ............................................ 33 Changes to Resettling the FIFO Section and Replaced Table 13; Renumbered Sequentially; Added Serial Port Initiated FIFO Reset Section, and Added FRAME Initiated Relative FIFOReset Section .................................................................................... 34 Added FRAME Initiated Absolute FIFO Reset Section andReplaced Table 14 ............................................................................ 35 Changes to Figure 54 ...................................................................... 38 Changes to Table 18 ........................................................................ 39 Changes to SED Example Section ................................................. 58 Added Example Start-Up Routine Section .................................. 59 9/09—Revision 0: Initial VersionAD9122Rev. A | Page 4 of 60FUNCTIONAL BLOCK DIAGRAMD15P—D15ND0P—D0NIOUT1P IOUT1NIOUT2P IOUT2NFSADJREFIO DCI FRAME08281-002Figure 2. AD9122 Functional Block DiagramAD9122Rev. A | Page 5 of 60SPECIFICATIONSDC SPECIFICATIONST MIN to T MAX , AVDD33 = 3.3 V , DVDD18 = 1.8 V , CVDD18 =1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1.Parameter Min Typ Max Unit RESOLUTION 16 Bits ACCURACY Differential Nonlinearity (DNL) ±2.1 LSB Integral Nonlinearity (INL) ±3.7 LSB MAIN DAC OUTPUTS Offset Error −0.001 0 +0.001 % FSR Gain Error (with Internal Reference) −3.6 ±2 +3.6 % FSR Full-Scale Output Current 18.66 19.6 31.66 mA Output Compliance Range −1.0 +1.0 V Output Resistance 10 MΩ Gain DAC Monotonicity Guaranteed Settling Time to Within ±0.5 LSB 20 ns MAIN DAC TEMPERATURE DRIFT Offset 0.04 ppm/°C Gain 100 ppm/°C Reference Voltage 30 ppm/°C REFERENCE Internal Reference Voltage 1.2 V Output Resistance 5 kΩ ANALOG SUPPLY VOLTAGES AVDD33 3.13 3.3 3.47 V CVDD18 1.71 1.8 1.89 V DIGITAL SUPPLY VOLTAGES DVDD18 1.71 1.8 1.89 V IOVDD 1.71 1.8/3.3 3.47 V POWER CONSUMPTION 2× Mode, f DAC = 491.22 MSPS, IF = 10 MHz, PLL Off 834 mW 2× Mode, f DAC = 491.22 MSPS, IF = 10 MHz, PLL On 913 mW 8× Mode, f DAC = 800 MSPS, IF = 10 MHz, PLL Off 1135 1241 mWAVDD33 55 57 mA CVDD18 85 90 mA DVDD18 444 495 mA Power-Down Mode (Register 0x01 = 0xF1) 6.5 18.8 mW Power Supply Rejection Ratio, AVDD33 −0.3 +0.3 % FSR/V OPERATING RANGE −40 +25 +85 °C1Based on a 10 kΩ external resistor.AD9122Rev. A | Page 6 of 60DIGITAL SPECIFICATIONST MIN to T MAX , AVDD33 = 1.8 V , IOVDD = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted.1LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted.DIGITAL INPUT DATA TIMING SPECIFICATIONSTable 3.Parameter Min Typ Max UnitLATENCY (DACCLK Cycles) 1× Interpolation (With or Without Modulation) 64 Cycles 2× Interpolation (With or Without Modulation) 135 Cycles 4× Interpolation (With or Without Modulation) 292 Cycles 8× Interpolation (With or Without Modulation) 608 Cycles Inverse Sinc 20 Cycles Fine Modulation 8 Cycles Power-Up Time 260 msAD9122Rev. A | Page 7 of 60AC SPECIFICATIONST MIN to T MAX , AVDD33 = 3.3 V , DVDD18 = 1.8 V , CVDD18 = 1.8 V , I OUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4.ParameterMin Typ Max UnitSPURIOUS-FREE DYNAMIC RANGE (SFDR) f DAC = 100 MSPS, f OUT = 20 MHz 78 dBc f DAC = 200 MSPS, f OUT = 50 MHz 80 dBc f DAC = 400 MSPS, f OUT = 70 MHz 69 dBc f DAC = 800 MSPS, f OUT = 70 MHz72 dBc TWO-TONE INTERMODULATION DISTORTION (IMD) f DAC = 200 MSPS, f OUT = 50 MHz 84 dBc f DAC = 400 MSPS, f OUT = 60 MHz 86 dBc f DAC = 400 MSPS, f OUT = 80 MHz 84 dBc f DAC = 800 MSPS, f OUT = 100 MHz81 dBc NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING f DAC = 200 MSPS, f OUT = 80 MHz −162 dBm/Hz f DAC = 400 MSPS, f OUT = 80 MHz −163 dBm/Hz f DAC = 800 MSPS, f OUT = 80 MHz−164 dBm/Hz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER f DAC = 491.52 MSPS, f OUT = 10 MHz 84 dBc f DAC = 491.52 MSPS, f OUT = 122.88 MHz 82 dBc f DAC = 983.04 MSPS, f OUT = 122.88 MHz 83 dBc W-CDMA SECOND ACLR, SINGLE CARRIER f DAC = 491.52 MSPS, f OUT = 10 MHz 88 dBc f DAC = 491.52 MSPS, f OUT = 122.88 MHz 86 dBc f DAC = 983.04 MSPS, f OUT = 122.88 MHz88dBcTable 5. Interface SpeedsBus Width Interpolation Factorf BUS (Mbps)1.8 V ± 5% 1.8 V ± 2% 1.9 V ± 5% Nibble (4 Bits) 1×1100 1200 1230 2× (HB1) 1100 1200 1230 2× (HB2) 1100 1200 1230 4× 1100 1200 1230 8× 1100 1200 1230 Byte (8 Bits) 1×1100 1200 1230 2× (HB1) 1100 1200 1230 2× (HB2) 1100 1200 1230 4× 1100 1200 1230 8× 550 600 615 Word (16 Bits) 1×1100 1200 1230 2× (HB1) 900 1000 1000 2× (HB2) 1100 1200 1230 4× 550 600 615 8×275 300 307.5AD9122Rev. A | Page 8 of 60ABSOLUTE MAXIMUM RATINGSTHERMAL RESISTANCEThe exposed paddle (EPAD) must be soldered to the ground plane for the 72-lead, LFCSP . The EPAD performs as an electrical and thermal connection to the board.Typical θJA , θJB , and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation effectively reducing θJA and θJB . Table 7. Thermal ResistancePackage θJA θJB θJC Unit Conditions 72-Lead LFCSP_VQ 20.7 10.9 1.1 °C/W EPAD solderedESD CAUTIONStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.AD9122Rev. A | Page 9 of 6008281-003D 11P D 11N D 10P D 10N D 9P D 9N D 8P D 8N D C I D C I D V D D 18D V S D 7P D 7N D 6P D 6N D 5P D 5N PIN CONFIGURATION AND FUNCTION DESCRIPTIONS12345678910111213141516CVDD18DACCLKP DACCLKNCVSS FRAMEP FRAMENIRQ D15P D15N NC IOVDD DVDD18D14P D14N D13P D13N 17D12P 18D12N 19202122232425262728293031323334P N S 3536545352515049484746454443424140393837RESET CS SCLK SDIO SDO DVDD18D0N D0P D1N D1P DVSS DVDD18D2N D2P D3N D3P D4N D4P727170696867666564636261605958575655C VD D 18C V D D 18REF C L K P R E F C L K N A V D D 33I O U T 1P I O U T 1N A V D D 33A V S S F S A D J R E F I O A V S S A V D D 33I O U T 2N I O U T 2P A V D D 33A V S S NCNOTES1. NC = NO CONNECT.2. EXPOSED PAD MUST BE CONNECTED TO AVSS.Figure 3. Pin ConfigurationAD9122Rev. A | Page 10 of 60AD9122050100150200250300350400450f OUT (MHz)TYPICAL PERFORMANCE CHARACTERISTICS0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c)08281-10150100150200250300350400450f OUT (MHz)Figure 4. Harmonics vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c )08281-10208281-1030–10–20–30–40–50–60–70–80–90–100050100150200250300350400450H A R M O N I C S (d B c )f OUT(MHz)08281-1040–10–20–30–40–50–60–70–80–90–10050100150200250300350400450H A R M O N I C S (d B c )f OUT (MHz)Figure 7. Second Harmonic vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC= 20 mA08281-1050–10–20–30–40–50–60–70–80–90–10050100150200250300350400450H A R M O N I C S (d B c )f OUT (MHz)Figure 5. Harmonics vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mAFigure 8. Third Harmonic vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC = 20 mA0–10–20–30–40–50–60–70–80–90–100H A R M O N I C S (d B c )100200300400500600700f OUT (MHz)08281-106Figure 6. Harmonics vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA Figure 9. Second Harmonic vs. f OUT over f SC , 2× Interpolation,f DATA = 400 MSPS, Digital Scale = 0 dBFSAD9122–69–70–71–72–73–74–75–77H I G H E S T D I G I T A L S P U R (d B c )–78–79050100150200250300350400450f OUT (MHz)–7608281-10708281-110START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 500.0MHzSWEEP 6.017s (601 PTS)08281-111START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 800.0MHzSWEEP 9.634s (601 PTS)Figure 10. Highest Digital Spur vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA–60–65–70–75–80–85H I G H E S T D I G I T A L S P U R (d B c )050100150200250300350400450f OUT (MHz)08281-108Figure 11. Highest Digital Spur vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA–60–90–95–85–80–75–70–65H I G H E S T D I G I T A L S P U R (d B c )010*******400500600700f OUT (MHz)08281-109Figure 12. Highest Digital Spur vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mAFigure 13. 2× Interpolation, Single-Tone Spectrum, f DATA = 250 MSPS,f OUT= 101 MHzFigure 14. 4× Interpolation, Single-Tone Spectrum, f DATA = 200 MSPS,f OUT = 151 MHz08281-START 1.0MHz #RES BW 10kHzVBW 10kHzSTOP 800.0MHzSWEEP 9.634s (601 PTS)112Figure 15. 8× Interpolation, Single-Tone Spectrum, f DATA = 100 MSPS,f OUT = 131 MHzAD91220–90–80–70–60–50–40–30–20–10I M D (d B c )050100150200250300350400450f OUT (MHz)308281-11Figure 16. IMD vs. f OUT over f DATA , 2× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–80–70–60–50–40–30–20–10–90I M D (d B c )050100150200250300350400450f OUT (MHz)408281-11Figure 17. IMD vs. f OUT over f DATA , 4× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–80–70–60–50–40–30–20–10I M D (d B c )–100–90050100150200250300350400450f OUT(MHz)08281-115Figure 18. IMD vs. f OUT over f DATA , 8× Interpolation,Digital Scale = 0 dBFS, f SC = 20 mA0–90–80–70–60–50–40–30–20–10050100150200250300350400450I M D (d B c )f OUT(MHz)08281-116Figure 19. IMD vs. f OUT over Digital Scale, 2× Interpolation,f DATA = 400 MSPS, f SC = 20 mA–50–85–80–75–70–65–60–55050100150200250300350400450I M D (d B c )f OUT (MHz)08281-117Figure 20. IMD vs. f OUT over f SC , 2× Interpolation, f DATA = 400 MSPS,Digital Scale = 0 dBFS–40–90–85–80–75–70–65–60–55–50–45I M D (d B c)050100150200250300350400450f OUT (MHz)08281-118Figure 21. IMD vs. f OUT , PLL On vs. PLL Off, 4× Interpolation, f DATA = 200 MSPS,Digital Scale = 0 dBFS, f SC = 20 mAAD9122–152–156–154–158–160–162–164––166N S D (d B m /H z )50100150200250300350400450f OUT (MHz)908281-11Figure 22. 1-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL Off–154–158–156–160–162–164–166–168N S D (d B m /H z )050100150200250300350400450f OUT (MHz)08281-12Figure 23. 1-Tone NSD vs. f OUT over Digital Scale, f DATA = 200 MSPS,4× Interpolation, f SC = 20 mA, PLL Off–158–159–160–161–162–163–164–165N S D (d B m /H z )–166050100150200250300350400450f OUT (MHz)08281-121Figure 24. 1-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL On 161.0–165.5–165.0–164.5–164.0–163.5–163.0–162.5–162.0–161.5050100150200250300350400450N S D (d B m /H z )f OUT(MHz)08281-122Figure 25. 8-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL Off–161.0–166.5–165.5–166.0–165.0–164.5–164.0–163.5–163.0–162.5–162.0–161.5050100150200250300350400450N S D (d B m /H z )fOUT (MHz)08281-123Figure 26. 8-Tone NSD vs. f OUT over Digital Scale, f DATA = 200 MSPS,4× Interpolation, f SC = 20 mA, PLL Off–160–161–162–163–164–165–166N S D (d B m /H z)050100150200250300350400450f OUT (MHz)08281-124Figure 27. 8-Tone NSD vs. f OUT over Interpolation Rate, Digital Scale = 0 dBFS,f SC = 20 mA, PLL OnAD9122–77–84–83–82–81–80–79–78A C L R (d B c )–050100150200250fOUT (MHz)50–55–60–65–70–75–80–85–900100200300400500A C L R (dB c )f OUT(MHz)08281-12508281-128Figure 28. 1-Carrier W-CDMA ACLR vs. f OUT over Digital Scale,Adjacent Channel, PLL Off–78–88–86–84–82–80–90A C L R (dB c )050100150200250fOUT (MHz)08281-126Figure 29. 1-Carrier W-CDMA ACLR vs. f OUT over f DAC ,Alternate Channel, PLL Off–70–90–85–80–75A C L R (dB c )–95050100150200250fOUT (MHz)08281-127Figure 30. 1-Carrier W-CDMA ACLR vs. f OUT over f DAC ,Second Alternate Channel, PLL Off Figure 31. 1-Carrier W-CDMA ACLR vs. f OUT , Adjacent Channel,PLL On vs. PLL Off–70–72–74–76–78–80–82–84–86–88–900100200300400500A C L R (dB c )f OUT(MHz)08281-129Figure 32. 1-Carrier W-CDMA ACLR vs. f OUT , Alternate Channel,PLL On vs. PLL Off–70–95–90–85–80–75A C L R (dB c)0100200300400500f OUT (MHz)08281-130Figure 33. 1-Carrier W-CDMA ACLR vs. f OUT , Second Alternate Channel,PLL On vs. PLL OffAD912208281-131START 133.06MHz #RES BW 30kHzVBW 30kHz STOP 166.94MHzSWEEP 143.6ms (601 PTS)START 125.88MHz #RES BW 30kHz VBW 30kHz STOP 174.42MHzSWEEP 206.9ms (601 PTS)TOTAL CARRIER POWER –11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22REF CARRIER POWER –16.89dBm/3.84000MHzLOWER UPPER OFFSET FREQ INTEG BW dBc dBm dBc dBm 1–16.92dBm 5.000MHz 3.840MHz –65.88–82.76–67.52–84.40RMS RESULTS FREQ LOWER UPPER OFFSET REF BW dBc dBm dBc dBm CARRIER POWER 5.00MHz 3.840MHz –75.96–85.96–77.13–87.13–10.00dBm/10.00MHz 3.840MHz –85.33–95.33–85.24–95.253.840MHz15.00MHz2.888MHz–95.81–95.81–85.43–95.4308281-1322–16.89dBm 10.00MHz 3.840MHz –68.17–85.05–69.91–86.793–17.43dBm 15.00MHz 3.840MHz–70.42–87.31–71.40–88.284–17.64dBmFigure 35. 1-Carrier W-CDMA ACLR Performance, IF = ~150 MHzFigure 34. 4-Carrier W-CDMA ACLR Performance, IF = ~150 MHzAD9122 TERMINOLOGYIntegral Nonlinearity (INL)INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale.Differential Nonlinearity (DNL)DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset ErrorThe deviation of the output current from the ideal of zero is called offset error. For IOUT1P, 0 mA output is expected when the inputs are all 0s. For IOUT1N, 0 mA output is expected when all inputs are set to 1.Gain ErrorThe difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0.Output Compliance RangeThe range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.Temperature DriftTemperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T MIN or T MAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius.Power Supply Rejection (PSR)The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling TimeThe time required for the output to reach and remain within a specified error band around its final value, measured fromthe start of the output transition.Spurious Free Dynamic Range (SFDR)The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output.Signal-to-Noise Ratio (SNR)SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.Interpolation FilterIf the digital inputs to the DAC are sampled at a multiple rate of f DATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near f DATA/2. Images that typically appear around f DAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR)The ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image RejectionIn a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.。
北斗卫星导航系统空间信号接口控制文件(精密单点定位服务信号PPP-B2b测试版)
©中国卫星导航系统管理办公室 2019
6.2.4 信息类型 2（轨道改正数及用户测距精度） ································ 15 6.2.5 信息类型 3（码间偏差改正数） ··············································· 17 6.2.6 信息类型 4（钟差改正数） ····················································· 19 6.2.7 信息类型 5（用户测距精度） ·················································· 21 6.2.8 信息类型 6（钟差改正与轨道改正-组合 1）································ 23 6.2.9 信息类型 7（钟差改正与轨道改正-组合 2）································ 25 6.3 信息有效期 ················································································· 27 7 用户算法 ···························································································· 28 7.1 PPP-B2b 信息增强对象··································································· 28 7.2 时间空间坐标系 ··········································································· 28 7.3 卫星码间偏差修正 ········································································ 28 7.4 卫星轨道改正 ·············································································· 29 7.5 卫星钟差改正 ·············································································· 29 7.6 用户测距精度 ·············································································· 30 7.7 系统时间解算 ·············································································· 30 8 缩略语 ······························································································· 31 附录 多进制 LDPC 编译码方法及示例 ·························································· 33
卫星接收系统抗干扰的卷积盲分离算法
关键 词 盲分 离 卷 积混合
ห้องสมุดไป่ตู้
初 等反射 矩 阵 信噪 比 噪声干 扰 卫星通 信
ＤｏＩ ０ ３ ８ ／．ｓ ｎ １ ０ — ５ Ｘ． ０ ２ ０ ． ０ ：１ ． ７ ｏ ｊ ｉｓ ． ０ ０ ７ ８ ２ １ ． ２ ０ ８
求 ，所 以可 以把 盲分 离技术 应用 到 卫 星 接 收系 统抗 干扰 中。盲 分 离所 研 究 的模 型 主要 分 为 瞬 时混 叠 、卷积｝ 昆叠及 非线 性混 叠 。而 在实 际的信 号环境 中 ，卫星 上接 收设 备 所接 收到 的信 号 基本上 都是 源信 号与 多径传 输信 道 的卷积混 叠 ，也就是 说 ，卫星上 接收 到 的信 号是 有用通 信信 号与 干扰信 号之
２ 卫 星 上 接 收信 号 的卷 积 盲 分离 模 型
考虑 一个 两输入 两输 出系统 ，卷 积盲分 离模 型可 表示为
声 １ 一
ｘ 一 ｓ （ Ｈ＊ 一∑ Ｈ ｋ （ 是 ） （ Ｓｔ ） ） 一
０
（） １
收 稿 日期 ；２ １ ５Ｏ 。 收修 改 稿 日期 ：２ １－７１ ０ １Ｏ ９ ０ １０ —１
生 旦
垦 窒 型 堂 垫
２
式 中 ｘ（） 观 测信 号 ， （） ｘ （） ｚ ￡］ ； 为未 知 的传 递通 道矩 阵 ，可 以用 Ｆ Ｒ模 型描 是 ｆ 一Ｅ ， （） Ｈ Ｉ
述 ，其 混合 滤波 器长度 为 ，矩 阵 Ｈ 要 求 是 列 满 秩 的 ； ｓ—Ｅ （） ， ￡］ Ｊ ￡ 期 望 的通 信 信 ｓ ｔ ，ｔ ） ，ｓ ）是 （ （ 号 ，， ｆ 是 干扰 信号 ，由于通 信信 号 ｓ 和干 扰 ｔ 分别来 自不 同的发射 源 ，它们是 相互 独立 的 ， ．（） （） ， ） （ 相 当于盲 信号分 离 中的源信 号 ；“＊ ”表示 卷 积算 子 ，卷 积盲 分 离 的 目的 是从 ｘ（）中获得 对 源 信 ￡ 号 的最 佳估 计 ，需要 寻 找一个 分 离滤 波器 ｗ 作 用 在 观 测信 号 ｘ（）上 ，使 得 输 出信 号 达 到统计 独
基于软件接收机的卫星双向时间频率传递
总第43卷第2期时间频率学报Vol.43No.2 2020年4月Journal of Time and Frequency Apr.,2020DOI：10.13875/j.issn.1674-0637.2020-02-0094-07基于软件接收机的卫星双向时间频率传递武文俊1,2,3，姜萌1,2,3，王翔1,2 ，张继海1,2，广伟1,2,3，董绍武1,2,3（1.中国科学院国家授时中心，西安710600；2.中国科学院时间频率基准重点实验室，西安710600；3.中国科学院大学天文与空间科学学院，北京101048）摘要：卫星双向时间频率传递是目前最准确的远距离时间比对方式之一。
多年以来，卫星双向一直是利用硬件调制解调器来开展工作。
在国际时间频率咨询委员会卫星双向工作组的组织下，全球主要时间实验室于2016年发起了基于软件接收机的卫星双向时间比对试验。
2016年8月，中国科学院国家授时中心与德国物理技术研究院开通了第一条欧亚间基于软件接收机的卫星双向时间比对链路。
通过对基于软件接收机的卫星双向时间比对进行测试与标定，结果表明：该时间比对方式的频率相对稳定度和时间稳定度分别可以达到1×10-15/d和1ns，其链路总不确定优于1.6ns。
最后将该链路与基于硬件调制解调器的卫星双向时间比对进行比较验证，二者结果互为一致。
关键词：协调世界时；时间比对；卫星双向；软件接收机Two-way satellite time and frequency transferbased on software defined receiverWU Wen-jun1,2,JIANG Meng1,2,3,WANG Xiang1,2,ZHANG Ji-hai1,2,GUANG Wei1,2,3,DONG Shao-wu1,2,3(1.National Time Service Center,Chinese Academy of Sciences,Xi’an710600,China;2.Key Laboratory of Time and Frequency Primary Standards,Chinese Academy of Sciences,Xi’an710600,China;3.School of Astronomy and Space Science,University of Chinese Academy of Sciences,Beijing101048,China)Abstract:The two-way satellite time and frequency transfer(TWSTFT)is one of the most accurate and precise methods for remote clocks.The traditional TWSTFT is operated on hardware modem.In2016,all the major time laboratories in the world launched the TWSTFT study based on software defined receiver(SDR) under the organization of Consultative Committee for Time and Frequency Work Group on TWSTFT (WGTWSTFT).The first Euro-Asia SDR TWSTFT link was built up between the National Time Service Center (NTSC),Chinese Academy of Sciences and Physikalisch-Technische Bundesanstalt(PTB).Test and calibration were implemented on the NTSC-PTB SDR link.It is shown that the relative frequency instability and time 收稿日期：2019-10-29；接受日期：2020-01-21基金项目：国家自然科学基金资助项目（11703030；11473029）作者简介：武文俊，男，副研究员，主要从事时间与频率研究。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
ＣＯＭＭＵＮＩＣＡＴＩＯＮＳ ＳＹＳＴＥＭ ＤＥＳＩＧＮ Ｄｉｇｉｔａｌ ＡＧＣ Ｂａｓｅｄ ｏｎ Ｃｏｈｅｒｅｎｔ Ａｄｊｕｓｔｍｅｎｔ Ｃｙｃｌｅ ｆｏｒ ＤＳＳＳ Ｒｅｃｅｉｖｅｒ
ＳＨＥＮ Ｙｕｙａｏ，ＷＡＮＧ Ｙｏｎｇｑｉｎｇ ，ＳＨ ＥＮＧ Ｄｅｗｅｉ，ＷＵ Ｓｉｌｉａｎｇ Ｓｃｈｏｏｌ ｏｆｌｎｉｂｎｎａｔｉｏｎ ａｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ，Ｂｅｉｊｉｎｇ Ｉｎｓｔｉｔｕｔｅ ｏｆＴｅｃｈｎｏｌｏｇｙ，Ｂｅｉｊｉｎｇ １０００８１，Ｃｈｉｎａ Ｃｏｒｒｅｓｐｏｎｄｉｎｇ ａｕｔｈｏｒ．Ｅ－ｍａｉｌ：ｗａｎｇｙｏｎｇｑｉｎｇ ｂｉｔ．ｅｄｕ．ｃｎ
Ａｂｓｔｒａｃｔ：Ｉｎ ｏｒｄｅｒ ｔｏ ｍｅｅｔ ｔｈｅ ｒｅｑｕｉｒｅｍｅｎｔｓ ｒ０ｒ ｚｅｒｏ ｖａｌｕｅ ｓｔａｂｉ１ｉｔｙ ｏｆ ｄｉｒｅｃｔ ｓｅｑＨｅｎｃｅ ｓｐｒｅａｄ ｓｐｅｃｔｒｕｍ（ＤＳＳＳ）ｓｉｇｎａｌ ｐｒｏｃｅｓｓｉｎｇ ｉｎ ｈｉｇｈ ｄｙｎａｍｉｃ ｓｃｅｎａｒｉｏ，ｄｉｇｉｔａｌ ａｕｔｏｍａｔｉｃ ｇａｉｎ ｃｏｎｔｒｏｌ（ＡＧＣ）ｉｓ ｅｍｐｌｏｙｅｄ ｔｏ ｒｅｇｕｌａｔｅ Ｐｏｗｅ ｒ．Ｈｏｗｅｖｅ ｒ．ｃｏｎｖｅｎｔｉｏｎａ１ ＡＧＣ ｃａｕｓｅｓ ｄｅｇｒａｄａｔｉｏｎ ｉｎ ｔｈｅ ｓｙｎｃｈｒｏｎｉｚａｔｉ０ｎ ｐｅｒｆｏｒｍａｎｃｅ ｏｆ ＤＳＳＳ ｒｅｃｅｉｖｅｒ．Ｂａｓｅｄ ｏｎ ｔｈｅ ｔｈｅｏｒｅｔｉｃａｌ ａｎａｌｙｓｉｓ ｏｆ ｔｈｅ ｉｎｆｌＨｅｎｃｅ ｏｆ ｄｉｇｉｔａｌ ＡＧＣ ｏｎ ＤＳＳＳ ｓｉｇｎａｌ ｓｙｎｃｈｒｏｎｉｚａｔｉｏｎ．ｔｈｉｓ ｐａｐｅｒ ｐｒｏｐｏｓｅｓ ａ ｎｅｗ ＡＧＣ ａｌｇｏｒｉｔｈｍ，ｗｈｉｃｈ ｉｓ ａｐｐｌｉｃａｂｌｅ ｔｏ ｍｕｌｔｉ—ｃｈａｎｎｅｌ ｄｉｇｉｔａｌ ＤＳＳＳ ｓｉｇｎａｌ ｒｅｃｅｉｖｅｒ．Ｂｙ ｍａｋｉｎｇ ｐｏｗｅｒ ａｄｊｕｓｔｍｅｎｔ ｃｙｃｌｅ ａｎｄ ｓｙｎｃｈｒｏｎｉｚａｔｉｏｎ ｃｙｃｌｅ ｃｏｈｅｒｅｎｔ ｗｉｔｈ ｅａｃｈ ｏｔｈｅｒ ａｄａｐｔｉｖｅｌｙ ｔｈｅ ｉｎｆｌＨｅｎｃｅ ｏｆ ｄｉｇｉｔａｌ ＡＧＣ ｏｎ ｓｕｂｓｅｑｕｅｎｔ ｓｙｎｃｈｒ０ｎｉｚａｔｉｏｎ ｐｒｏｃｅｓｓｉｎｇ ｈａｓ ｂｅｅｎ ｅｌｉｍｉｎａｔｅｄ．Ｔｈｅｏｒｅｔｉｃａｌ ａｎａｌｙｓｉｓ，ｓｉｍｕｌａｔｉｏｎ ｒｅｓｕｌｔｓ ａｎｄ ｅｘｐｅｒｉｍｅｎｔａｌ ｄａｔａ ｖｅｒｉｆｙ ｔｈｅ ｖａｌｉｄｉｔｙ ｏｆ ｔｈｅ ｐｒｏｐｏｓｅｄ ａ１ｇｏｒｉｔｈｎ１．ＢＹ ｖｉ ｒｔｕｅ ｏｆ ｔｈｅ Ｐ ｒｏｐｏｓｅｄ ａｌｇｏｒｉｔｈｍ，ｔｈｅ ｉｎｆｌｕｅｎｃｅ ｏｆ ｄｉｇｉｔａｌ ＡＧＣ ｏｎ ＤＳＳＳ ｓｉｇｎａｌ ｓｙｎｃｈｒ０ｎｉｚａｔｉｏｎ ｉｓ ｅｌｉｍｉｎａｔｅｄ． Ｔｈｉ ｓ ａｌｇｏｒｉｔｈｍ ａｐｐｌｉｅｓ ｔｏ ａｎ ａｅｒｏｓｐａｃｅ ｅｎｇｉｎｅｅｒｉｎｇ ｐｒｏｊｅｃｔ ｓｕｃｃｅｓｓｆｕｌｌｙ． Ｋｅｙｗｏｒｄｓ：ＤＳＳＳ ｒｅｃｅｉｖｅｒ；ｄｉｇｉｔａｌ ＡＧＣ； ａｃｑｕｉｓｉｔｉｏｎ；ｔｒａｃｋｉｎｇ Ｉ．ＩＮＴＲＯＤＵＣＴＩＯＮ Ｄｕｅ ｔｏ ｉｔｓ ｈｉｇｈ—ｃｏｎｃｅａｌｍｅｎｔ，ａｎｔｉ—ｉｎｔｅｒｃｅｐｔｉｏｎ ａｎｄ ａｎｔｉ－ｊａｍｍｉｎｇ ａｂｉｌｉｔｙ，ＤＳＳＳ ｉｓ ｈｅａｖｉｌｙ ｕｔｉ— ｌｉｚｅｄ ｉｎ ｔｈｅ ｆｉｅｌｄｓ ｉｎｃｌｕｄｉｎｇ ｓａｔｅｌｌｉｔｅ ｎａｖｉｇａｔｉｏｎ ９５ ａｎｄ ｐｏｓｉｔｉｏｎｉｎｇ ｓｙｓｔｅｍ，ＴＴ＆Ｃ ｃｏｍｍｕｎｉｃａ— ｔｉｏｎ ｓｙｓｔｅｍ ｃｉｖｉｌｉａｎ ｃｏｍｍｕｎｉｃａｔｉｏｎｓ，ｅｔｃ．Ｅｓ— ｐｅｃｉａｌｌｙ ｆｏｒ ｏｎｂｏａｒｄ ｓｐｒｅａｄ ｓｐｅｃｔｒｕｍ ＴＴ＆Ｃ ｒｅｓｐｏｎｄｅｒｓ［１—２］ａｎｄ ｎａｖｉｇａｔｉｏｎ ｒｅｃｅｉｖｅｒｓ ［３］，ｔｈｅ ｉｎｐｕｔ ｓｉｇｎａｌ ｈａｓ ａ ｌａｒｇｅ ｐｏｗｅｒ ｒａｎｇｅ ａｎｄ ｃｏｎｔｉｎｕｏｕｓ ｐｏｗｅｒ ｃｈａｎｇｉｎｇ．Ｄｕｅ ｔｏ ｌｏｎｇ ｗｏｒｋｉｎｇ ｄｉｓｔａｎｃｅ ａｎｄ ａｎｔｉ－ｊａｍｍｉｎｇ ａｂｉｌｉｔｙ ｄｅｍａｎｄ，ｔｈｅ ｉｎｐｕｔ ｐｏｗｅｒ ｏｆ’ｏｎｂｏａｒｄ ｅｑｕｉｐ— ｍｅｎｔｓ ｈａｓ ｌａｒｇｅｒ ｄｙｎａｍｉｃ ｒａｎｇｅ ｔｈａｎ ｔｈａｔ ｏｌ、 ｔｈｅ ｃｏｎｖｅｎｔｉｏｎａｌ ｅｑｕｉｐｍｅｎｔ ｉｎ ｇｒｏｕｎｄ ｓｔａｔｉｏｎ， ｇｅｎｅｒａｌｌｙ ｅｘｃｅｅｄｉｎｇ ７０ｄＢ．Ｏｎ ｔｈｅ ｏｔｈｅｒ ｈａｎｄ， ｒａｐｉｄ ｍｏｖｅｍｅｎｔ ｏｆ ｔｈｅ ｓａｔｅｌｌｉｔｅｓ（＞１ ０ｋｍ／ｓ）ｒｅ— ｓｕｉｔｓ ｉｎ ｃｏｎｔｉｎｕｏｕｓ ｃｈａｎｇｅ ｏｆ、ｔｈｅ ｉｎｐｕｔ ｓｉｇｎａｌ ｐｏｗｅｒ ｗｉｔｈ ｈｉｇｈ ｃｈａｎｇｉｎｇ ｒａｔｅ，ｓｏ ｏｎｂｏａｒｄ ｒｅ— ｓｐｏｎｄｅｒｓ ａｎｄ ｎａｖｉｇａｔｉｏｎ ｒｅｃｅｉｖｅｒｓ ｎｅｅｄ ＡＧＣ ｐｒｏｃｅｓｓｉｎｇ ｔｏ ｅｎｓｕｒｅ ｔｈａｔ ｉｎｐｕｔ ｓｉｇｎａｌ ｈａｖｅ ｓｕｆｆｉｃｉｅｎｔ ｄｙｎａｍｉｃ ｒａｎｇｅ． ＡＧＣ ｐｒｏｃｅｓｓｉｎｇ ｒｅｄｕｃｅｓ ｔｈｅ ｆｌｕｃｔｕａｔｉｏｎ ｏｆ ｉｎｐｕｔ ｐｏｗｅｒ ｅｎｓｕｒｉｎｇ ｔｈｅ ｃｈａｎｇｅ ｗｉｔｈｉｎ ａ ｓｍａｌ１ ｒａｎｇｅ．Ａｃｃｏｒｄｉｎｇ ｔｏ ｔｈｅ ｉｍｐｌｅｍｅｎ— ｔａｔｉｏｎ ｍｏｄｅ．ＡＧＣ ｃａｎ ｂｅ ｄｉｖｉｄｅｄ ｉｎｔｏ ｔｈｒｅｅ ｃａｔｅｇｏｒｉｅｓ，ｎａｍｅｌｙ，ａｎａｌｏｇ ＡＧＣ［５－６】，ｈｙｂｒｉｄ ＡＧＣ［７］ａｎｄ ｄｉｇｉｔａｌ ＡＧＣ［８－９１．Ｔｈｅ ｒｅｓｅａｒｃｈ ｏｆ ＡＧＣ ｃｏｎｃｅｎｔｒａｔｅｓ ｏｎ ｔｈｅ ｐｏｗｅｒ ｄｅｔｅｃｔｉｏｎ ｍｅｔｈｏｄ［１ ０］ａｎｄ ｔｈｒｅｓｈｏｌｄ ｊ ｕｄｇｍｅｎｔ ｍｅｔｈｏｄ 【１ １—１２ Ｊ．Ｉｎ ｒｅｌａｔｉｖｅ ｔｅｒｎｌｓ ａｎａｌｏｇ ＡＧＣ ｈａｓ ｐｏｏｒ ｐｅｒｆｏｒｍａｎｅｅ ｏｎ ｎｏｉｓｅ ｒｅｓｉｓｔａｎｃｅ，ａｎ— ｔｉ－ｊａｍｍｉｎｇ ａｎｄ ａｍｐｌｉｔｕｄｅ ｄｅｔｅｃｔｉｏｎ ｐｒｅｃｉｓｉｏｎ． Ｍｏｒｅｏｖｅｒ，ｉｔｓ ｌｏｏｐ ｓｔａｂｉｌｉｔｙ ｉｓ ｖｅｒｙ ｌｉｍｉｔｅｄ ａｎｄ ｄｉｆｉｃｕｌｔ ｔｏ ａｄｊｕｓｔ．Ｔｈｅｒｅｔｂｒｅ，ｈｙｂｒｉｄ ＡＧＣ ａｎｄ ｄｉｇｉｔａｌ ＡＧＣ ａｔｔｒａｃｔ ｍｏｒｅ ａｔｔｅｎｔｉｏｎ ｎｏｗａｄａｙｓ． Ｒａｎｇｉｎｇ ａｃｃｕｒａｃｙ ｉｓ ａｎ ｉｍｐｏｒｔａｎｔ ｓｙｓｔｅｍ
Ｃｈｉｎａ Ｃｏｍｍｕｎｉｃａｔｉｏｎｓ・Ｆｅｂｒｕａｒｙ ２０ １ ５ ｉｎｄｉｃａｔｏｒ ｆｏｒ ｒｅｓｐｏｎｄｅｒｓ ａｎｄ ｎａｖｉｇａｔｉｏｎ ｒｅ— ｃｅｉｖｅｒｓ．Ｈｏｗｅｖｅｒ，ｔｈｅ ｚｅｒｏ ｖａｌｕｅ ｏｆ ｔｈｅ ｄｅｖｉｃｅ ｗｈｉｃｈ ｄｉｒｅｃｔｌｙ ｉｍｐａｉｒｓ ｒａｎｇｉｎｇ ａｃｃｕｒａｃｙ ｉｓ ｄｅｃｉｄｅｄ ｂｙ ｔｈｅ ｄｙｎａｍｉｃ ｒａｎｇｅ ａｎｄ ｔｅｍｐｅｒａｔｕｒｅ ｏｆ ｔｈｅ ｒｅｃｅｉｖｉｎｇ ｃｈａｎｎｅ１．Ｃｏｎｓｉｄｅｒｉｎｇ ｔｈｅ ｉｍ— ｐｏｒｔａｎｃｅ ｏｆ ｒａｎｇｉｎｇ ａｃｃｕｒａｃｙ ａｎｄ ｔｈｅ ｉｎｆｌｕｅｎｃｅ ｏｆ ｚｅｒｏ ｖａｌｕｅ ｓｔａｂｉｌｉｔｙ ｏｎ ｒａｎｇｉｎｇ ａｃｃｕｒａｃｙ， ｄｉｇｉｔａｌ ＡＧＣ ｈａｓ ｓｕｐｅｒｉｏｒ ｐｅｒｆｏｒｍａｎｃｅ ｔｈａｎ ｔｈｅ ｏｔｈｅｒ ｔｗｏ，ｂｅｃａｕｓｅ ｏｆ ｉｔｓ ｃｏｎｓｔａｎｔ ｄｅｌａｙ，ｗｈｉｃｈ ｉｓ ｉｎｄｅｐｅｎｄｅｎｔ ｏｆ ｉｎｐｕｔ ｐｏｗｅｒ ｃｈａｎｇｅ．Ａｎ— ｏｔｈｅｒ ｒｅａｓｏｎ ｉｓ ｔｈａｔ ｄｉｇｉｔａｌ ＡＧＣ ｉｓ ｆｒｅｅ ｆｒｏｍ ｔｈｅ ｔｅｍｐｅｒａｔｕｒｅ ｃｈａｎｇｅ，ｓｏ ｉｔ ｈａｓ ｇｏｏｄ ｐｅｒｆｏｒ－ ｍａｎｃｅ ｏｎ ｚｅｒｏ ｖａｌｕｅ ｓｔａｂｉｌｉｔｙ． Ｂｕｔ ｗｈｅｔｈｅｒ ｄｉｇｉｔａｌ ＡＧＣ ｗｉｌ１ ａｆｆｅｃｔ ｔｈｅ ｌａｔｔｅｒ ｓｖｎｃｈｒｏｎｉｚａｔｉｏｎ ｐｒｏｃｅｓｓｉｎｇ？Ｉｓ ｔｈｅ ｅｆｆｅｃｔ ｎｅｇａｔｉｖｅ？Ａｎｄ ｉｆ ｄｉｇｉｔａｌ ＡＧＣ ｄｏｅｓ ｈａｖｅ ｎｅｇａ’ ｔｉｖｅ ｅｆｆｅｃｔ．ｈｏｗ ｃａｎ ｗｅ ｅｌｉｍｉｎａｔｅ ｊｔ？Ｒｅｌａｔｉｖｅ ｒｅｓｅａｒｃｈ ｈａｓ ｎｏｔ ｂｅｅｎ ｆｏｕｎｄ ｙｅｔ．Ｔｈｉｓ ｐａｐｅｒ ｆｉｒｓｔ ａｎａｌｙｓｅｓ ｄｉｇｉｔａｌ ＡＧＣ ｔｅｃｈｎｏｌｏｇｙ，ｓｔｕｄｉｅｓ ｉｔｓ ｉｎｆｌｕｅｎｃｅ ｏｎ ＤＳＳＳ ｓｉｇｎａｌ ａｃｑｕｉｓｉｔｉｏｎ ａｎｄ ｔｒａｃｋｉｎｇ．Ｔｈｅｎ ａ ｎｅｗ ａｄａｐｔｉｖｅ ＡＧＣ ａｌｇｏｒｉｔｈｍ ｗｈｉｃｈ ｃａｎ ｅｆｆｅｃｔｉｖｅｌｙ ｅｌｉｍｉｎａｔｅ ｔｈｅ ｎｅｇａｔｉｖｅ ｅｆｆｅｃｔ ｏｎ ａｃｑｕｉｓｉｔｉｏｎ ａｎｄ ｔｒａｃｋｉｎｇ ｉｓ ｐｒｏｐｏｓｅｄ． Ｓｉｍｕｌａｔｉｏｎ ｒｅｓｕｌｔｓ ａｎｄ ｅｘｐｅｒｉｍｅｎｔａｌ ｄａｔａ ｖｅｒｉ－ ｆｙ ｔｈｅ ｅｆｆｅｅｔｉｖｅｎｅｓｓ ｏｆ ｔｈｅ ａｌｇｏｒｉｔｈｍ．
ＩＩ－ＡＮＡＬＹＳＩＳ ＯＦ ＡＧＣ ＴＥＣＨＮＯＬｏＧＹ Ｃｏｎｓｉｄｅｒｉｎｇ ｔｈｅ ｄｙｎａｍｉｃ ｒａｎｇｅ ｏｆ ｉｎｐｕｔ ｓｉｇｎａｌ ａｎｄ ｉａｍｍｉｎｇ ｒｅｓｉｓｔａｎｃｅ ｔｏｌｅｒａｎｃｅ，ｔｈｅ ｐｏｗｅｒ ｏｆ ｒｅｃｅｉｖｅｄ ｓｉｇｎａｌｓ ｃｈａｎｇｅｓ ｗｉｔｈｉｎ ａ ｌａｒｇｅ ｒａｎｇｅ ｗｈｉｃｈ ｓｈｏｕｌｄ ｂｅ ｐｒｏｃｅｓｓｅｄ ｂｙ ＡＧＣ ｍｏｄｕｌｅ．Ｔｏ ａｎａｌｏｇ ＡＧＣ ａｎｄ ｈｙｂｒｉｄ ＡＧＣ， ｔｈｅ ｗｏｒｋ ｓｔａｔｅ ｗｉｌｌ ｃｈａｎｇｅ ｗｉｔｈ ｉｎｐｕｔ ｐｏｗｅｒ ａｎｄ ｔｈｅ ｗｏｒｋ ｓｔａｔｅ ｏｆ ｖａｒｉａｂｌｅ ｇａｉｎ ａｍｐｌｉｆｉｅｒ ｉｓ ｃｌｏｓｅｌｙ ｒｅｌａｔｅｄ ｔｏ ｔｈｅ ｔｅｍｐｅｒａｔｕｒｅ，ｓｏ ｉｎｐｕｔ ｐｏｗｅｒ ｗｉｌｈｎｆｌｕｅｎｃｅ ｔｈｅ ｚｅｒｏ ｖａｌｕｅ ｓｔａｂｉｌｉｔｙ ｏｆ ｔｈｅ ｒｅｃｅｉｖｅｒｓ．１ｎ ｃｏｎｔｒａｓｔ．ｄｉｇｉｔａｌ ＡＧＣ ｓｈｏｗｎ ｉｎ Ｆｉｇｕｒｅ １ ｈａｓ ｂｅｔｔｅｒ ｐｅｒｆｏｒｍａｎｃｅ ｏｎ ｚｅｒｏ ｖａｌ－ ｔｉｅ ｓｔａｂｉｌｉｔｙ．Ａｆｔｅｒ ＡＤ ｃｏｎｖｅｒｓｉｏｎ，ａｄｊｕｓｔ ｓｉｇｎａｌ ａｍｐｌｉｔｕｄｅ ａｎｄ ｓｅｎｄ ｔｈｅ ａｄｊｕｓｔｍｅｎｔ ｒｅｓｕｌｔｓ ｔｏ ｔｈｅ ｓｉｇｎａｌ ｐｒｏｃｅｓｓｅｒ．Ｔｈｅ ａｄｊｕｓｔｍｅｎｔ ｆａｃｔｏｒ ｉｓ ｏｂｔａｉｎｅｄ ｆＦＯ１ＴＩ ａｍｐｌ ｉｔｕｄｅ ｄｅｔｅｃｔｉｏｎ，ｔｈｒｅｓｈｏｌｄ ｃｏｍｐａｒｉｓｏｎ ａｎｄ ｌｏｏｐ ｆｉｌｔｅｒ，ｗｈｉｃｈ ａｒｅ ｉｍｐｌｅ— ｍｅｎｔｅｄ ｉｎ ｄｉｇｉｔａｌ ｗａｙ．Ｔｈｅｒｅｆｏｒｅ，ｄｉｇｉｔａｌ ＡＧＣ ｃａｎ ｅｎｓｕｒｅ ｒｅｃｅｉｖｉｎｇ ｃｈａｎｎｅｌ ｗｏｒｋ ｓｔａｂｌｙ ｕｎｄｅｒ ｄｉｆｆｅｒｅｎｔ ｉｎｐｕｔ ｐｏｗｅｒ．Ｍｏｒｅｏｖｅｒ，ｄｉｇｉｔａｌ ＡＧＣ ｈａｓ ｃｏｎｓｔａｎｔ ｐｒｏｃｅｓｓｉｎｇ ｄｅｌａｙ ｗｈｉｃｈ ｉｓ