几个常用的Verilog小程序

几个常用的Verilog小程序

(1) 8位串并转换

module haidaoqi(clk,rst,din,dout);

input clk,rst,din;

output [7:0] dout;

reg[7:0] data,dout;

reg[2:0] cnt;

always@(posedge clk or posedge rst)

if(rst) //复位高有效

data <=8'b0;

else

data<= {data[7:0],din};//din是输入串行数据，假设输入数据高位在前

//这是一个移位寄存器

always@(posedge clk or posedge rst)

if(rst)

cnt <= 3'b0;

else

if(cnt == 3'b111)

cnt <= 3'b0;

else

cnt <= cnt +1;//计数器，用来计算移位次数，移位8次在以

后产生一个有效数据

always@(posedge clk or posedge rst)

if(rst)

dout <= 8'b0;

else

if(cnt == 3'b111)

dout <= data;//如果计数器记到7，那么输出一个有效的8位数据

else

dout <= 0;

endmodule

(2) 8 位数据寄存器

module reg8(out_data,in_data,clk,clr);

output[7:0] out_data;

input[7:0] in_data;

input clk,clr;

reg[7:0] out_data;

always @(posedge clk or posedge clr)

begin

if(clr) out_data <=0;

else out_data <=in_data;

end

endmodule

(3) 8位数据锁存器

module haidaoqi(data_out,data_in,clk,rst); output[7:0] data_out;

input[7:0] data_in;

input clk,rst;

reg[7:0] data_out;

always @(rst or clk or data_in)

begin

if (rst) data_out<=8'b0;

else if (clk) data_out<=data_in;

else data_out<=8'b0;

end

endmodule

(4) 8位并串转换

module haidaoqi(rst,clk,tem,D1);

input rst,clk;

input [7:0] tem;

output D1;

reg D1;

wire [7:0] tem;

reg [2:0] counter;

always @(posedge clk or posedge rst) begin

if (rst)

begin

counter<=3'b0;

D1<=0;

end

else if(counter==7)

begin

counter<=3'b0;

D1<=0;

end

else

begin

counter<=counter+1;

D1=tem[counter];

end

end

endmodule

(5) clk一分四/八频

module haidaoqi(clk1,clk2,clk,rst);

output clk1,clk2;

input clk,rst;

reg clk1,clk2;

reg[7:0] state;

parameter S0=8'b00000000,

S1=8'b00000001,

S2=8'b00000010,

S3=8'b00000100,

S4=8'b00001000,

S5=8'b00010000,

S6=8'b00100000,

S7=8'b01000000,

S8=8'b10000000;

always@(posedge clk)

if(rst)

begin

clk1<=0;

clk2<=0;

state<=S0;

end

else

begin

case(state)

S0:state<=S1;

S1:state<=S2;

S2:

begin

clk1<=~clk1;

state<=S3;

end

S3:state<=S4;

S4:

begin

clk1<=~clk1;

clk2=~clk2;

state<=S5;

end

S5:state<=S6;

S6:

begin

clk1<=~clk1;

state<=S7;

end

S7:state<=S8;

S8:

begin

clk1<=~clk1;

clk2=~clk2;

state<=S0;

end

default:state<=S0;

endcase

end

endmodule

(6) 8位比较器

module haidaoqi(a,b,en,y);

input[width-1:0] a,b;

input en;

output y;

reg y;

parameter width=8;

always@(a or b)

if(en)

begin

if(a==b)

y<=1;

else

y<=0;

end

else

y<=0;

endmodule

(7)带使能端的ram

module haidaoqi(dataout,datain,ena,read,write); output[7:0] dataout;

input[7:0] datain;

input ena,read,write;

reg[7:0] ram[1:0];

parameter addr=1'b0;

assign dataout=(read && ena)?ram[addr]:8'hzz;

always@(posedge write)

begin

ram[addr]<=datain;

end

endmodule

(8) 译码器

module haidaoqi(ma,a,b,c,d,e);

input[2:0] ma;

output a,b,c,d,e;

reg a,b,c,d,e;

always@(ma)

case(ma)

3'b001:{a,b,c,d,e}<=5'b10000;

3'b010:{a,b,c,d,e}<=5'b01000;

3'b011:{a,b,c,d,e}<=5'b00100;

3'b100:{a,b,c,d,e}<=5'b00010;

3'b101:{a,b,c,d,e}<=5'b00001;

default:{a,b,c,d,e}<=5'bzzzzz;

endcase

endmodule

(9) 带清0/置1端的T触发器

module T-trigger(clk,T,R,S,Q,Q1);

input clk,T,R,S;

output Q,Q1;

reg Q,Q1;

always @(posedge clk or negedge R or negedge S) begin

if(!R)

begin

Q <= 1'b0;

Q1<=1'b1;

end

else if(!S)

begin

Q <=1'b1;

Q1<=1'b0;

end

else if(T)

begin

Q<=~Q;

Q1<=~Q1;

end

end

endmodule

(10)带起始位识别的串并转换（存8位有效数据）module SIM(din,clk,rst,dout,ok);

input din,clk,rst;

output ok;

output[7:0] dout;

reg[7:0] indata_buf,dout;

reg[3:0] counter;

reg[2:0] state;

reg[1:0] cnt;

reg tag,ok;

integer bitpos=7;

parameter s0=0,s1=1,s2=2,s3=3,s4=4;

always@(posedge clk or posedge rst)

if(rst)

begin

state<=0;

counter<=0;

tag<=0;

indata_buf<=8'bz;

cnt<=0;

bitpos=7;

end

else case(state)

s0:begin

tag=0;

ok<=tag;

if(din)

begin

cnt<=cnt+1;

state<=s0;

if(cnt==3)

begin

state<=s1;

cnt<=0;

end

end

else begin

counter<=0;

state<=s0;

end

end

s1:begin

if(counter==7)

begin

state<=s2;

counter<=0;

end

else

begin

counter<=counter+1;

state<=s0;

end

end

s2:if(!din)

state<=s3;

else

state<=s0;

s3:begin

if(bitpos==-1)

begin

bitpos=7;

state<=s4;

end

else

begin

indata_buf[bitpos]<=din;

bitpos<=bitpos-1;

state<=s3;

end

end

s4:begin

tag=1'b1;

ok<=tag;

dout<=indata_buf;

state<=s0;

end

endcase

endmodul

(11)移位寄存器（9位有效数据输出）module ywjc(din,clk,rst,dout,ok);

input din,clk,rst;

output ok;

output[8:0] dout;

reg[8:0] indata_buf,dout;

reg[3:0] counter;

reg[2:0] state;

reg[1:0] cnt;

reg tag,ok;

integer bitpos=8;

parameter s0=0,s1=1,s2=2,s3=3,s4=4;

always@(posedge clk or posedge rst) if(rst)

begin

state<=0;

counter<=0;

tag<=0;

indata_buf<=9'bz;

cnt<=0;

bitpos=8;

end

else case(state)

s0:begin

tag=0;

ok<=tag;

begin

cnt<=cnt+1;

state<=s0;

if(cnt==3)

begin

state<=s1;

cnt<=0;

end

end

else begin

counter<=0;

state<=s0;

end

end

s1:begin

if(counter==8)

begin

state<=s2;

counter<=0;

end

else

counter<=counter+1;

state<=s0;

end

end

s2:if(!din)

state<=s3;

else

state<=s0;

s3:begin

if(bitpos==-1)

begin

bitpos=8;

state<=s4;

end

else

begin

indata_buf[bitpos]<=din;

bitpos<=bitpos-1;

state<=s3;

end

end

s4:begin

tag=1'b1;

ok<=tag;

dout<=indata_buf;

state<=s0;

end

endcase

endmodule