超大规模集成电路第九次作业2016秋-段成华

超大规模集成电路第九次作业2016秋-段成华

————————————————————————————————作者：————————————————————————————————日期：

Assignment 9

1. Design an 8-bit up and down synchronous counter in VHDL with the following features:

(1)The same ports are used for signals to be inputted and outputted. The ports are

bi-directionally buffered (three-state).

(2)The counter is with an asynchronous reset that assigns a specific initial value

for counting.

(3)The counter is with a synchronous data load control input for a new value of

counting and an enable control input for allowing the up and down counting.

The load control input has a priority over the enable control input. This implies that when the load operation is in process the counter operation is prohibited.

(4)Some data types, such as STD_LOGIC, UNSIGNED, SIGNED and INTEGER,

may be used.

Synthesize the design. Create a set of reasonable input waveforms for your design and complete both behavioral and post-place&route simulations with internal signals and/or variables included in waveform or list windows.

Solution:代码如下：

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity count_8_bidir is

Port (

clk : in STD_LOGIC;

rst : in STD_LOGIC;

load : in STD_LOGIC;

enable : in STD_LOGIC;

cnt : inout STD_LOGIC_VECTOR (7 downto 0)); end count_8_bidir;

architecture Behavioral of count_8_bidir is

signal cnt_in: STD_LOGIC_VECTOR (7 downto 0);

signal cnt_out: STD_LOGIC_VECTOR (7 downto 0);

begin

pro0:process(oe,cnt_out,cnt)

begin

if(load='1')then

cnt <= (others=>'Z');

cnt_in <= cnt;

else

cnt <= cnt_out;

end if;

end process;

pro1:process(clk,rst)

begin

if(rst='1')then

cnt_out <= (others=>'0');

elsif rising_edge(clk)then

if(load='1')then

cnt_out <= cnt_in;

elsif(enable='1')then

cnt_out <= cnt_out + 1;

else

cnt_out <= cnt_out - 1;

end if;

end if;

end process;

end Behavioral;

解释代码：这里有两个进程，进程0时是用来控制三态门控制的双向端口。当cnt作为输入时（load='1'），把cnt赋给cnt_in（初值装载），然后置cnt为高阻状态；否则，即cnt作为输出时（load='0'），把cnt_out（计数器计数输出值）赋给cnt。进程1的作用是：当复位信号rst='1'，计数器输出cnt_out为全0，否则在时钟的上升沿检测cnt端口是作为输入还是作为输出，当作为输入时（load='1'），把cnt_in中的数取进来，然后当up_down='0'时，进行加法运算，否则做减法运算，同时可以和进程0配合当load='0'，将数值从cnt_out输出到cnt。

TestBench代码：

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY count_8_bidir_tb IS

END count_8_bidir_tb;

ARCHITECTURE behavior OF count_8_bidir_tb IS

-- Component Declaration for the Unit Under Test (UUT) COMPONENT count_8_bidir

PORT(

oe : IN std_logic;

clk : IN std_logic;

rst : IN std_logic;

load : IN std_logic;

enable : IN std_logic;

cnt : INOUT std_logic_vector(7 downto 0)

);

END COMPONENT;

--Inputs

signal oe : std_logic := '0';

signal clk : std_logic := '0';

signal rst : std_logic := '0';

signal load : std_logic := '0';

signal enable : std_logic := '0';

--BiDirs

signal cnt : std_logic_vector(7 downto 0);

-- Clock period definitions

constant clk_period : time := 100ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: count_8_bidir PORT MAP (

oe => oe,

clk => clk,

rst => rst,

load => load,

enable => enable,

cnt => cnt

);

-- Clock process definitions clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2; end process;

-- Stimulus process

stim_proc: process

begin

rst<='1';

load<='0';

enable<='1';

cnt<=(others=>'Z');

wait for 100 ns;

rst<='0';

wait for 500 ns;