FPGA实验报告

FPGA实验一、实验目的1. 熟悉Quartus Ⅱ软件基本使用方法；2. 掌握电路的基本设计方法；3. 掌握电路的基本仿真方法；4. 掌握电路的基本下载方法；5. 学习状态机的设计技巧；6. 掌握CASE 语句的使用；7. 掌握时钟分频电路的HDL 设计；8. 掌握CASE 语句的使用；9. 掌握VHDL模块化程序设计方式；10. 学习VHDL程序的设计技巧；11. 掌握VHDL语言译码电路的设计；12. 掌握选择信号赋值语句的设计方法；二、实验器材1. KH-310 下载板；2. KH-310 LED 显示模块；3. KH-310 时钟模块；5．KH-310 七段数码管模块。

4. 计算机。

三、实验原理乒乓球机：乒乓球游戏机是用8～16 个发光二极管代表乒乓球台，中间两个发光二极管兼作乒乓球网，用点亮的发光二极管按一定方向移动来表示球的运动。

另外设置发球开关：Af、Bf；和接球开关Aj、Bj。

利用若干七段数码管作为计分牌。

甲乙双方按乒乓球比赛规则来操作开关。

当甲方按动发球开关Af 时，靠近甲方的第一个灯亮，然后顺序向乙方移动。

当球过网后，乙方可以接球，接球后灯反方向运动，双方继续比赛，如果一方提前击球（过网击球）或未击到球，则判失分，对方加分。

重新发球后继续比赛。

译码器：状态机：状态机的一个常用的用处是构成控制步进电机的逻辑电路。

表1给出了用于顺时针和逆时针驱动步进电机的二进制码。

状态机的设计中我们需要提到一些称为常态和次态的状态，表2列举了步进电机的状态转换顺序。

时钟：图3.27四、实验内容1.用VHDL 语言和原理图分别完成设计、仿真和下载基本逻辑门电路半加器的过程：输入：a，b；输出：求和sum，进位c；2. 控制8 个LED 进行花式显示，设计四种显示模式：1. 从左到右逐个点亮LED；2. 从右到左逐个点亮LED；3. 从两边到中间逐个点亮LED；4. 从中间到两边逐个点亮LED。

四种模式循环切换，由复位键rst 控制系统的运行与停止。

3. 设计一个乒乓球游戏机，模拟乒乓球比赛基本过程和规则，并能自动裁判和计分。

4. 设计一个简单的指令译码器，按指定的要求，对两个逻辑变量进行运算，并将运算的结果在发光二极管上显示。

5.使用VHDL语言，编制一个4相步进电机控制程序，由发光二极管指示步进电机的相序，要求正反转控制，通过改变时钟频率实现调速。

6. 设计一个电子钟，要求可以显示时、分、秒，用户可以设置时间且需要设置的时间显示要求闪烁。

跑马灯：输入信号：时钟clk 接10Hz 输入(SW7) P152；复位rst 接拨动开关I01（拨码开关SW3 左1）P1 ；输出信号：8 位输出信号接LED 模块O25—O32。

P43～P50；乒乓球：输入信号：控制时钟CLK：可调时钟SW7 输入；接发球输入Af，Aj，Bf，Bj：脉冲发生器EPI0～EPI3（Pin236 Pin238 Pin237 Pin239）；系统复位Clr：拨码开关I01；输出信号：乒乓球信号shift[15..0]：LED 显示模块O25～O40；计分输出q[6..0]：七段数码管O56～O50（Pin79～Pin73）（JP1）；Sellread[3..0]：数码管选择SO61～SO58（Pin86～Pin83）（数码管跳线接左侧扫描方式）。

译码器：输入信号：译码器输入开关c、b、a 接拨动开关I01（拨码开关SW3 左1 P1）、I02（拨码开关SW3 左2 P2）、I03（拨码开关SW3 左3 P3），输入数据data1、data2接IO9（拨码开关SW4 左1 P11）、IO10（拨码开关SW3 左2 P12）输出信号：LED 模块O25 P43；步进机：输入信号：时钟clk 接10Hz 输入(SW7) P152；方向dir接拨动开关I01（拨码开关SW3 左1）P1 ；输出信号：4 位输出信号接LED 模块O25—O28。

P43～P46；电子钟：输入信号：时钟clk：接开发板可调时钟SW7（P152），选择100KHz 频率；模式选择mode：接脉冲发生器模块EPI0；P236时间设定set：接脉冲发生模块EPI1；P238输出信号：Seg7[7.. 0]接数码管段扫描信号O50～O56、SO57；P73、74、75、76、77、78、79、82 Segctr[7..0]接数码管位选显示信号S O58～S O65；P83、84、85、86、87、88、93、94 CLR ；P1 清零信号1. 新建文本文件2. 建立工程项目3. 编译并综合4. 设计仿真5. 管脚的分配与定位6. 硬件连接7. 器件下载编程与硬件实现七、实验操作1. 跑马灯：下载程序，将SW7 拨至第二段（10Hz），拨码开关SW3 的IO1 拨至ON 的位置，此时，LED 灯的前8 位会有规律的闪烁。

2. 乒乓球：下载程序，将SW3 的IO1 拨到ON 后可进行比赛，PULS1 为甲方发球，PULS2 为甲方接球，PULS3 为乙方发球，PULS4 为乙方接球。

LED 灯中，始终点亮的代表球网，将SW7 拨至第四段的位置。

点击发球之后，双方可进行比赛，比赛规则参照实验原理部分。

3. 译码器：改变译码器的输入值（a、b、c）和输入数据值（data1、data2），输出数据按设计值输出4. 步进机：下载程序，将SW7 拨至第二段（10Hz），此时，LED 灯的前1 位会有规律的闪烁。

改变方向开关的电平信号，指示灯的移动方向立即改变。

5. 电子钟：下载程序，按PULSE1 可进行时、分、秒的切换，按PULSE2 可以对时，分，秒进行设置，I01为系统的使能，I01 为off 时开始计时。

1.半加器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity halfadd isport(a:in std_logic;b:in std_logic;sum:out std_logic;c,d:out std_logic);end;architecture main of halfadd isbeginc<=a and b;sum<=a xor b;end;2.跑马灯library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity led isport(clk:in std_logic;rst:in std_logic;q :out std_logic_vector(7 downto 0));end;architecture led of led isconstant s0:std_logic_vector(1 downto 0):="00"; --模式1constant s1:std_logic_vector(1 downto 0):="01"; --―模式2constant s2:std_logic_vector(1 downto 0):="10"; --―模式3constant s3:std_logic_vector(1 downto 0):="11"; --―模式4signal present:std_logic_vector(1 downto 0); -- ――当前模式signal q1:std_logic_vector(7 downto 0);signal count:std_logic_vector(3 downto 0);beginprocess(rst,clk)beginif(rst='0')then -- ――系统初始化present<=s0;q1<=(others=>'0');elsif(clk'event and clk='1')thencase present iswhen s0 => if(q1="00000000")then --――S0模式：从左到右逐个点亮LEDq1<="10000000";else if(count="0111")thencount<=(others=>'0');q1<="00000001";present<=s1;else q1<=q1(0) & q1(7 downto 1);count<=count+1;present<=s0;end if;end if;when s1 => if(count="0111")then --S1模式：从右到左逐个点亮LEDcount<=(others=>'0');q1<="10000001";present<=s2;else q1<=q1(6 downto 0) & q1(7);count<=count+1;present<=s1;end if;when s2 => if(count="0011")then --S2模式：从两边到中间逐个点亮LEDcount<=(others=>'0');q1<="00011000";present<=s3;else q1(7 downto 4)<=q1(4) & q1(7 downto 5);q1(3 downto 0)<=q1(2 downto 0) & q1(3);count<=count+1;present<=s2;end if;when s3 => if(count="0011")then --S3模式：从中间到两边逐个点亮LEDcount<=(others=>'0');q1<="10000000";present<=s0;else q1(7 downto 4)<=q1(6 downto 4) & q1(7);q1(3 downto 0)<=q1(0) & q1(3 downto 1);count<=count+1;present<=s3;end if;end case;end if;end process;q<=q1;end;3.乒乓球Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity corna isport (clr,af,aj,bf,bj,clk:in std_logic;shift:out std_logic_vector(15 downto 0);ah,al,bh,bl: out std_logic_vector(3 downto 0));end corna;architecture corna_arc of corna issignal amark,bmark : integer;signal clk1:std_logic;signal fen:std_logic_vector(9 downto 0);beginprocessbeginwait until clk='1';fen<=fen+1;clk1<=fen(7);end process;process(clr,clk1)variable a,b : std_logic;variable she: std_logic_vector(15 downto 0); beginif clr='0' thena:='0';b:='0';she:="0000000000000000";amark<=0;bmark<=0;elsif clk1'event and clk1 ='1' thenif a='0' and b='0' and af='1' thena:='1';she:="1000000000000000";elsif a='0' and b='0' and bf='1' thenb:='1';she:="0000000000000001";elsif a='1' and b='0' thenif she>128 thenif bj='1' thenamark<=amark+1;a:='0';b:='0';she:="0000000000000000";elseshe:='0'&she(15 downto 1);end if;elsif she=0 thenamark<=amark+1;a:='0';b:='0';elseif bj='1' thena:='0';b:='1';elseshe:='0'& she(15 downto 1);end if;end if;elsif a='0' and b='1' thenif she<256 and she/=0 thenif aj='1' thenbmark<=bmark+1;a:='0';b:='0';she:="0000000000000000";elseshe:=she(14 downto 0)&'0';end if;elsif she=0 thenbmark<=bmark+1;a:='0';b:='0';elseif aj='1' thena:='1';b:='0';elseshe:=she(14 downto 0)&'0';end if;end if;end if;end if;shift<=she;end process;process(clk,clr,amark,bmark)variable aha,ala,bha,bla: std_logic_vector(3 downto 0); variable tmp1,tmp2: integer;beginif clr='0' thenaha:="0000";ala:="0000";bha:="0000";bla:="0000";tmp1:=0;tmp2:=0;elsif clk'event and clk='1' thenif amark>tmp1 thenif ala="1001" thenala:="0000";aha:=aha+1;tmp1:=tmp1+1;elseala:=ala+1;tmp1:=tmp1+1;end if ;end if;if bmark>tmp2 thenif bla="1001" thenbla:="0000";bha:=bha+1;tmp2:=tmp2+1;elsebla:=bla+1;tmp2:=tmp2+1;end if ;end if;end if;al<=ala;bl<=bla;ah<=aha;bh<=bha;end corna_arc;Library ieee;use ieee.std_logic_1164.all;entity ch41a isport(sel:in std_logic_vector(2 downto 0);d0,d1,d2,d3: in std_logic_vector(3 downto 0);q: out std_logic_vector(3 downto 0));end ch41a;architecture ch41_arc of ch41a isbeginprocess(sel)begincase sel iswhen "100"=>q<=d2;when "101"=>q<=d3;when "000"=>q<=d0;when others=>q<=d1;end case;end process;end ch41_arc;Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity sel isport (clk:in std_logic;sell:out std_logic_vector(2 downto 0));end sel;architecture sel_arc of sel isbeginprocess(clk)variable tmp: std_logic_vector(2 downto 0);beginif clk'event and clk='1' thenif tmp="000" thentmp:="001";elsif tmp="001" thentmp:="100";elsif tmp="100" thentmp:="101";elsif tmp="101" thentmp:="000";end if;end if;sell<=tmp;end process;Library ieee;use ieee.std_logic_1164.all;entity disp isport (d:in std_logic_vector(3 downto 0);q:out std_logic_vector(6 downto 0));end disp;architecture disp_arc of disp isbeginprocess(d)begincase d iswhen "0000"=>q<="0111111";when "0001"=>q<="0000110";when "0010"=>q<="1011011";when "0011"=>q<="1001111";when "0100"=>q<="1100110";when "0101"=>q<="1101101";when "0110"=>q<="1111101";when "0111"=>q<="0100111";when "1000"=>q<="1111111";when others=>q<="1101111";end case;end process;end disp_arc;Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity pingpong isport (clr,af,aj,bf,bj,clk:in std_logic;shift:out std_logic_vector(15 downto 0);q: out std_logic_vector(6 downto 0);net: out std_logic_vector(1 downto 0);sellread:out std_logic_vector(3 downto 0));end pingpong;architecture pingpong of pingpong iscomponent corna isport (clr,af,aj,bf,bj,clk:in std_logic;shift:out std_logic_vector(15 downto 0);ah,al,bh,bl: out std_logic_vector(3 downto 0));end component;component ch41a isport(sel:in std_logic_vector(2 downto 0);d0,d1,d2,d3: in std_logic_vector(3 downto 0);q: out std_logic_vector(3 downto 0));end component;component sel isport (clk:in std_logic;sell:out std_logic_vector(2 downto 0));end component;component disp isport (d:in std_logic_vector(3 downto 0);q:out std_logic_vector(6 downto 0));end component;signal i1,i2,i3,i4,i5: std_logic_vector(3 downto 0); signal i6:std_logic_vector(2 downto 0);beginu1:corna port map(clr,af,aj,bf,bj,clk,shift,i1,i2,i3,i4); u2:ch41a port map(i6,i2,i1,i4,i3,i5);u3:sel port map(clk,i6);u4:disp port map(i5,q);net <= "11";--with i6 select--sellread<="1000" when "000"--"0100" when "001"-- "0010" when "100"-- "0001" when others;sellread<="1000" when i6="000" else"0100" when i6="001" else"0010" when i6="100" else"0001" ;--sellread<=i6;end pingpong;4.指令译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity decoder isport(a,b,c:in std_logic;data1,data2:in std_logic;dataout:out std_logic);end decoder;architecture data_flow of decoder issignal inter:std_logic_vector(2 downto 0);begin inter<=c&b&a;with inter selectdataout<=data1 and data2 when "001",data1 or data2 when "010",data1 nand data2 when "011",data1 xor data2 when "100",data1 xnor data2 when "101",'Z' when others;end data_flow;5.状态机library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity state_stepper_b isport(clk,dir:in std_logic;q:out std_logic_vector(3 downto 0));end state_stepper_b;architecture arc of state_stepper_b istype state_type is (s0,s1,s2,s3);signal state:state_type;beginprocess(clk)beginif clk'event and clk='1' thenif dir='1' thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s0;end case;elsecase state iswhen s0=> state <=s3;when s1=> state <=s0;when s2=> state <=s1;when s3=> state <=s2;end case;end if;end if;end process;with state selectq<= "0001" when s0,"0010" when s1,"0100" when s2,"1000" when s3;end arc;6.时钟library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity BCD isport(DataIn:in std_logic_vector(5 downto 0);BCDOut:out std_logic_vector(7 downto 0) );end BCD;architecture main of BCD isbeginprocess(DataIn)variable inter:std_logic_vector(13 downto 0);variable test:std_logic_vector(3 downto 0);begininter:="00000000"&DataIn;for i in 0 to 5 looptest:=inter(9 downto 6);if(test>=5) thentest:=test+3;inter(9 downto 6):=test;end if;inter:=inter(12 downto 0)&'0';end loop;BCDOut<=inter(13 downto 6);end process;end main;Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Clock isport( mode, set, clr, clk :in std_logic;seg7, segctr :out std_logic_vector(7 downto 0));end entity;ARCHITECTURE arch OF Clock ISsignal state: std_logic_vector(1 downto 0);signal Hour, Min, Sec: std_logic_vector(5 downto 0); signal BCDH, BCDM, BCDS: std_logic_vector(7 downto 0); signal segDat: std_logic_vector(3 downto 0);signal blink: std_logic_vector(2 downto 0);signal set_reg, blink_clk: std_logic;component BCDport(DataIn : in std_logic_vector(5 downto 0);BCDOut : out std_logic_vector(7 downto 0));end component;BEGINprocess(mode)beginif (clr='1') thenstate<="00";elseif (mode'event and mode='1') thenstate<=state+1;end if;end if;end process;process(state, blink_clk)begincase state iswhen "00" => blink<="000";when "01" => blink<=(2=>blink_clk, others=>'0'); when "10" => blink<=(1=>blink_clk, others=>'0'); when "11" => blink<=(0=>blink_clk, others=>'0'); end case;end process;process(clk)variable blink_cnt: std_logic_vector(13 downto 0); beginif (clr='1') thenblink_clk<='0';blink_cnt:=(others=>'0');elseif (clk'event and clk='1') thenif (blink_cnt="11000011010011") thenblink_cnt:=(others=>'0');blink_clk<=not blink_clk;elseblink_cnt:=blink_cnt+1;end if;end if;end if;end process;process(clk, state)variable clk_cnt: std_logic_vector(16 downto 0); beginif (clr='1') thenHour<="000000"; Min<="000000"; Sec<="000000"; clk_cnt:=(others=>'0');set_reg<='0';elseif (clk'event and clk='1') thencase state iswhen "00" =>if (clk_cnt="11000011010011111") thenclk_cnt:=(others=>'0');if (Sec=59) thenSec<=(others=>'0');if (Min=59) thenMin<=(others=>'0');if (Hour=23) thenHour<=(others=>'0');else Hour<=Hour+1;end if;else Min<=Min+1;end if;else Sec<=Sec+1;end if;else clk_cnt:=clk_cnt+1;end if;when "01" =>if (set='1') thenif set_reg='0' thenset_reg<='1';if (Hour=23) thenHour<=(others=>'0');else Hour<=Hour+1;end if;end if;elseset_reg<='0';end if;when "10" =>if (set='1') thenif set_reg='0' thenset_reg<='1';if (Min=59) thenMin<=(others=>'0');else Min<=Min+1;end if;end if;elseset_reg<='0';end if;when "11" =>if (set='1') thenif set_reg='0' thenset_reg<='1';if (Sec=59) thenSec<=(others=>'0');else Sec<=Sec+1;end if;end if;elseset_reg<='0';end if;end case;end if;end if;end process;HBCD : BCDport map(Hour, BCDH);MBCD : BCDport map(Min, BCDM);SBCD : BCDport map(Sec, BCDS);process(clk)variable cnt :std_logic_vector(2 downto 0); beginif (clr='1') thencnt:=(others=>'0');segCtr<=(others=>'0');elseif (clk'event and clk='1') thencnt:=cnt+1;case cnt iswhen "000" =>segDat<=BCDH(7 downto 4)or (blink(2) & blink(2) & blink(2) & blink(2)); segctr<="10000000";when "001" =>segDat<=BCDH(3 downto 0)or (blink(2) & blink(2) & blink(2) & blink(2)); segctr<="01000000";when "010" =>segDat<="1010";segctr<="00100000";when "011" =>segDat<=BCDM(7 downto 4)or (blink(1) & blink(1) & blink(1) & blink(1)); segctr<="00010000";when "100" =>segDat<=BCDM(3 downto 0)or (blink(1) & blink(1) & blink(1) & blink(1)); segctr<="00001000";when "101" =>segDat<="1010";segctr<="00000100";when "110"=>segDat<=BCDS(7 downto 4)or (blink(0) & blink(0) & blink(0) & blink(0)); segctr<="00000010";when "111"=>segDat<=BCDS(3 downto 0)or (blink(0) & blink(0) & blink(0) & blink(0)); segctr<="00000001";end case;end if;end if;end process;process(segDat)begincase segDat iswhen "0000" => seg7<="11111100"; when "0001" => seg7<="01100000"; when "0010" => seg7<="11011010"; when "0011" => seg7<="11110010"; when "0100" => seg7<="01100110"; when "0101" => seg7<="10110110"; when "0110" => seg7<="10111110"; when "0111" => seg7<="11100000"; when "1000" => seg7<="11111110"; when "1001" => seg7<="11110110"; when "1010" => seg7<="00000010"; when others => seg7<="00000000";end case;end process;END arch;测验题译码器library ieee;use ieee.std_logic_1164.all;entity dec isport(signal cba: in std_logic_vector(2 downto 0);signal G: in std_logic_vector(1 downto 0);signal y: out std_logic_vector(7 downto 0));end dec;architecture behavior of dec isbeginprocess(cba,G)beginy<="11111111";if(G="10") thencase cba iswhen "000"=>y(0)<='0';when "001"=>y(1)<='0';when "010"=>y(2)<='0';when "011"=>y(3)<='0';when "100"=>y(4)<='0';when "101"=>y(5)<='0';when "110"=>y(6)<='0';when "111"=>y(7)<='0';when others=>null;end case;else y<="11111111";end if;end process;end behavior;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity state_stepper_b isport(clk,dir:in std_logic;q:out std_logic_vector(7 downto 0));end state_stepper_b;状态机architecture arc of state_stepper_b istype state_type is (s0,s1,s2,s3,s4,s5,s6,s7);signal state:state_type;beginprocess(clk)beginif clk'event and clk='1' thenif dir='1' thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s6;when s6=> state <=s7;when s7=> state <=s0;end case;else state<=s0;end if;end if;end process;with state selectq<= "00000001" when s0,"00000011" when s1,"00000111" when s2,"00001111" when s3,"00010000" when s4,"00110000" when s5,"01110000" when s6,"11110000" when s7;end arc;八、实验感想通过FPGA的实验更好的认识了编程预言在模拟开发中的应用学习了Quartus Ⅱ软件基本使用方法；掌握了VHDL模块化程序设计方式；.学习VHDL程序的设计技巧；掌握VHDL语言译码电路的设计。