时钟设计

begin
if(!reset)
begin
{timing,alarming,adjusting}<=3'b100;
cnt<=0;
end
else if(load)
begin
{timing,alarming,adjusting}<=3'b100;
cnt<=0;
end
else if(cnt==0) begin {timing,alarming,adjusting}<=3'b001;cnt<=1; end
end
else if(adjusting==state)
begin
if(!load)
begin
Sec_1_temp<=pre_sec_1;
Sec_10_temp<=pre_sec_10;
Min_1_temp<=pre_min_1;
Min_10_temp<=pre_min_10;
end
end
else begin
else pre_sec_10<=pre_sec_10+1'b1;end
else if(bit_sel==2)
begin if(pre_min_1==9) pre_min_1<=0;
else pre_min_1<=pre_min_1+1'b1;end
else
begin if(pre_min_10==5) pre_min_10<=0;
else if(bit_sel==2)
begin if(pre_min_1==0) pre_min_1<=9;
else pre_min_1<=pre_min_1-1'b1;end
else
begin if(pre_min_10==0) pre_min_10<=5;
else pre_min_10<=pre_min_10-1'b1;end
reg[12:0]t;
reg state=1;
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
clk_10hz<=0;
cnt<=0;
end
else
begin//fen pin 256hz
if(cnt==2500000)
begin
clk_10hz=!clk_10hz;
if((state==alarming)||(state==timing))
begin
if(Sec_1_temp==9)
begin
Sec_1_temp<=0;
if(Sec_10_temp==5)
begin
Sec_10_temp<=0;
if(Min_1_temp==9)
begin
Min_1_temp<=0;
Sec_1<=pre_sec_1;
Sec_10<=pre_sec_10;
Min_1<=pre_min_1;
else if(state==adjusting)
state<=alarming;
else if(state==alarming)
state<=timing;
else state<=timing;
end
always @(negedge reset or negedge model or posedge load)
begin
if(bit_sel==0)
begin if(pre_sec_1==0) pre_sec_1<=9;
elsepre_sec_1<=pre_sec_1-1'b1;end
else if(bit_sel==1)
begin if(pre_sec_10==0) pre_sec_10<=5;
else pre_sec_10<=pre_sec_10-1'b1;end
else
low_sw1<=low_sw;
always @(posedge clk)
begin
if(!model)
begine_sec_10<=Sec_10;
pre_min_1<=Min_1;
pre_min_10<=Min_10;
end
else if(low_sw2[0])// down action
end
always@(posedge clk or negedge reset) //消抖
if(!reset)
key<=2'b11;
else
key<={up,down};
always@(posedge clk or negedge reset)
if(!reset)
key1<=2'b11;
else
key1<=key;
end
else if(low_sw2[1])// up action
begin
if(bit_sel==0)
begin if(pre_sec_1==9) pre_sec_1<=0;
elsepre_sec_1<=pre_sec_1+1'b1;end
else if(bit_sel==1)
begin if(pre_sec_10==5) pre_sec_10<=0;
always@(negedge model or negedge reset or posedge load)
begin
if(!reset)
state<=timing;
else if(load==1)
state<=timing;
else if(state==timing)
state<=adjusting;
output [3:0]pre_sec_1,pre_sec_10,pre_min_1,pre_min_10;
reg [3:0]pre_sec_1,pre_sec_10,pre_min_1,pre_min_10;
reg state;
reg[1:0]cnt;
reg timing,alarming,adjusting;
Down：调整减1信号，高电平有效。
输出部分：
Alarm_out:闹铃信号，高电平有效；
Min_10:分钟十位信号；七段LED输出；
Min_1：分钟个位信号；七段LED输出；
Sec_10:秒的十位信号；七段LED输出；
Sec_1:秒的个位信号；七段LED输出；
电路功能描述：
1、可以实现校时；校时时可以实现对秒，十秒，分，十分位的分别调整；
reg[3:0]Min_10_temp,Min_1_temp,Sec_10_temp,Sec_1_temp;
output alarm_out;
reg alarm_out;
reg[3:0]Min_10_t,Min_1_t,Sec_10_t,Sec_1_t;
reg clk_10hz;
output clk_10hz;
if(!reset)
bit_sel<=0;
elsebegin
if(state==alarming||state==adjusting)
begin
if(bit_sel==3)
bit_sel<=0;
else
bit_sel<=bit_sel+1'b1;
end //bit_sel=0 => sec_1;//bit_sel=1 =>sec_10 etc.
cnt<=0;
end
else
cnt<=cnt+1'b1;
end
end
always @(posedge clk_10hz or negedge reset)
if(!reset)
begin
Min_10_temp<=0;
Min_1_temp<=0;
Sec_10_temp<=0;
Sec_1_temp<=0;
end
end
always @(posedge clk_10hz )
if(state==alarming)
begin
if(!load)
begin
Min_10_t<=pre_min_10;
Min_1_t<=pre_min_1;
Sec_10_t<=pre_sec_10;
Sec_1_t<=pre_sec_1;
（2）掌握仿真工具的运用。
（3）掌握时钟计时基本编程原理和实现闹钟，调整功能。
二、实验内容
输入部分：
Reset：全局清零，高电平有效；
Load：数据载入，高电平有效。（解决同一时间多次载入问题）。
Clk：时钟信号。1024Hz；
Model：功能选择信号；
Sel：位选择信号，高电平有效；
Up：调整加1信号，高电平有效；
else if(cnt==1) begin {timing,alarming,adjusting}<=3'b010;cnt<=2; end
else if(cnt==2) begin {timing,alarming,adjusting}<=3'b100;cnt<=0; end
end
always @(posedge sel or negedge reset )// bit selcted for//adjust