caputer生成网表报错原因解析演示教学

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Cadence中Capture向Allegro中导入网表时的常见错误

一、Capture生成netlist的时候报错：1.Unable to open c:\Cadence\PSD_14.2\tools\capture\allegro.cfg for reading. Please correct the above error(s) to proceed错误解释：allegro.cfg文件找不到或allegro.cfg文件不能打开，这个问题的根源是，有可能每台电脑上安装Allegro的的位置不一样，allegro.cfg 文件找不到是理所当然的。

处理办法：点生成netlist，点setup，修改路径为capture\allegro.cfg所在路径，把allegro.cfg文件的位置选择你现在安装目录的文件位置。

2. Spawning... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "F:\gcht\CC2430\Projects\mysch.dsn" -n"C:\CADENCE\PSD_15.1\TOOLS\PROJECTS" -c"C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j"CC2430_DEMO"#1 Error [ALG0012] Property "PCB Footprint" missing from instance U3: SCHEMATIC1, PAGE1 (2.00, 2.10).#2 Error [ALG0012] Property "PCB Footprint" missing from instance C2: SCHEMATIC1, PAGE1 (2.30, 0.30).#17 Aborting Netlisting... Please correct the above errors and retry.错误解释：Error [ALG0012] Property "PCB Footprint" missing from part <Part Reference>: <Schematic> , <Page> (<LocationX> , <LocationY)>A PCB Footprint (JEDEC_TYPE in Allegro) is required for all parts in Allegro. Therefore all parts without this property are listed before aborting the netlisting. You can add the PCB Footprint property by selecting the part listed, then choosing Edit Properties from the pop-up menu and placing a value, such as dip14_3, on the part.在Allegro中，每个器件都需要一个PCB封装。

Cadence中Capture向Allegro中导入网表时的常见错误

处理办法：点生成netlist，点setup，修改路径为capture\allegro.cfg所在路径，把allegro.cfg文件的位置选择你现在安装目录的文件位置。

【免费下载】cadence生成网络表时出现如下错误解决办法

U(ZE0B5L5b%X;n4g Allegro对一些字符[例如"空格","小数点"等等]很在意,可以参阅相关文档的描述.（3）Error Illegal character "Dot(.)" found in "PCB Footprint"#1 Error [ALG0081] Illegal character "Dot(.)" found in "PCB Footprint" property for componen t instance C255: PG16_AC97, PG16_AC97 (226.06, 132.08) .封装命名不能包含“.”（4）Error Illegal character "Forward Slash(/)" found in "PCB Footprint" property#1 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance C255: PG16_AC97, PG16_AC97 (226.06, 132.08) .#2 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance D3: PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp (93.98, 33.02) .#3 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance C245: PG16_AC97, PG16_AC97 (205.74, 35.56) .封装命名不能包含“/”（5）比较隐藏的排除法Loading... E:\FPGA\SCH\allegro/pstchip.dat#34 WARNING(SPCODD-34): Expected ';' character on line 5308.Check the name and value syntax for invalid characters in theprimitive definition before the line number.ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the pac kaging operation did not complete. Check the pxl.log file for the errors causing this situ ation and package the design again.#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has enc ountered a null object ID. The design may not have been saved correctly. Save the sc hematic and rerun packaging.#187 Error [ALG0036] Unable to read logical netlist data.Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\motherb oard.dsn" -n "E:\FPGA\SCH\allegro" -c "D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"*** Done*******掌握排错方法，查找文件pstchip.dat，第on line 5308 看看错误，便可以解决（6）封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决********************************************************************************** Netlisting the design*********************************************************************************Design Name:E:\FPGA\SCH\basicboard.dsnNetlist Directory:E:\FPGA\SCH\allegroConfiguration File:D:\Cadence\SPB_16.2\tools\capture\allegro.cfgSpawning... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basic board.dsn" -n "E:\FPGA\SCH\allegro" -c "D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"#1 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property f or component instance MG2: Basic, PG06_Stepmotor (180.34, 83.82) .#2 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property f or component instance ISO1: Basic, PG05_DC Motor (134.62, 40.64) .#3 Info: PCB Editor does not support Dots(.), Forward Slash(/) and White space in foot print names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).#4 Aborting Netlisting... Please correct the above errors and retry.Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboa rd.dsn" -n "E:\FPGA\SCH\allegro" -c "D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"*** Done ***封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决（7）Warning#11 Warning [ALG0051] Pin "GND" is renamed to "GND#A6" after substituting illegal ch aracters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACO NFIG (2.40, 3.10).#12 Warning [ALG0051] Pin "GND" is renamed to "GND#A11" after substituting illegal c haracters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGAC ONFIG (2.40, 3.10).#13 Warning [ALG0051] Pin "GND" is renamed to "GND#A1" after substituting illegal ch aracters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACO NFIG (2.40, 3.10).#14 Warning [ALG0051] Pin "GND" is renamed to "GND#W8" after substituting illegal c haracters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGAC ONFIG (2.40, 3.10).这条警告信息，在命名规范的前提下就不考虑这个警告了。

ORCAD出ALLEGRO网表非法错误案例：

错误报告内容：Spawning... "D:\Cadence\SPB_16.5\tools\capture\pstswp.exe" -pst -d"e:\work\yuleying\hj-am13-mb-0.0.0\sch\hj-am13-mb-v000\hj-am13-mb-v000.dsn" -n "e:\work\yuleying\hj-am13-mb-0.0.0\sch\hj-am13-mb-v000\allegro" -c"D:\Cadence\SPB_16.5\tools\capture\allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint"-hpath "HPathForCollision"#1 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#2 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#3 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#4 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#5 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#6 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#7 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#8 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#9 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#10 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#11 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#12 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#13 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#14 ERROR(ORCAP-36055): Illegal character in \hj-am13-mb-v0.0.0(a10)\.#15 ERROR(ORCAP-36035): Multiple pin GND's which have different nets connected for J10: SCHEMATIC1,6.VIDEO_DEC (96.52, 175.26).#16 ERROR(ORCAP-36018): Aborting Netlisting... Please correct the above errors and retry.Exiting... "D:\Cadence\SPB_16.5\tools\capture\pstswp.exe" -pst -d"e:\work\yuleying\hj-am13-mb-0.0.0\sch\hj-am13-mb-v000\hj-am13-mb-v000.dsn" -n "e:\work\yuleying\hj-am13-mb-0.0.0\sch\hj-am13-mb-v000\allegro" -c"D:\Cadence\SPB_16.5\tools\capture\allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint"-hpath "HPathForCollision"INFO(ORCAP-32005): *** Done ***分析原因：首先确认了是非法字符，ORCAD包含的非法字符有：”/”、“<”、“>”、“＃”、“$”、“（”、“）”。

OrCAD Capture CIS导网表常见问题

OrCAD Capture CIS导网表常见问题汇总1、ERROR(ORCAP-36032): Duplicate Reference Designator C38: SCHEMATIC1, P02-POWER/URAT/FE LED (2.73, 7.79).问题：C38位号重复，更改重复的位号即可；2、ERROR(ORCAP-36055): Illegal character in \rtl8211f(d)(i)_utp_rgmii_v10\. 问题：器件封装描述有非法字符—小括号（）；解决方法（1）点开Design Cache找到错误提示里对应的器件路径，比如RTL8211可以发现，描述里含有小括号；（2）然后把该路径复制下来，新建一个LIBRARY1.OLB，把刚才复制的那个路径粘贴到新的LIBRARY1.OLB里去，器件封装名默认变为：RTL8112_22，点击保存；（3）回到Design Cache找到器件路径，把路径替换为新建LIBRARY1.OLB的路径，并下拉找到8211对应的封装名：RTL8112_22；（4）更改后路径变为如下，已无非法字符了；3、ERROR(ORCAP-36071): Illegal character "Dot(.)" found in "PCB Footprint" property for component instance T25: SCHEMATIC1, P04-Ethernet Port (7.72, 6.48) .问题：PCB Footprint描述含有非法字符-“.”，在PCB Footprint里把点去掉即可；4、ERROR(ORCAP-36041): Duplicate Pin Name "XTALP" found on Package XTAL , Y1 Pin Number 3: SCHEMATIC1, P08-RTL8812BRH (16.51, 13.40). Please renumber one of these.问题：有2个管脚封装名称相同，都是XTALP，点开封装，更改管脚名称即可；5、ERROR(ORCAP-36022): Pin number missing from Pin "1" of Package CAP NP , C101: SCHEMATIC1, P04-Ethernet Port (1.80, 6.10). All pins should be numbered.问题：电容C101，有管脚没有管脚编码，点开电容封装（Eidit Part）把每个管脚编号及写上名称即可；6、WARNING(ORCAP-36038): "No_connect" property on Pin "U1.98" ignored for U1: SCHEMATIC1, P02-POWER/URAT/FE LED (16.93, 11.04). Connecting pin to net "VFB2V5_1V8".问题：U1的98pin属性是No_connect，但是却有连线，需点开编辑属性，找到pin栏，把no-connect属性那个勾去掉即可；7、WARNING(ORCAP-36006): Part Name "SMA/UFLR_0_RF_CABLE_P3M5_SMA/UFLR" is renamed to "SMA/UFLR_0_RF_CABLE_P3M5_SMA/UF".问题：封装路径名字太长（导网表时默认是31字节），按照第2点的第2步，粘贴路径后再rename，把路径名称改短一点即可；8、WARNING(ORCAP-36006): Part Name "C_C0201_贴片电容_1NF" is renamed to "C_C0201__1NF".问题：part name里有中文字体，需去掉，如下图，把part的class值设置为空格即可；9、WARNING(ORCAP-36006):Part Name"SPDT/SKYWORKS/SKY85601-21_3_QFN16_P0M5_3M4X3M4__SKY85717-21/RTC5638H," is renamed to "SPDT/SKYWORKS/SKY85601-21_3_QFN16_P0M5_3M4X3M4__SK".问题：part的路径名太长，在Design Cache里找到对应器件part，复制到新建的LIBRARY1.OLB 里，并重新命名，再把part路径按照第2点第3步方法更新即可；10、ERROR(SPCODD-248): All physical pins are common in section 9 of physical part 'RTL8197F-DRQFN128_QFN128-1010-5-H9-E55__RTL8197FH'. Each section must have at least one non-common pin.问题：打开封装可知，芯片RTL8197FH的封装分为好多个部分。

caputer生成网表报错原因解析#(精选.)

（1）Warning "No_connect"#1 Warning [ALG0047] "No_connect" property on Pin "P1.8" ignored forP1: SCHEMATIC1, 13)URAT (7.90, 1.20). Connecting pin to net "N16811229".&H)K]-hwM$k3D3pd-T$W7heALG0047，这个警告基本可以忽略；造成这个问题的原因是，设计之初先对器件相关的管脚上加上'X'(也就是NC符号)，更新设计的过程又对管脚做了连接处理；但是后面的连接处理没有去掉管脚的NC 属性，不信的话把那个管脚上的net删掉看看。

RG9f解决办法很简单，对这些管脚再做一次NC（2）Warning Part Name#5 Warning [ALG0016] Part Name "CAP PN_C100UP-6.3V-SMT-S_100UF/6.3V" is renamed to "CAP PN_C100UP-6.3V-SMT-S_100UF/"这个警告不可避免，allegro对相关的属性名称进行合并，超过一定数量的字符就截掉；在命名规范的前提下就不考虑这个警告了。

无法根治这个#2 Warning [ALG0016] Part Name "?j#w?rm之类的错误在于你建立元件原理图的时候你的原件Value值太长了超过32个字符,从而使系统在进行命名规范的时候溢出,而出错,很简单的,只写关键元件名,比如 A2541P10_HDR2X5-100MIL_2X5 HEADER" is renamed to "A2541P10_HDR2X5-100MIL_2X5 HEAD错误只需要把2X5 HEADER更改为A2541P10,去除中间的空格即可.Allegro对一些字符[例如"空格","小数点"等等]很在意,可以参阅相关文档的描述.（3）Error Illegal character "Dot(.)" found in "PCB Footprint"#1 Error [ALG0081] Illegal character "Dot(.)" found in "PCB Footprint" property for component instance C255:PG16_AC97, PG16_AC97 (226.06, 132.08) .封装命名不能包含“.”（4）Error Illegal character "Forward Slash(/)" found in "PCB Footprint" property#1 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instanceC255: PG16_AC97, PG16_AC97 (226.06, 132.08) .#2 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance D3: PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp (93.98, 33.02) .#3 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instanceC245: PG16_AC97, PG16_AC97 (205.74, 35.56) .封装命名不能包含“/”（5）比较隐藏的排除法Loading... E:\FPGA\SCH\allegro/pstchip.dat#34 WARNING(SPCODD-34): Expected ';' character on line 5308. Check the name and value syntax for invalid characters in theprimitive definition before the line number.ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causingthis situation and package the design again.#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging.#187 Error [ALG0036] Unable to read logical netlist data.Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\motherboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"*** Done*******掌握排错方法，查找文件pstchip.dat，第on line 5308 看看错误，便可以解决（6）封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决*********************************************************** *********************** Netlisting the design*********************************************************** **********************Design Name:E:\FPGA\SCH\basicboard.dsnNetlist Directory:E:\FPGA\SCH\allegroConfiguration File:D:\Cadence\SPB_16.2\tools\capture\allegro.cfgSpawning... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"#1 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance MG2: Basic, PG06_Stepmotor (180.34, 83.82) .#2 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance ISO1: Basic, PG05_DC Motor (134.62, 40.64) .#3 Info: PCB Editor does not support Dots(.), Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).#4 Aborting Netlisting... Please correct the above errors and retry.Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"*** Done ***封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决（7）Warning#11 Warning [ALG0051] Pin "GND" is renamed to "GND#A6" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#12 Warning [ALG0051] Pin "GND" is renamed to "GND#A11" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#13 Warning [ALG0051] Pin "GND" is renamed to "GND#A1" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#14 Warning [ALG0051] Pin "GND" is renamed to "GND#W8" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).这条警告信息，在命名规范的前提下就不考虑这个警告了。

caputer生成网表报错原因解析

无法根治这个#2 Warning [ALG0016] Part Name "?j#w?rm之类的错误在于你建立元件原理图的时候你的原件Value值太长了超过32个字符,从而使系统在进行命名规范的时候溢出,而出错,很简单的,只写关键元件名,比如 A2541P10_HDR2X5-100MIL_2X5 HEADER" is renamed to "A2541P10_HDR2X5-100MIL_2X5 HEAD错误只需要把2X5 HEADER更改为A2541P10,去除中间的空格即可.Allegro对一些字符[例如"空格","小数点"等等]很在意,可以参阅相关文档的描述.（3）Error Illegal character "Dot(.)" found in "PCB Footprint"#1 Error [ALG0081] Illegal character "Dot(.)" found in "PCB Footprint" property for component instance C255:PG16_AC97, PG16_AC97 (226.06, 132.08) .封装命名不能包含“.”（4）Error Illegal character "Forward Slash(/)" found in "PCB Footprint" property#1 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instanceC255: PG16_AC97, PG16_AC97 (226.06, 132.08) .#2 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance D3: PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp (93.98, 33.02) .#3 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instanceC245: PG16_AC97, PG16_AC97 (205.74, 35.56) .封装命名不能包含“/”（5）比较隐藏的排除法Loading... E:\FPGA\SCH\allegro/pstchip.dat#34 WARNING(SPCODD-34): Expected ';' character on line 5308. Check the name and value syntax for invalid characters intheprimitive definition before the line number.ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the packaging operation did not complete. Check the pxl.log file for the errors causingthis situation and package the design again.#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging.#187 Error [ALG0036] Unable to read logical netlist data.Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\motherboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"*** Done*******掌握排错方法，查找文件pstchip.dat，第on line 5308 看看错误，便可以解决（6）封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决*********************************************************** *********************** Netlisting the design*********************************************************** **********************Design Name:E:\FPGA\SCH\basicboard.dsnNetlist Directory:E:\FPGA\SCH\allegroConfiguration File:D:\Cadence\SPB_16.2\tools\capture\allegro.cfgSpawning... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"#1 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance MG2: Basic, PG06_Stepmotor (180.34, 83.82) .#2 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance ISO1: Basic, PG05_DC Motor (134.62, 40.64) .#3 Info: PCB Editor does not support Dots(.), Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).#4 Aborting Netlisting... Please correct the above errors and retry.Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"*** Done ***封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决（7）Warning#11 Warning [ALG0051] Pin "GND" is renamed to "GND#A6" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#12 Warning [ALG0051] Pin "GND" is renamed to "GND#A11" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#13 Warning [ALG0051] Pin "GND" is renamed to "GND#A1" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#14 Warning [ALG0051] Pin "GND" is renamed to "GND#W8" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).这条警告信息，在命名规范的前提下就不考虑这个警告了。

利用Allegro画封装和布局时常见错误详解

利⽤Allegro画封装和布局时常见错误详解⼀：焊盘篇1. 问题⼀：⽤padstack editor制作完焊盘后，在pcb editor中找不到焊盘。

解决办法：在Pcb editor中选择set→user preference→paths→Library→分别在padpath和psmpath中加⼊焊盘的路径（选中所对应的上层⽂件夹即可）⼆：⽹表导⼊篇（Cadence中⽣成netlist失败的原因）1. 问题⼀：Unable to open c:\Cadence\PSD_14.2\tools\capture\allerro.cfg for reading.Please correct the above error(s) to proceed.错误原因：allegro.cfg⽂件找不到或allegro.cfg⽂件不能打开，这个问题的根源是，有可能每台电脑上安装Allegro的位置不⼀样，allegro.cfg⽂件找不到是理所当然的。

解决办法：点⽣成netlist，点setup，修改路径为capture\allegro.cfa所在路径，把allegro.cfg⽂件的位置选择你现在安装⽬录的⽂件位置。

（⽰例：D:\Cadence\SPB_16.5\tools\capture\allegro.cfg）2.问题⼆：#1 ERROR(ORCAP-36055):Illegal character in \hi-am13-mb-v.ooo(a10)#2 ERROR(ORCAP-36055):Illegal character in \hi-am13-mb-v.ooo(a10)\#3 ERROR(ORCAP-36055):Illegal character in \hi-am13-mb-v.ooo(a10)\…….错误原因：⾸先确认了是⾮法字符，ORCAD包含的⾮法字符有：”/”、”<”、”>”、”#”、”$”、”（”、”）”。

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c a p u t e r生成网表报错原因解析（1）Warning "No_connect"#1 Warning [ALG0047] "No_connect" property on Pin "P1.8" ignored forP1: SCHEMATIC1, 13)URAT (7.90, 1.20). Connecting pin to net "N16811229".&H)K]-hwM$k3D3pd-T$W7heALG0047，这个警告基本可以忽略；造成这个问题的原因是，设计之初先对器件相关的管脚上加上'X'(也就是NC符号)，更新设计的过程又对管脚做了连接处理；但是后面的连接处理没有去掉管脚的NC 属性，不信的话把那个管脚上的net删掉看看。

无法根治这个#2 Warning [ALG0016] Part Name "?j#w?rm之类的错误在于你建立元件原理图的时候你的原件Value值太长了超过32个字符,从而使系统在进行命名规范的时候溢出,而出错,很简单的,只写关键元件名,比如 A2541P10_HDR2X5-100MIL_2X5 HEADER" is renamed to "A2541P10_HDR2X5-100MIL_2X5 HEAD错误只需要把2X5 HEADER更改为A2541P10,去除中间的空格即可.Allegro对一些字符[例如"空格","小数点"等等]很在意,可以参阅相关文档的描述.（3）Error Illegal character "Dot(.)" found in "PCB Footprint"#1 Error [ALG0081] Illegal character "Dot(.)" found in "PCB Footprint" property for component instance C255:PG16_AC97, PG16_AC97 (226.06, 132.08) .封装命名不能包含“.”（4）Error Illegal character "Forward Slash(/)" found in "PCB Footprint" property#1 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instanceC255: PG16_AC97, PG16_AC97 (226.06, 132.08) .#2 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance D3: PG01_LED&Switch&7-Segment Disp, PG01_LED&Switch&7-Segment Disp (93.98, 33.02) .#3 Error [ALG0081] Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instanceC245: PG16_AC97, PG16_AC97 (205.74, 35.56) .封装命名不能包含“/”（5）比较隐藏的排除法Loading... E:\FPGA\SCH\allegro/pstchip.dat#34 WARNING(SPCODD-34): Expected ';' character on line 5308. Check the name and value syntax for invalid characters in theprimitive definition before the line number.ERROR(SPCODD-47): File ./allegro/pstchip.dat could not be loaded, and the packaging operation did notcomplete. Check the pxl.log file for the errors causingthis situation and package the design again.#53 ERROR(SPCODD-53): Packaging cannot be completed because packaging has encountered a null object ID. The design may not have been saved correctly. Save the schematic and rerun packaging.#187 Error [ALG0036] Unable to read logical netlist data.Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\motherboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"*** Done*******掌握排错方法，查找文件pstchip.dat，第on line 5308 看看错误，便可以解决（6）封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决*********************************************************** *********************** Netlisting the design*********************************************************** **********************Design Name:E:\FPGA\SCH\basicboard.dsnNetlist Directory:E:\FPGA\SCH\allegroConfiguration File:D:\Cadence\SPB_16.2\tools\capture\allegro.cfgSpawning... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"#1 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance MG2: Basic, PG06_Stepmotor (180.34, 83.82) .#2 Error [ALG0081] Illegal character "White space" found in "PCB Footprint" property for component instance ISO1: Basic, PG05_DC Motor (134.62, 40.64) .#3 Info: PCB Editor does not support Dots(.), Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).#4 Aborting Netlisting... Please correct the above errors and retry.Exiting... "D:\Cadence\SPB_16.2\tools\capture\pstswp.exe" -pst -d "E:\FPGA\SCH\basicboard.dsn" -n"E:\FPGA\SCH\allegro" -c"D:\Cadence\SPB_16.2\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"*** Done ***封装命名中不能包含“小数点”、“/”、“空格”，把空格换成下划线或删除，可以解决（7）Warning#11 Warning [ALG0051] Pin "GND" is renamed to "GND#A6" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#12 Warning [ALG0051] Pin "GND" is renamed to "GND#A11" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#13 Warning [ALG0051] Pin "GND" is renamed to "GND#A1" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).#14 Warning [ALG0051] Pin "GND" is renamed to "GND#W8" after substituting illegal characters in Package XC3S1400A-4FG676-C_0FF , U1A: SCHEMATIC1, PG01_FPGACONFIG (2.40,3.10).这条警告信息，在命名规范的前提下就不考虑这个警告了。