Common Interfaces but... (Graphical) Component Assembly versus Usage Persistence Compon
W9812G2GB-6I中文资料
1M × 4 BANKS × 32BITS SDRAM Table of Contents-1.GENERAL DESCRIPTION (3)2.FEATURES (3)3.AVAILABLE PART NUMBER (3)4.BALL CONFIGURATION (4)5.PIN DESCRIPTION (5)6.BLOCK DIAGRAM (6)7.FUNCTIONAL DESCRIPTION (7)7.1.Power Up and Initialization (7)7.2.Programming Mode Register (7)7.3.Bank Activate Command (7)7.4.Read and Write Access Modes (7)7.5.Burst Read Command (8)7.6.Burst Write Command (8)7.7.Read Interrupted by a Read (8)7.8.Read Interrupted by a Write (8)7.9.Write Interrupted by a Write (8)7.10.Write Interrupted by a Read (8)7.11.Burst Stop Command (9)7.12.Addressing Sequence of Sequential Mode (9)7.13.Addressing Sequence of Interleave Mode (9)7.14.Auto-precharge Command (10)7.15.Precharge Command (10)7.16.Self Refresh Command (10)7.17.Power Down Mode (11)7.18.No Operation Command (11)7.19.Deselect Command (11)7.20.Clock Suspend Mode (11)8.OPERATION MODE (12)9.ELECTRICAL CHARACTERISTICS (13)9.1.Absolute Maximum Ratings (13)9.2.Recommended DC Operating Conditions (13)9.3.Capacitance (13)9.4.DC Characteristics (14)9.5.AC Characteristics and Operating Condition (15)10.TIMING WAVEFORMS (17)mand Input Timing (17)10.2.Read Timing (18)10.3.Control Timing of Input/Output Data (19)10.4.Mode Register Set Cycle (20)11.OPERATING TIMING EXAMPLE (21)11.1.Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) (21)11.2.Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) (22)11.3.Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (23)11.4.Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) (24)11.5.Interleaved Bank Write (Burst Length = 8) (25)11.6.Interleaved Bank Write (Burst Length = 8, Auto-precharge) (26)11.7.Page Mode Read (Burst Length = 4, CAS Latency = 3) (27)11.8.Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) (28)11.9.Auto-precharge Read (Burst Length = 4, CAS Latency = 3) (29)11.10.Auto-precharge Write (Burst Length = 4) (30)11.11.Auto Refresh Cycle (31)11.12.Self Refresh Cycle (32)11.13.Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) (33)11.14.Power Down Mode (34)11.15.Auto-precharge Timing (Read Cycle) (35)11.16.Auto-precharge Timing (Write Cycle) (36)11.17.Timing Chart of Read to Write Cycle (37)11.18.Timing Chart of Write to Read Cycle (37)11.19.Timing Chart of Burst Stop Cycle (Burst Stop Command) (38)11.20.Timing Chart of Burst Stop Cycle (Precharge Command) (38)11.21.CKE/DQM Input Timing (Write Cycle) (39)11.22.CKE/DQM Input Timing (Read Cycle) (40)12.PACKAGE SPECIFICATION (41)12.1.TFBGA 90 Balls pitch=0.8mm (41)13.REVISION HISTORY (42)1. GENERAL DESCRIPTIONW9812G2GB is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1,048,576 words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology, W9812G2GB delivers a data bandwidth of up to 166MHz words per second (-6). For different application, W9812G2GB is sorted into two speed grades: -6/-6I and -75. The –6 is compliant to the 166MHz/CL3 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the 133MHz/CL3 specification.Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9812G2GB is ideal for main memory in high performance applications.2. FEATURES• 3.3V ± 0.3V Power Supply•Up to 166 MHz Clock Frequency• 1,048,576 Words × 4 banks × 32 bits organization• Self Refresh Mode•CAS Latency: 2 and 3•Burst Length: 1, 2, 4, 8 and full page•Burst Read, Single Writes Mode•Byte Data Controlled by DQM•Auto-precharge and Controlled Precharge•4K Refresh cycles / 64 mS• Interface: LVTTL•Packaged in TFBGA 90 Ball•W9812G2GB is using lead free materials with RoHS compliant3. AVAILABLE PART NUMBERPART NUMBER SPEEDMAXIMUM SELFREFRESH CURRENTOPERATINGTEMPERATUREW9812G2GB-6 166MHz/CL3 2mA 0°C ~ 70°C W9812G2GB-6I 166MHz/CL3 2mA -40°C ~ 85°C W9812G2GB-75 133MHZ/CL3 2mA 0°C ~ 70°C4. BALL CONFIGURATION5. PIN DESCRIPTION6. BLOCK DIAGRAM7. FUNCTIONAL DESCRIPTION7.1. Power Up and InitializationThe default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.During power up, all V DD and V DDQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power up voltage must not exceed V DD +0.3V on any of the input pins or V DD supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.7.2. Programming Mode RegisterAfter initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RA,S CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t RSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.7.3. Bank Activate CommandThe Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t RCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t RC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD). The maximum time that each bank can be held active is specified as t RAS (max).7.4. Read and Write Access ModesAfter a bank has been activated, a read or write cycle can be followed. This is accomplished by setting S RCD delay. WE pin voltage level RAS high and CA low at the clock rising edge after minimum of tdefines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation amongmany different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.7.5. Burst Read CommandThe Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.7.6. Burst Write CommandThe Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.7.7. Read Interrupted by a ReadA Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied.7.8. Read Interrupted by a WriteTo interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.7.9. Write Interrupted by a WriteA burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.7.10. Write Interrupted by a ReadA Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.7.11. Burst Stop CommandA Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop.7.12. Addressing Sequence of Sequential ModeA column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.Table 2 Address Sequence of Sequential Mode7.13. Addressing Sequence of Interleave ModeA column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.Table 3 Address Sequence of Interleave Mode7.14. Auto-precharge CommandIf A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency.A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (t RP) has been satisfied. Issue of Auto-precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as Write t WR. The bank undergoing auto-precharge can not be reactivated until t WR and t RP are satisfied. This is referred to as t DAL, Data-in to Active delay (t DAL = t WR + t RP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t RAS (min).7.15. Precharge CommandThe Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (t RP).7.16. Self Refresh CommandThe Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the t AC cycle time plus the Self Refresh exit time.If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. The period between the Auto Refresh command and the next command is specified by t RC.7.17. Power Down ModeThe Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t REF) of the device.The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on t CK. The input buffers need to be enabled with CKE held high for a period equal to t CKS (min) + t CK (min).7.18. No Operation CommandThe No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.7.19. Deselect CommandThe Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.7.20. Clock Suspend ModeDuring normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.8. OPERATION MODEFully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.Table 1 Truth Table (Note (1), (2))Notes:(1) v =valid x =Don’t care L =Low Level H =High Level(2) CKEn signal is input level when commands are provided.CKEn-1 signal is the input level one clock cycle before the command is issued.(3) These are state of bank designated by BS0, BS1 signals.(4) Device state is full page burst operation.(5) Power Down Mode can not be entered in the burst cycle.When this command asserts in the burst cycle, device state is clock suspend mode.9. ELECTRICAL CHARACTERISTICS9.1. Absolute Maximum RatingsRATINGUNIT PARAMETER SYMBOLInput/Output Voltage V IN, V OUT -0.3 ~ V DD +0.3 VPower Supply Voltage V DD, V DDQ-0.3 ~ 4.6 VOperating Temperature (-6/-75) T OPR0 ~ 70 °C°C85Operating Temperature (-6I) T OPR -40~°C150Storage Temperature T STG -55~Soldering Temperature (10s) T SOLDER 260 °CW Power Dissipation P D 1mA Short Circuit Output Current I OUT 50Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.9.2. Recommended DC Operating Conditions(Ta = 0 to 70°C for -6/-75, Ta= -40 to 85°C for -6I)UNIT PARAMETER SYMBOL MIN.MAX.TYP.Power Supply Voltage V DD 3.0 3.3 3.6 VPower Supply VoltageV DDQ 3.0 3.3 3.6 V(for I/O Buffer)V DD +0.3 VInput High Voltage V IH 2.0 -Input Low Voltage V IL -0.3 - 0.8 VNote: V IH(max) = V DD/ V DDQ+1.2V for pulse width < 5 nSV IL(min) = V SS/ V SSQ-1.2V for pulse width < 5 nS9.3. Capacitance(V DD= 3.3V, f = 1 MHz, Ta 25°C)Note: These parameters are periodically sampled and not 100% tested.9.4. DC Characteristics(VDD =3.3V± 0.3V, Ta = 0 to 70°C for-6/-75, Ta= -40 to 85°C for -6I)NOTESUNIT PARAMETER SYMBOL MIN.MAX.Input Leakage CurrentI I(L) -5 5 µA (0V ≤V IN≤ V DD, all other pins not under test = 0V)Output Leakage CurrentI O(L) -5 5 µA (Output disable , 0V ≤ V OUT≤ V DDQ)LVTTL Output ″H″ Level VoltageV OH 2.4 - V(I OUT = -2 mA )LVTTL Output ″L″ Level VoltageV OL - 0.4 V(I OUT = 2 mA )9.5. AC Characteristics and Operating Condition(VDD =3.3V ± 0.3V, Ta = 0 to 70°C for -6/-75, Ta= -40 to 85°C for -6I, Notes: 5, 6, 7, 8, 9, 10)-6/-6I -75PARAMETER SYM.MIN. MAX. MIN. MAX.UNIT NOTESRef/Active to Ref/Active Command Period t RC 60 65 Active to precharge Command Period t RAS 42 10000045 100000 nSActive to Read/Write Command Delay Timet RCD 18 20 Read/Write(a) to Read/Write(b) Command Periodt CCD 1 1 t CKPrecharge to Active Command Period t RP 18 20 Active(a) to Active(b) Command Period t RRD 12 15 nS CL* = 2 22 t CKWrite Recovery Time CL* = 3 t WR 22CL* = 2 101000101000CLK Cycle TimeCL* = 3t CK6 1000 7.5 1000CLK High Level widtht CH 2 2.5 9 CLK Low Level widtht CL 2 2.59CL* = 2 6 6 Access Time from CLKCL* = 3t AC 5 5.4 10 Output Data Hold Timet OH 3 3 10 Output Data High Impedance Time t HZ 3 6 3 7.5 8 Output Data Low Impedance Time t LZ 0 0 10 Power Down Mode Entry Time t SB 0 6 0 7.5Transition Time of CLK (Rise and Fall) t T 0.1 1 0.1 1 7 Data-in Set-up Time t DS 1.5 1.5 9 Data-in Hold Time t DH 1.0 1.0 9 Address Set-up Time t AS 1.5 1.5 9 Address Hold Time t AH 1.0 1.0 9 CKE Set-up Time t CKS 1.5 1.5 9 CKE Hold Time t CKH 1.0 1.0 9 Command Set-up Time t CMS 1.5 1.5 9 Command Hold Time t CMH 1.0 1.0nS9Refresh Timet REF 64 64 mS Mode register Set Cycle Time t RSC 12 15 nS Exit self refresh to ACTIVE commandt XSR72 75 nS*CL = CAS LatencyNotes:1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.2. All voltages are referenced to V SS3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t CK and t RC .4. These parameters depend on the output loading conditions. Specified values are obtained with output open.5. Power up sequence is further described in the “Functional Description” section.6. AC Testing ConditionsPARAMETER CONDITIONSOutput Reference Level1.4VOutput LoadSee diagram belowInput Signal Levels (V IH /V IL ) 2.4V/0.4VTransition Time (t T : tr/tf) of Input Signal 1/1 nS Input Reference Level 1.4V7. Transition times are measured between V IH and V IL .8. t HZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.9. Assumed input transition Time (t T ) = 1nS.If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter(The t T maximum can’t be more than 10nS for low frequency application.)10. If clock rising time (t T ) is longer than 1nS, (t T /2-0.5)nS should be added to the parameter.10. TIMING WAVEFORMS 10.1. Command Input Timing10.2. Read Timing10.3. Control Timing of Input/Output Data10.4. Mode Register Set Cycle11. OPERATING TIMING EXAMPLE11.1. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)11.2. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)11.3. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)11.4. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)11.5. Interleaved Bank Write (Burst Length = 8)11.6. Interleaved Bank Write (Burst Length = 8, Auto-precharge)11.7. Page Mode Read (Burst Length = 4, CAS Latency = 3)11.8. Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)11.9. Auto-precharge Read (Burst Length = 4, CAS Latency = 3)11.10. Auto-precharge Write (Burst Length = 4)11.11. Auto Refresh Cycle11.12. Self Refresh Cycle11.13. Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)11.14. Power Down Mode11.15. Auto-precharge Timing (Read Cycle)11.17. Timing Chart of Read to Write Cycle11.18. Timing Chart of Write to Read Cycle11.19. Timing Chart of Burst Stop Cycle (Burst Stop Command)11.20. Timing Chart of Burst Stop Cycle (Precharge Command)11.21. CKE/DQM Input Timing (Write Cycle)11.22. CKE/DQM Input Timing (Read Cycle)12. PACKAGE SPECIFICATION12.1. TFBGA 90 Balls pitch=0.8mmPublication Release Date:Aug. 13,2007- 41 - Revision A07Publication Release Date: Aug. 13,2007- 42 - Revision A0713. REVISION HISTORYVERSION DATEPAGEDESCRIPTIONA01 Mar. 24, 2006 All Create new datasheet A02 Jul. 05, 2006 8 Burst Stop commandA03 Sep. 08, 2006 10 Exit Auto refresh to next command is specified by t RC A04 Sep. 27, 200615,16Modify Characteristics Notes 9 and add Notes 10 (t T ) A05 Apr. 12, 2007 15,32,34,41Add t XSR timing specification and package dimension ball openingA06 Jun. 21, 2007 3,13,14,15Add -6I gradeA07 Aug. 13, 200716Revise transient time t T AC test condition and calculate formula for compensation consideration in Notes 6, 9 of AC Characteristics and Operating ConditionImportant NoticeWinbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.。
信息检索关键词部分
信息检索关键词部分Key word第1章信息检索（Information Retrieval, IR）数据检索（data retrieval）相关性（relevance）推送（Push）超空间（hyperspace）拉出（pulling）⽂献逻辑表⽰（视图）（logical view of the document）检索任务（retrieval task 检索（retrieval ）过滤（filtering）全⽂本（full text）词⼲提取（stemming）⽂本操作（text operation）标引词（indexing term）信息检索策略（retrieval strategy）光学字符识别（Optical Character Recognition, OCR）跨语⾔（cross-language）倒排⽂档（inverted file）检出⽂献（retrieved document）相关度（likelihood）信息检索的⼈机交互界⾯（human-computer interaction, HCI）检索模型与评价（Retrieval Model & Evaluation）⽂本图像（textual images）界⾯与可视化（Interface & Visualization）书⽬系统（bibliographic system）多媒体建模与检索（Multimedia Modeling & Searching）数字图书馆（Digital Library）检索评价（retrieval evaluation）标准通⽤标记语⾔（Standard Generalized Markup Language, SGML）标引和检索（indexing and searching）导航（Navigation）并⾏和分布式信息检索（parallel and distribution IR）模型与查询语⾔（model and query language）导航（Navigation）有效标引与检索（efficient indexing and searching）第2章特别检索（ad hoc retrieval）过滤（filtering）集合论（set theoretic）代数（algebraic）概率（probabilistic 路由选择（routing）⽤户需求档（user profile）阙值（threshold）权值（weight）语词加权（term-weighting）相似度（similarity）相异度（dissimilarity）域建模（domain modeling）叙词表（thesaurus）扁平（flat）⼴义向量空间模型（generalized vector space model）神经元（neuron）潜语义标引模型（latent semantic indexing model）邻近结点（proximal node）贝叶斯信任度⽹络（Bayesian belief network）结构导向（structure guided）结构化⽂本检索（structured text retrieval, STR）推理⽹络（inference network）扩展布尔模型（extended Boolean model）⾮重叠链表（non-overlapping list）第3章检索性能评价（retrieval performance evaluation）会话（interactive session）查全率(R, Recall Ratio) 信息性（Informativeness）查准率(P, Precision Ratio) ⾯向⽤户（user-oriented）漏检率(O, Omission Ratio) 新颖率（novelty ratio）误检率(M, Miss Ratio) ⽤户负担（user effort）相对查全率（relative recall）覆盖率（coverage ratio）参考测试集（reference test collection）优劣程度（goodness）查全率负担（recall effort）主观性（subjectiveness）信息性测度（informativeness measure）第4章检索单元（retrieval unit）字母表（alphabet）分隔符（separator）复合性（compositional）模糊布尔（fuzzy Boolean）模式（pattern）SQL(Structured Query Language, 结构化查询语⾔) 布尔查询（Boolean query）参照（reference）半结合（semijoin）标签（tag）有序包含（ordered inclusion）⽆序包含（unordered inclusion）CCL(Common Command Language, 通⽤命令语⾔) 树包含（tree inclusion）布尔运算符（Boolean operator） searching allowing errors容错查询Structured Full-text relevance feedback 相关反馈Query Language (SFQL) （结构化全⽂查询语⾔） extended patterns扩展模式CD-RDx Compact Disk Read only Data exchange (CD-RDx)（只读磁盘数据交换）WAIS (⼴域信息服务系统Wide Area Information Service)visual query languages. 查询语⾔的可视化查询语法树（query syntax tree）第5章query reformulation 查询重构 query expansion 查询扩展 term reweighting 语词重新加权相似性叙词表（similarity thesaurus）User Relevance Feedback⽤户相关反馈 the graphical interfaces 图形化界⾯簇（cluster）检索同义词（searchonym） local context analysis局部上下⽂分析第6章⽂献（document）样式（style）元数据（metadata）Descriptive Metadata 描述性元数据 Semantic Metadata 语义元数据intellectual property rights 知识产权 content rating 内容等级digital signatures数字签名 privacy levels 权限electronic commerce电⼦商务都柏林核⼼元数据集（Dublin Core Metadata Element Set）通⽤标记语⾔（SGML，standard general markup language）机读⽬录记录（Machine Readable Cataloging Record, MARC）资源描述框架(Resource Document Framework, RDF) XML(eXtensible Markup Language, 可扩展标记语⾔) HTML（HyperText Markup Language, 超⽂本标记语⾔）Tagged Image File Format (TIFF标签图像⽂件格式)Joint Photographic Experts Group (JPEG) Portable Network Graphics (PNG新型位图图像格式)第7章分隔符（separator）连字符（hyphen）排除表（list of stopwords）词⼲提取（stemming）波特（porter）词库（treasury of words）受控词汇表（controlled vocabulary）索引单元（indexing component）⽂本压缩text compression 压缩算法compression algorithm注释（explanation）统计⽅法（statistical method）赫夫曼（Huffman）压缩⽐（compression ratio）数据加密Encryption 半静态的（semi-static）词汇分析lexical analysis 排除停⽤词elimination of stopwords第8章半静态（semi-static）191 词汇表（vocabulary）192事件表（occurrence）192 inverted files倒排⽂档suffix arrays后缀数组 signature files签名档块寻址（block addressing）193 索引点（index point）199起始位置（beginning）199 Vocabulary search词汇表检索Retrieval of occurrences 事件表检索 Manipulation of occurrences事件表操作散列变换（hashing）205 误检（false drop）205查询语法树（query syntax tree）207 布鲁特-福斯算法简称BF（Brute-Force）故障（failure）210 移位-或（shift-or）位并⾏处理（bit-parallelism）212顺序检索（sequential search）220 原位（in-place）227第9章并⾏计算（parallel computing） SISD （单指令流单数据流）SIMD （单指令流多数据流） MISD （多指令流单数据流）MIMD （多指令流多数据流）分布计算（distributed computing）颗粒度（granularity）231 多任务（multitasking）I/O（input/output）233 标引器（indexer）映射（map）233 命中列表（hit-list）全局语词统计值（global term statistics）线程（thread）算术逻辑单元（arithmetic logic unit, ALU 中介器（broker）虚拟处理器（virtual processor）240分布式信息检索(distributed information retrieval)249⽂献收集器（gatherer）主中介器（central broker）254第10章信息可视化（information visualization）图标（icon）260颜⾊凸出显⽰（color highlighting）焦点+背景（focus-plus-context）画笔和链接（brushing and linking）魔术透镜（magic lenses）移动镜头和调焦（panning and zooming）弹性窗⼝（elastic window）概述及细节信息（overview plus details）⾼亮⾊显⽰（highlight）信息存取任务（information access tasks）⽂献替代（document surrogate）常见问题(FAQ, Frequently Asked Question) 群体性推荐（social recommendation）上下⽂关键词（keyword-in-context, KWIC）伪相关反馈（pseudo-relevance feedback）重叠式窗⼝（overlapping window）⼯作集（working set）第11/12章多媒体信息检索（Multimedia Information Retrieval, MIR）超类（superclass）半结构化数据（semi-structured data）数据⽚（data blade）可扩充型系统（extensible type system）相交（intersect）动态服务器（dynamic server）叠加（overlaps）档案库服务器（archive server）聚集（center）逻辑结构（logical structure）词包含（contain word）例⼦中的查询（query by example）路径名（path-name）通过图像内容查询（Query by Image Content, QBIC）图像标题（image header）主要成分分析（Principal Component Analysis, PCA）精确匹配（exact match）潜语义标引（Latent Semantic Indexing, LSI）基于内容（content-based）范围查寻（Range Query）第13章exponential growth指数增长 Distributed data 数据的分布性volatile data 不稳定数据 redundant data 冗余数据Heterogeneous data异构数据分界点（cut point）373Centralized Architecture集中式结构收集器-标引器（crawler-indexer）373 Wanderers 漫步者 Walkers 步⾏者 Knowbots 知识机器⼈Distributed Architecture分布式结构 gatherers 收集器brokers 中介器 the query interface 查询界⾯the answer interface响应界⾯ PageRank ⽹页级别Crawling the Web漫游Web breadth-first ⼴度优先depth-first fashion 深度优先 Indices（index pl.）索引Web Directories ⽹络⽬录 Metasearchers元搜索引擎Teaching the User⽤户培训颗粒度（granularity）384超⽂本推导主题检索（Hypertext Included Topic Search, HITS）380 Specific queries专指性查询 Broad queries 泛指性查询Vague queries模糊查询 Searching using Hyperlinks使⽤超链接搜索Web Query Languages查询语⾔ Dynamic Search 动态搜索Software Agents 软件代理鱼式搜索（fish search）鲨鱼搜索（shark search）拉出/推送（pull/push）393门户（portal）395 Duplicated data 重复数据第14章联机公共检索⽬录（online public access catalog, OPAC）397化学⽂摘（Chemical Abstract, CA）399 ⽣物学⽂摘（Biological Abstract, BA）⼯程索引（Engineering Index,EI）国会图书馆分类法（Library of Congress Classification）408杜威⼗进分类法（Dewey Decimal Classification）408联机计算机图书馆中⼼（Online Computer Library Center, OCLC）409机读⽬录记录（Machine Readable Cataloging Record, MARC）409第15章NSF (National Science Foundation, 美国国家科学基⾦会)NSNA（National Aeronautics and Space Administration，美国航空航天局）数字图书馆创新项⽬（Digital Libraries Initiative, DLI）4155S（stream,信息流structure,结构space, 空间scenario, 场景society社会）416基于数字化对象标识符（Digital Object Identifier, DOI）420都柏林核⼼（Dublin Core, DC）430 数字图书馆（Digital Library, DL）资源描述框架(Resource Document Framework, RDF)431text encoding initiative (TEI) （⽂本编码创新项⽬）431v。
历年网络管理员及答案
网络管理员一、单项选择题（每小题2 分，共 100分）1、在一个动态分配IP地址的主机上，如果开机后没有得到DHCP服务器的响应，则该主机在（）中寻找一个没有冲突的IP地址。
A、169.254.0.0/16B、224.0.0.0/24C、202.117.0.0/16D、192.168.1.0/24【答案】A【解析】自动专用IP寻址（Automatic Private IP Addressing，APIPA），是一个DHCP故障转移机制。
当DHCP服务器出故障时， APIPA在169.254.0.1到169.254.255.254的私有空间内分配地址，所有设备使用默认的网络掩码255.255.0.0。
2、在文件菜单中打印对话框的“页面范围”下的“当前页”项是指（13）。
A、最后打开的页B、最早打开的页C、当前窗口显示的页D、插入光标所在的页【答案】D【解析】在“文件”菜单中“打印对话框”中的“页面范围”下的“当前页”项是指插入光标所在的页。
如果只打印一页的话，那么就打印出这一页。
3、无线局域网新标准IEEE802.11n提供的最高数据速率可达到（）。
A、11Mb/sB、54Mb/sC、100Mb/sD、300Mb/s【答案】D4、脚本语言程序开发不采用“编写，编译一链接．运行”模式，（）不属于脚本语言。
A、DelphiB、PhpC、PythonD、Ruby【答案】A【解析】试题分析：脚本语言的特点是语法简单，一般以文本形式保存，并且不需要编译成目标程序，在调用的时候直接解释。
常见的有JavaScript、VBScript、Perl、PHP、Python、Ruby。
5、使用常用文字编辑工具编辑正文时，在“打印预览”方式下，单击“ （2）”按钮可返回编辑文件；A、打印预览B、放大镜C、关闭D、全屏显示【答案】C【解析】在“打印预览”方式下，单击“关闭”按钮即可返回编辑状态。
“打印预览”、“放大境”和“全屏显示”均为在预览状况下的操作。
latex中graphical abstract 命令 -回复
latex中graphical abstract 命令-回复引言：在科学研究领域，图形摘要（graphical abstract）广泛应用于科学论文中，用于简明扼要地展示论文的主题和重要结论。
本文将介绍在LaTeX 中创建图形摘要的命令，并详细解释每一步的操作。
第一步：安装必要的宏包在LaTeX 中创建图形摘要需要使用一些特定的宏包。
首先，确保已安装`graphicx` 宏包，它提供了插入图片的功能。
使用以下命令检查该宏包是否已安装：latex\usepackage{graphicx}如果提示未找到该宏包，可以通过在LaTeX 发行版的包管理器中搜索并安装该宏包。
第二步：创建图形摘要环境要在LaTeX 中创建图形摘要，需要定义一个新的环境。
可以使用以下命令在文档的导言区定义一个名为`graphicalabstract` 的环境：latex\newenvironment{graphicalabstract}{\par\smallskip\noindent\textbf{Graphical Abstract:}\par\noindent} {\par\smallskip}这个命令定义了一个新的环境`graphicalabstract`，在摘要之前和之后增加了适当的空白行，并以粗体字形式显示“Graphical Abstract:”字样。
第三步：插入图形摘要在定义了图形摘要环境后，可以在文档的适当位置插入图形摘要。
以下是一个示例，展示如何插入一个图片作为图形摘要：latex\begin{graphicalabstract}\includegraphics[width=\textwidth]{graphical_abstract.jpg}\end{graphicalabstract}在这个示例中，使用`includegraphics` 命令插入了名为`graphical_abstract.jpg` 的图片。
《网络设备配置与调试》教学计划
《网络设备配置与调试》教学计划英文回答：The teaching plan for "Network Device Configuration and Debugging" is designed to provide students with comprehensive knowledge and practical skills in configuring and troubleshooting network devices. The course will cover various topics, including network device types, network protocols, device configuration, and network troubleshooting techniques.In the first part of the course, we will introduce different types of network devices, such as routers, switches, and firewalls. We will discuss their functionalities, features, and how they work together to form a network infrastructure. This will help students understand the role of each device and its significance in network communication.Next, we will delve into network protocols, includingTCP/IP, DHCP, DNS, and SNMP. Students will learn how these protocols enable communication between devices andfacilitate the exchange of data over the network. We will also cover topics like IP addressing, subnetting, and VLANs, which are essential for configuring network devices.Moving on, the course will focus on device configuration. Students will learn how to access and configure network devices using command-line interfaces (CLI) and graphical user interfaces (GUI). We will explore popular device operating systems, such as Cisco IOS and Junos, and teach students how to configure basic device settings, including interfaces, routing protocols, and security features.The final part of the course will cover network troubleshooting techniques. Students will learn how to identify and resolve common network issues, such as connectivity problems, performance degradation, andsecurity breaches. We will discuss troubleshooting methodologies, tools, and best practices to help students develop critical thinking and problem-solving skills in anetwork environment.中文回答：《网络设备配置与调试》教学计划旨在为学生提供全面的网络设备配置和故障排除知识与实践技能。
Chapter10_Graphical_User_Interface
If you entered ‘abc’ into the Edit Text, then the command above will make K = ‘abc’
Graphical User Interface(10/60)
The initial layout area is usually resizable by clicking and dragging the handles on the corners of the templanterface(4/60)
Listbox
Identical to the Pop-up menu, except that the options are already visible without being clicked on. (To see options in Pop-up menu, need to click on it first).
Components -Graphical Components: pushbuttons, edit boxes, sliders, labels, menus, … Static Components: frames, text strings,…
Callbacks-The functions which perform the required action when a component is pushed
‘value’ will indicate the index of the choice made. Example: If the 2nd choice is made, then ‘value’=2.
interface 用法
interface 用法中括号在英语中通常被称为“square brackets”（方括号），而“interface”则是指计算机科学中的接口。
本文将详细介绍interface用法，包括其在不同领域的应用、基本语法和常见用途等方面的内容。
第一部分：介绍interface的基本概念和定义（300-500字）在计算机科学领域，interface（接口）是一种在不同软件模块之间进行通信的规范或约定。
它定义了模块之间传递数据和交互的规则，以确保程序的整体功能能够顺利运行。
在软件开发中，interface被广泛应用于不同编程语言和平台，如Java、C#、C++等。
第二部分：interface在编程语言中的用法（600-900字）1. Java中的interface用法在Java编程语言中，interface是一个纯粹的抽象类，只定义方法的名称、参数列表和返回类型，并不提供具体的实现。
其他类通过实现（implement）该interface可以达到约定的数据交换和交互目的。
通过使用interface，可以实现多态性，提高代码的可扩展性和灵活性。
2. C#中的interface用法在C#中，interface与Java类似，用于定义一组行为（behaviors）。
类可以通过实现（implement）接口来表达自己拥有某些特定的行为。
与Java不同的是，C#中的接口允许在接口中定义属性和事件。
3. C++中的interface用法在C++中，interface概念由抽象类来表示。
抽象类中只包含纯虚函数（pure virtual functions），这些函数没有具体的实现，要求派生类必须实现。
通过继承抽象类，实现了接口的效果。
第三部分：interface在不同领域的应用（600-900字）1. 软件开发中的interface在软件开发中，interface非常重要。
它允许多个开发者协同工作，各自实现不同的模块，并通过interface进行数据的传递和交互。
关于接口interface一些笔记
关于接口interface一些笔记接口技术主要用来描述类具有什么功能，而并不给出每个功能的具体实现。
一个类可以实现（implement）一个或多个接口，并在需要接口的地方，随时使用实现了相应接口的对象。
接口不是类，而是一组对类的需求描述，这些类要遵从接口描述的统一格式进行定义。
如Comparable接口public interface Comparable<T>{int compareT o(T other);}例如，在实现Comparable<Employee>接口的类型中，必须提供以下方法：int compareT o(Employee other)也可以使用没有类型参数的Comparable类型，但必须手工地将compareT o方法的参数转换成所希望的类型。
接口中的所有方法自动地属于public，因此在接口中声明方法时，不必提供关键字public。
但是在实现接口时，必须把方法声明为public。
在接口中还可以定义常量，接口中的域被自动地设为public static final。
然而，接口绝不能含有实例域，也不能在接口中实现方法，提供实例域和方法实现的任务应该由实现接口的那个类来完成。
为了让类实现一个接口，通常需要下面两个步骤：1.将类声明为实现给定的接口，使用关键字implements；如：class Employee implements Comparable2.对接口中的所有方法进行定义。
接口的特性接口不是类，不能使用new运算符实例化一个接口。
尽管不能构造接口对象，却能声明接口变量，接口变量必须引用实现了接口的类对象。
Comparable x;x=new Employee(…);与使用instanceof检查一个对象是否属于某个特定类一样，也可以用instanceof检查一个对象是否属于某个特定的接口。
接口也可以像类一样建立继承关系。
尽管每个类只能拥有一个超类，但却可以实现多个接口，使用逗号将实现的各个接口分隔开。
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Examples of JavaBeans
USC - Center for Software Engineering
• GUI Items (e.g. Buttons, Listboxes) • (proprietary) Algorithms (e.g. Sorting) • (proprietary) Applications (e.g. DBs) => Service provider => Reusable components => Domain components
USC
CSE
USC - Center for Software Engineering
Java Beans
the only component architecture for Java?
Based in parts on “Java Beans API” from SUN
Alexander Egyed
• Beans support two mechanisms:
– use Java Serialization Mechanism which provides an automatic way of storing and restoring the internal state of Java objects – use Java Externalization Mechanism (extension of above) which gives a class complete control over the writing of its state
USC - Center for Software Engineering
Alexander Egyed, 4/15/99, 4
2
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CSE
JDK 1.1 (slide from Eric Chu, Sun)
USC - Center for Software Engineering
Alexander Egyed, 4/15/99, 5
Alexander Egyed, 4/15/99, 11
USC
CSE
Characteristics of JavaBeans?
USC - Center for Software Engineering
• Introspection: Ability of seeing inside a bean and analyzing how it works • Customization: Ability of manipulating the appearance or behavior of a bean while using the application • Event-Handling: Ability for beans to communicate with themselves and with their outside world • Properties: Both for customization and programmatic use • Persistence: Capturing the customized state of a bean for later (re) use • Security: just like regular Java security (applet vs. application)
USC - Center for Software Engineering
• • • • •
also • ease of use (design/runtime) • simple interface/complex behavior
Alexander Egyed, 4/15/99, 8
4
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Alexander Egyed, 4/15/99, 6
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What is JavaBeans?
USC - Center for Software Engineering
A Java Bean is a reusable software component that can be manipulated visually in a builder tool. • Beans frequently have strong visual aspects • Primarily targeted at builder tools: Web page builders, visual application builders, GUI layout builders, server application builders • May also be used ‘manually’ by programmers • Beans have capabilities for design time (e.g. customization features) and run time (e.g. actual functionality) - to separate them, beans support separate deign and run-time interfaces => download on demand)
• Besides properties (run-time state), beans also need to store customized information (e.g. how to deal with pointers to other beans).
Alexander Egyed, 4/15/99, 13
Class Libraries versus Beans • Not all modules should turn into beans • Beans are good for components that can be visually manipulated or customized • Class libraries are for everything else
CS612
April, 1999
Alexander Egyed, 4/15/99, 1
USC
CSE
Outline
USC - Center for Software Engineering
• • • • •
Java JavaBeans and their Characteristics JavaBeans Builder Tool Beans and Applications RMI, ActiveX, and CORBA
Alexander Egyed, 4/15/99, 9
USC
CSE
Other JavaBeans Issues
USC - Center for Software Engineering
Granularity • composite components as building blocks for (customizable) applications (e.g. button as component) • compound components (documents) as applications (e.g. spreadsheet into web page) • most components small to medium size Portability • provides implementation independent API • may still be implemented into platform specific containers Uniform API
USC
CSE
Java
USC - Center for Software Engineering
Java
• • • • Object-Oriented Portable Network Aware Common Interfaces
but ...
• (Graphical) Component Assembly versus Usage • Persistence • Component Interaction (e.g. two applets/applications)
Alexander Egyed, 4/15/99, 7
USC
CSE
Why JavaBeans?
software component model component architecture of choice for Java platform-neutral architecture developing or assembling network-aware solutions heterogeneous hardware and operating system (independent software vendors ISV)
Alexander Egyed, 4/15/99, 10
5
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CSE
JavaBeans
USC - Center for Software Engineering
Created by Sun; supported by Partners?
• Apple, Borland, IBM, Netscape, Oracle, Symantec, Sybase, and others
USC
CSE
Events
USC - Center for Software Engineering
• Are the core feature of Java Beans architectures • They allow components to be plugged together in application builders • Some components act as sources and others as targets (listeners) for events • Usually, events propagate state changes from the source object to all its listeners • Examples for events are mouse actions and widget updates • Listener components need to register to receive events • Event notifications are propagated by the event source via method invocation