CL31_Operator_Training
华为虚拟化及云操作系统FusionSphere 3.1售前专家培训
创新的分布式存储虚拟化
Oracle RAC测试对比: 华为 VS. Exadata
Server
VM
VM
volume1
Client
Server
VM
VM
volume2
Client
Server
VM
VM
volume3
Client
FusionStorage
华为公司4T真实财务数据查询测试
6
华为公司云计算整体战略视图
Cloud DataCenter
OA
Enterprise App
Telco App
Internet
Linux /Windows Server
FusionSphere
Compute
Storage Network & Security
FusionCube FusionAccess
3DMark06 分数
22413
22277
原生主机
GPU直通虚拟机 13
虚拟化将图形命令调度到vGPU上处理
华为 GPU虚拟化 VMware vSphere 5.0
简单模型 ProE
复杂模型
CS1.5 （游戏）
SphereWorld (3D动画)
★★★★★ ★★★★☆ ★★☆☆☆ ★★★★☆
★★☆☆☆ ★☆☆☆☆ ☆☆☆☆☆ ☆☆☆☆☆
5
大 价 值
信息更安全 (Information/IPR protection）
运营成本通过实现应用程序资源配置和IT运营 的自劢化，可将运营成本减少70%或更多，幵 让一名管理员同时管理数百台服务器，而丌是 只能管理几十台服务器。
快速应用部署(Quick deployment of applications)，可在几分钟内而丌是2周内完 成应用部署；系统能力劢态扩展(Dynamic Scalability/Elasticity)，快速精确匹配丌断变 化的业务需求。
Ultimate3000型高效液相色谱仪自主操作培训教材
Ultimate 3000型高效液相色谱仪自主操作培训教材福州大学测试中心2018年9月第一部分Ultimate 3000型高效液相色谱原理和仪器配置一、液相色谱原理简介1、色谱法起源色谱法最早是由俄国植物学家茨维特（Tswett）在1906 年研究用碳酸钙分离植物色素时发现的，色谱法(Chromatography)因之得名。
后来在此基础上发展出纸色谱法、薄层色谱法、气相色谱法、液相色谱法。
2、液相色谱法的分离原理溶于流动相(mobile phase)中的各组分经过固定相(stationary phase)时，由于与固定相发生作用（吸附、分配、离子交换、排阻、亲和）的大小、强弱不同，在固定相中滞留时间不同，从而先后从固定相中流出。
又称为色层法、层析法。
英文为High Performance Liquid Chromatography，简称为HPLC。
3、HPLC分离模式包括反相模式 (RP-LC)；正相模式 (NP-LC)；离子对色谱 (IPC)；离子交换色谱 (IEC)；体积排阻色谱 (GPC/GFC)；亲和色谱（AC）等。
其中，反相和正相模式又属于液液分配色谱。
•流动相的极性小于固定液的极性（正相 normal phase），反之，流动相的极性大于固定液的极性（反相 reverse phase）。
正相与反相的出峰顺序相反；化学键合固定相：（将各种不同基团通过化学反应键合到硅胶（担体）表面的游离羟基上。
C-18柱（常用反相柱）。
4、HPLC与经典液相色谱方法以及气相色谱（GC）方法的比较4.1 HPLC与经典液相色谱方法比较高速：HPLC采用高压输液设备，流速大增加，分析速度极快，只需数分钟；而经典方法靠重力加料，完成一次分析需时数小时。
高效：填充物颗粒极细且规则，固定相涂渍均匀、传质阻力小，因而柱效很高。
可以在数分钟内完成数百种物质的分离。
高灵敏度：检测器灵敏度极高：UV——10-9g, 荧光检测器——10-11g。
日本横河DCS CS3000培训教材
日本横河DCS CS3000培训教材目录一.横河系统项目的一般创建步骤二.PROJECT的创建三.COMMON ITEMS通用项目的定义四．FCS组态五．HIS组态日本横河DCS CS3000培训教材一．横河系统项目的一般创建步骤依照相关的自控图纸和工艺说明，进行DCS的软硬件选型、相关系统软硬件设计、软件模拟测试、软硬件上电测试、与现场仪表联动调试。
最终提交用户一个硬件安全可靠、软件健壮界面友好操作方便的工艺过程监控平台。
第一步：由自控图纸和工艺说明以及DCS规格需求书，确定系统硬件配置（包括控制器、I/O、通讯、操作站、服务器、以及其它附件），绘制系统配置图、机柜布置图、各种接线图。
第二步：利用SYSTEM VIEW 集成的工具进行硬件组态，包括控制器、I/O节点、I/O卡件、I/O通道、操作站。
第三步：利用SYSTEM VIEW集成的工具进行软件组态，包括回路控制组态、联锁逻辑组态、顺序控制组态、批量控制组态以及操作站各种人机界面的组态。
第四步：利用SYSTEM VIEW集成的虚拟测试功能，对控制器以及操作站组态进行软件功能测试。
通过此项测试可以解决其它系统只有在连接实际硬件时才能发现的问题，为安装调试做好准备。
第五步：系统安装调试，经考核运行后，提交用户。
下面是横河的工程工作流程图二．PROJECT的创建（详细内容参见横河文档IM 33S01B30-01E）1．PROJECT的类型（1）DEFAULT PROJECT当SYSTEM VIEW第一次启动创建的项目，为缺省项目,能够对控制器进行下载。
（2）CURRENT PROJECT一旦DEFAULT PROJECT项目中的一个FCS下载成功时，该项目属性自动变为CURRENT PROJECT,从而能够在线的对项目进行修改。
(3)USER-DEFINED PROJECT除以上两个类型PROJECT以外，创建的项目。
此类型的项目不能对控制器进行下载，只有通过改变PROJECT属性类型为DEFAULT 时，才能下载。
Pilot Flow Training - 03_ Low Power
Pilot Flow TrainingLow PowerPilot 3.1Predictable SuccessLow Power Flow•Low power is not a single point solution, rather it is theapplication of several methodologies throughout aflow -all aimed at decreasing power•Low Power is supported throughout the Pilot Flow with© 2006 Synopsys, Inc. (2)the following featuresClock GatingMulti-Vt Library supportStatic/Dynamic Power OptimizationUPF MVDD Implementation –see UPF unit for details Static/Dynamic Power AnalysisFill Cell, Fill Metal (ICC, Hercules)Final Extraction (Star RCXT)DRC/LVS Virtual Flat Planning MVDD Regions Power MeshCreation/Synthesi sPrototype Route RTL Synthesis Clock Gating DC, DCT GateOptimization (Design Scan Insertion ScanCompression JTAG Integration GateOptimization (Design Placement Optimization HFNS, Clock Optimization RouteOptimization RTLGDSIISynthesisDesign ForTest Design Planning P&ROptimization Chip FinishingSteps Tasks© 2006 Synopsys, Inc. (3)(Hercules)and IPOPin Assignment Budgeting (ICC)Compiler)Compiler)Global Analysis TasksSTA, Formal, ATPG, Power, Rail, EM/IRPower Closure SI Closure (IC Compiler)Metrics Capture & AnalysisGlobal TasksLow Power FlowClock GatingMulti-Vt LibrariesStatic/Dynamic OptimizationStatic/Dynamic Power Analysis© 2006 Synopsys, Inc. (4)Clock gating•Clock-gating insertion is a 2-step processperformed as part of the syn task in the SYN step The syn task usesTEV_PRE_COMPILE_SCRIPT to specify a design specific script to load before compiling the design•TEV_PRE_COMPILE_SCRIPT points to a local scriptblocks/<block>/scripts_block/syn/pr e_compile.tcl•The set_clock_gating_style command is © 2006 Synopsys, Inc. (5)part of the script. This command allows you to specify your clock-gating requirementsIn addition to the clock-gating specification, TEV_SYN_CMD must include “-gate_clock”•TEV_SYN_CMD is used to specify the compile command and options you want to use for your block•The default value of TEV_SYN_CMD is $tev_syn_cmd_default is compile_ultra –gate_clock –scan (for DCT)•To disable clock-gating, setTEV_SYN_CMD to not include “-gate_clock”Clock gating TVAR Settings•The default clock gating specification used in pre_compile.tcl makes use of two TVAR variables to define ICG (Integrated Clock Gating) cellsTVAR(lib,icg_scan_cellname) TVAR(lib,icg_noscan_cellname)•These are used as the –positive_edge_logic argument in the set_clock_gating_style command© 2006 Synopsys, Inc. (6)Which one is used depends upon whether scan is enabled for this designLow Power FlowClock GatingMulti-Vt LibrariesStatic/Dynamic OptimizationStatic/Dynamic Power Analysis© 2006 Synopsys, Inc. (7)Multi-VT Libraries•Pilot has variables which are used to set the libraries used for Multi-Vtoptimization throughout the flowThere is one variable used to specify the standard cell target libraries to be used•TVAR(config,target_libs)The link library list variable should always contain the target library settings plus any non-target libraries such as IO or RAM•TVAR(config,link_libs)© 2006 Synopsys, Inc. (8)Pilot Default Multi-Vt Flow•The Flow is configured to perform Multiple Vt optimization bydefault.If you are running DCT during the SYN step, leakage power optimization willhappen in the “syn” taskDuring the PNR step, Multi-Vt optimization will begin with theicc_place_opt task and continue through all other tasks© 2006 Synopsys, Inc. (9)•Variation on this flow can be effected by simply changing theappropriate variablesFor a single Vt flow simply specify a single Vt library in your targetlibrary variable TVAR(config,target_libs)Multi Vt Filler Cells•Filler cell insertion for Multi-Vt designs is technology dependentCan support both fill and decap-fill cells•To handle this a technology specific script is supplied with Pilot toperform multi-vt fill cell insertion in ICCscripts_techlib/<technology>/finish/icc_insert_filler_cells.tcl © 2006 Synopsys, Inc. (10)This is called out in the finish flow, it will need to be edited for newor updated technologies not supported in an initial Pilot release.It has some TEV parameters to control it as shown on next page This can perform a mixture of rules based and heuristic based fillercell insertion as requiredicc_insert_filler_cells.tcl© 2006 Synopsys, Inc. (11)Low Power FlowClock GatingMulti-Vt LibrariesStatic/Dynamic OptimizationStatic/Dynamic Power Analysis© 2006 Synopsys, Inc. (12)SYN Step Power Optimization•As per the recommended flow leakage power optimization is enabled in the default DCT flow. This is enabled byputting the following constraint in the constraints_design.tcl fileset_max_leakage_power 0•Dynamic Power is not enabled by default. To enable dynamic power optimization, you should add one of the following © 2006 Synopsys, Inc. (13)constraints to constraints_design.tcl set_max_dynamic_power 0 set_max_total_power 0•If dynamic power optimization is enabled, the tools by default use a vector-free approach for switching activity. If you would like to annotate your own switching activity file, you should include the appropriate commands inconstraints_design.tcl to include the file.PNR Step ICC Power Constraints Setup•Like the rest of the flow, the PNR step uses a vector-free approach for switching activity by default•If you annotated a switching activity file as part of the initial constraint file loaded duringSYN, the switching activity should carry forward to the rest of the flow in the database.© 2006 Synopsys, Inc. (14)•If you did not annotate a switching activity file during SYN, but would like to annotate one during PNR, then you should include the appropriate switching activity commands in the the PNR section of constraints_design.tcl.If you are enabling MCMM for ICC, then you should include switching activity for each scenario in constraints_design.tcl if you elect to NOT use the default vector-free approachDC/ICC Power Constraints•It is NOT a requirement to load switching activity files. DC andICC by default use a vector free approach for calculating dynamicpower consumption. Pilot is configured to use the vector-free approach by default.•The loading of switching activity, if NOT using the vector-free approach, should be included as part of the timing constraint file, © 2006 Synopsys, Inc. (15)TEV_CONSTRAINT_FILEDefault : blocks/<block>/scripts_block/conf/constraints_design.tcl Any valid tool command (e.g. set_switching_activity) can beincluded in this file.When MCMM is enabled, switching activity should be included for each scenario.DC/ICC Non-MCMM Power Constraints•For non-MCMM optimization, no scenarios are defined in constraints_design.tcl DC power optimization is © 2006 Synopsys, Inc. (16)•enabled byset_max_leakage_power, set_max_dynamic_power, set_max_total_power•Switching activity loaded once based upon commands included inconstraints_design.tclBy default no switching activity is loaded in the vector-freeMCMM Power Constraints•For DC/ICC MCMMoptimization, powerconstraints, if any, should beincluded for each scenario inconstraints_design.tcl© 2006 Synopsys, Inc. (17)PNR Step Power Optimization•Power optimization can be enabled during three tasks in the PNR flowicc_place_opt•To enable include “-power” in the TEV_PLACE_OPT_OPTIONS variableicc_clock_opt•Automatically performs power optimization based on TEV_SET_POWER_OPTIONS being non nullicc_route_opt•To enable include “-power” in the TEV_ROUTE_OPT_OPTIONS variable© 2006 Synopsys, Inc. (18)•In each of these tasks the TEV variable TEV_SET_POWER_OPTIONS isused to pass command options to the ICC set_power_options commandicc_place_opt TEV_SET_POWER_OPTIONS = “-leakage true –dynamic true” icc_clock_opt TEV_SET_POWER_OPTIONS = “-leakage true –dynamic true”icc_route_opt TEV_SET_POWER_OPTIONS = “-leakage true”•It is possible to perform different power optimizations in each task bysetting TEV variables on a task by task basisLow Power FlowClock GatingMulti-Vt LibrariesStatic/Dynamic OptimizationStatic/Dynamic Power Analysis© 2006 Synopsys, Inc. (19)Power Analysis•PrimeTime-PX is the recommended power analysis tool. Foraccurate power numbers, you must use PrimeTime-PX.•Power analysis is also performed in ICC and DCT (if poweroptimization is enabled).It is recommended that you only use these numbers as a relativeindication of power consumption. Here are the DCT and ICC power © 2006 Synopsys, Inc. (20)analysis reports that are generated.•blocks/<block>/syn/rpts/020_syn/dc.report_power•blocks/<block>/pnr/rpts/$GEV_DST/icc.report_power (where $GEV_DST is any icc task destination)•Use PrimeTime-PX for absolute power analysis numbersPrimeTime-PX Power Analysis• • • •TEV_POWER_ANALYSIS is set to 1 so power analysis is always enabled by default during STA runs PrimeTime-PX is run as part of the static timing analysis that happens at the end of each step. The static timing flow is run from its own makefile, blocks/<block>/scripts_block/sta/fl ow_sta.gmake The makefile contains 2 targets (one to generate scenarios and one to run the scenarios) for each step which are run at the end of each step© 2006 Synopsys, Inc. (21)Predictable Successexecute_scenarios.tcl• Power analysis is always enabled by default becauseTEV_POWER_ANALYSIS is set to 1 in flow_sta.gmake• The default switching format is VECTORFREE as specified byTEV_SWITCHING_FORMAT. Other options are TCL, SAIF and VCD. Note that you could still load SAIF or VCD formats even if you specify TCL for the switching format. You could do this by putting read_saif or read_vcd commands inside the TCL file pointed to by TEV_SWITCHING_FILE.© 2006 Synopsys, Inc. (22)Predictable SuccessSummary•Pilot supports several low power flow featuresClock Gating Multi-Vt Optimization Static and Dynamic power optimization•Power optimization occurs during PNR step and can optionally be enabled in the SYN step – optimization can occur with our without Multi-Vt cellsDCT Synthesis ICC Place Opt ICC Clock Opt ICC Route Opt•Pilot contains full support for implementation and verification of multi-VDD designs which is covered in the UPF unitCoarse grain MtCmos, level shifters, isolation cells, retention registers Demonstrated on the des_hard_macro_multi_vdd sample design•Power analysis is uses PrimeTime-PX and is run as part of the STA flow at the end of each step© 2006 Synopsys, Inc. (23)Predictable Success• Backup MaterialsInteractive Dynamic Power Gating Analysis© 2006 Synopsys, Inc. (24)Predictable SuccessPower Gating Dynamic IR AnalysisPM Cell PlacementPM Cell Placement• • •Main / controlled P/G routed & regular cells placed Need to decide Number and Location of PM cells Rail analysis needs: What-if analysis to enable quick iteration and decisionPowerPower-up Sequence DesignPowerPower-up Sequence Design• • •PM cells are placed PM cell P/G routed but signal pins not connected Rail analysis needs: Create power-up sequence “template” from design Flexibility in power-up sequence configuration to enable fast explorationFinal Analysis in implementation / signoffFinal Analysis / SignSign-off•Rail analysis needs: Link with IC Compiler for final analysis in implementation (vectorfree flow) Link with PrimeTime for sign-off (VCD flow)© 2006 Synopsys, Inc. (25)Predictable SuccessNumber & Location of PM CellsVDD VDDVVSS© 2006 Synopsys, Inc. (26)Predictable SuccessPower-Up SequenceVDD VDDVVSS© 2006 Synopsys, Inc. (27)Predictable SuccessWhat-if Power-Up SequenceVDD VDDVVSS© 2006 Synopsys, Inc. (28)Predictable Success“What-if” Sequence Analysis (65nM design)Wakeup Time Power-up sequence from PT report Peak rush current: 312mA Wake-up time: 4.9ns Peak voltage drop: 337mV One-by-oneWakeup TimeRow-by-rowRow-by-row turn-on with 0.1 ns interval Peak rush current: 789mA Wake-up time: 1.84ns Peak voltage drop: 642mV© 2006 Synopsys, Inc. (29)Predictable Success。
鼎利-Pilot Pioneer操作培训
鼎利通信 鼎力支持
Dingli Communications Inc.
TD-SCDMA MOS测试步骤 测试步骤
1. 2. 3. 4. 连接两个Da Tang手机，连接 手机， 语音评估盒和GPS，通过软件配置好设备； 连接两个 手机 连接TD-SCDMA MOS语音评估盒和 语音评估盒和 ，通过软件配置好设备； 新建TDSCDMA-MOS测试计划；选择New Dial，在网络类型中选择 测试计划；选择 新建 测试计划 ，在网络类型中选择TDSCDMA；输入被 ； 叫号码、呼叫持续时间、呼叫间隔、拨打次数等必要信息； 叫号码、呼叫持续时间、呼叫间隔、拨打次数等必要信息； 勾选Mos Process，在Play Device和Record Device中都选择 中都选择USB Audio CODEC（语 勾选 ， 和 中都选择 （ 音评估盒对应的声卡）；不要勾选Mutil MOS和Mobile to Fix； ）；不要勾选 音评估盒对应的声卡）；不要勾选 和 ； 将两个手机音量设成最大； 两个手机音量设成最大；
配置设备
连接好硬件后，双击导航栏“ Devices”或选择主菜单“设置 或选择主菜单“ 连接好硬件后，双击导航栏“设备 或选择主菜单 设备” 弹出设备配置对话框，增加相关设备， 设备”，弹出设备配置对话框，增加相关设备，可以通过大唐驱动来查 看每个设备的端口号（一般是3个端口 一个trace，一个 个端口， 看每个设备的端口号（一般是 个端口，一个 ，一个modem，一个 ， 用于建立拨号连接）。 用于建立拨号连接）。 终端trace端口 终端 端口
鼎利通信 鼎力支持
Dingli Communications Inc.
连接设备－ 连接设备－开始记录
配置完设备和测试模板后，即可开始测试； 配置完设备和测试模板后，即可开始测试； 选择主菜单“ 连接” 选择主菜单“记录 连接”或点击工具栏 选择主菜单“记录 开始” 选择主菜单 记录 开始”或点击工具栏 开始记录； 开始记录； 按钮，连接设备； 按钮，连接设备； 按钮， 按钮，指定测试数据名称后
ClearCase使用培训(测试与开发人员)
软件技术处
使用版本扩展命名法
使用标准命名法，将看到当前试图选择 的元素版本
使用扩展版本命名法，将能看到试图中 的任意版本
软件技术处
使用版本树浏览器
版本树浏览器使用一个层次图来显示一 个元素的进化情况
标有“眼睛”的图标显示当前试图选择 的版本
软件技术处
元素的属性
元素的属性可以通过 自己的属性页查看
IDE开发工具
软件技术处
ClearCase命令行工具
软件技术处
ClearCase学习途径
在线帮助 pdf手册 Clearcase新闻组
软件技术处
三、使用初步
版本对象库（VOB） 元素（element） 版本（Version）、版本树（ Version Tree） 视图（View） 视图配置规则（Config Spec） 使用模式（Checkout – Edit –Checkin ） 分支 （Branch） 归并 （Merge） 标签 （Label）
0 1
2
3
3
7
软件技术处
版本、版本树
控制任何文件的版本
可对目录和子目录进行 版本控制
完美的分支和归并功能 采用版本树结构 文本比较
丰富的注释和版本报告 信息
\main
0
LABELS
BETA_01 1 RLS1.0 2
RLS2.0 3
\enhance
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\special
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ClearCase
使用培训(研发、测试人员)
软件技术处
培训内容
ClearCase简介 ClearCase界面 使用初步 版本化工作 文件的版本 目录的版本 ClearCase程序组工具简介 使用技巧及注意事项
3d扫描及cyclone系统培训_review_080527
关键词：导航窗口，数据库1.右键点击导航窗口中的“服务器”对象，选择“Database”（也可使用菜单命令Configure>Database），点击“Add”，在“Name”处输入数据库名，这样建立了一个空的数据库。
2.如果要打开一个已有数据库，在上图中点击“…”，在打开的对话框中选择后缀为imp的文件，这时“Database Name”栏中自动取名为文件名，必要时可进行修改。
项目的建立关键词：导航窗口，项目1.右键点击导航窗口中的“数据库”对象，选择“Creat>Project”，这时可采用默认的名称，也可修改这个默认名。
2.如果要修改已有的项目名，可单击这个项目名，再次单击，即可进行修改。
关键词：导航窗口，扫描仪1.连接扫描仪2.右键点击导航窗口中的“Scanner”，选择“Scanner”，点击“Add”，选择设备型号，输说明：如果第一步正确地连接了扫描仪，此时OK按钮变为可点击。
？服务器的建立关键词：导航窗口，服务器1.点击菜单configure，servers, 点击“Add”，给服务器起名。
2.点击servers右键也可建立。
Cyclone菜单标把拼接关键词：导航窗口，拼接窗口，视图窗口，标靶，拼接1.右键单击数据库，Creat>Registration，建立了一个拼接站，系统进行自动命名（必要时可修改这个名字），双击这个拼接站，进入拼接站界面。
2. 选择ModelSpace 卡，点击“Add Scanworld ”按钮（或使用菜单命令ScanWord>AddScanword ），添加两站数据。
1.点击这个卡2.再点击这个按钮3. 使用菜单命令“Constraint>Auto-Add Constraint ”添加标靶约束4. 使用菜单命令Registration>Register 进行（两站点云）数据拼接2.点击OK5.在Constraint list卡中，检查标靶误差6.使用菜单命令Registration>Create ScanWorld/Freeze Registration建立一个ScanWord。
ClearCase training
• Dunton ClearCase domain: 6976\CDSID
ClearCase Training
for Powertrain
Introduction
Goals of this training session:
• Provide Engineers with overview of ClearCase so that they can begin using the tool effectively • Demonstrate common ClearCase operations
25/09/2016
5
Overview
• How Does ClearCase differ from other common version control systems? • The most common model for a version control system is to have a separate archive. Files are extracted from this archive into the file system. (SCCS, RCS, PVCS, CMS are expamples of this type of system) • .ClearCase differs by providing extensions to the file system that supports multiple versions. No separate archive file exists (as far as the user is concerned).