IRLR8726 规格书

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8726C 8726W Addressable Remote Lamps 说明书

INTRODUCTIONThe 8726C (round plate) and 8726W (rectangular plate) Address-able Remote Lamps, shown in Figure 1, operate as an additional LED indicator for a device in the fire alarm control system’s addres-sable device circuit. The 8726C/8726W can be used when a device already has an accessory. The 8726C/8726W can be installed at any location of an addressable device circuit, and it remotely indicates the status of the device(s) in that same circuit.Mode of OperationThe 8726C/8726W has one mode of operation: Direct Addressing Mode. The two-position jumper P1 must be positioned to set the mode to Direct Addressing.When set and programmed to Direct Addressing Mode, system logic and programming determine when the ILED-H will blink.Controls and IndicatorsIn Direct Addressing mode, the LED on the 8726C/8726W is controlled by logic functions programmed using the CIS-4 Tool. In Direct Addressing mode, the 8726C/8726W blink color (red only) cannot be changed.PROGRAMMINGRefer to Figure 2 for the location of the programming holes and jumper P1.Direct Addressing ModeTo set the 8726C/8726W to Direct Addressing Mode follow the steps listed below:1.Determine a unique address for the 8726C/8726W.2.Set jumper P1 to position 2 and3.3.Connect the 8726C/8726W to the 8720 Programmer/Tester byinserting the plug from the cable provided with the 8720 Programmer/Tester into the programming holes on the 8726C/8726W board.4.Follow the instructions in the 8720 Programmer/Tester Manual, P/N 315-033260FA, to program the 8726C/8726W to the desired address. Record the device address on the label located on the 8726C/8726W front panel.INSTALLATION INSTRUCTIONS AND WIRING FORINTELLIGENT REMOTE LAMPSP/N 8726C AND 8726WFigure 18726C And 8726W Remote LampsSiemens Industry, Inc.Building Technologies Division • Florham Park, NJ Tel: (973) 593-2600 • Fax: (973) 593-6670Web: Figure 28726 Printed Circuit Board5.In the CIS-4 Programming Tool, assign the 8726C/8726W to an output zone. When an Input Group that is assigned to that Output Zone reports an off-normal event, the 8726C/8726W will blink red if the reported event type matches the output type selected for its zone. Refer to the CIS-4 Manual for further information.6.The 8726C/8726W can now be installed and wired to the system.WIRINGWARNING: Disconnect BATTERY and AC prior to working on equipment.Refer to the wiring diagram in Figure 3 below to wire the 8726C/8726W.NOTE: The 8726C/8726W is polarity insensitive. Switching Line1 and Line2 has no effect on performance.Recommended wire size:18 AWG minimum, 14 AWG maximumWire larger than 14 AWG can damage the connector.LINE2LINE1TO ADDRESSABLE DEVICE CIRCUITFigure 3Wiring The 8726C/8726WINSTALLATIONNOTE: Be sure to program the 8726C/8726W before installing the unit.The 8726C/8726W may be placed at any location on the address-able device circuit. Use a single-gang switch box (user supplied) for mounting the 8726W. Use a 4-inch octagonal conduit box (user supplied) for mounting the 8726C. Refer to Figure 4 for typical 8726C/8726W installation.The number of 8726C/8726W modules on the addressable device circuit must be included in the total count of intelligent field devices.For the restriction of the total number of devices in the FDLC loop,refer to the FDLC Installation Instructions, P/N 315-447360FA.ELECTRICAL RATINGSDO NOT USE REAR CONDUIT ENTRYFigure 4Mounting The 8726Wtn e r r u C t u p n I Am 1。

TM8726资料

TM87264 Bit Microcontroller GENERAL DESCRIPTIONThe TM8726 is an embedded high-performance 4-bit microcomputer with LCD driver. It contains all the necessary functions, such as 4-bit parallel processing ALU, ROM, RAM, I/O ports, timer, clock generator, dual clock operation, Resistance to Frequency Converter(RFC), EL panel driver, LCD driver, look-up table, watchdog timer and key matrix scanning circuitry in a signal chip.FEATURE1. Low power dissipation.2. Powerful instruction set (178 instructions).z B inary addition, subtraction, BCD adjust, logical operation in direct and index addressing mode.z S ingle-bit manipulation (set, reset, decision for branch).z V arious conditional branch.z16 working registers and manipulation.z T able look-up.z L CD driver data transfer.3. Memory capacity.4096x 16 bits.capacityz R OMz R AM capacity 512 x 4 bits.4. LCD driver output.z9 common outputs and 41 segment outputs (up to drive 369 LCD segments).z1/2 Duty, 1/3 Duty, 1/4 Duty, 1/5 Duty, 1/6Duty, 1/7Duty, 1/8Duty or 1/9Duty is selected by MASK option.z1/2 Bias, 1/3 Bias or 1/4 Bias is selected by MASK option.z S ingle instruction to turn off all segments.z C OM5~9,SEG1~41 could be defined as CMOS or P_open drain type output by mask option.5. Input/output ports.z P ort IOA 4 pins (with internal pull-low), muxed with SEG24~SEG27.z P ort IOB 4 pins (with internal pull-low). muxed with SEG28~SEG31z P ort IOC 4 pins (with internal pull-low, low-level-hold), muxed with SEG32 ~SEG35.IOC port had built in the input signal chattering prevention circuitry.z P ort IOD 4 pins (with internal pull-low), muxed with SEG36 ~ SEG39. IODport had built in the input signal chattering prevention circuitry.6. 8 level subroutine nesting.7. Interrupt function.z E xternal factors 4(INT pin, Port IOC, IOD & KI input).z I nternal factors 4(Pre-Divider, Timer1, Timer2 & RFC).8. Built-in EL-light driver.z E LC, ELP (Muxed with SEG28, SEG29).9. Built in Alarm, clock or single tone melody generator.z B ZB, BZ (Muxed with SEG30, SEG31).10. Built-in resistance to frequency converter.z C X, RR, RT, RH (Muxed with SEG24 ~ SEG27).11. Built in key matrix scanning function.z K1~K16 (Shared with SEG1~SEG16).z K I1~KI4 (Muxed with SEG32 ~ SEG35).12. Two 6-bit programmable timer with programmable clock source.13. Watch dog timer.14. Built-in Voltage doubler, halver, tripler, quartic charge pump circuit.15. Dual clock operationz s low clock oscillation can be defined as X’tal or external RC type oscillator by mask option.z f ast clock oscillation can be defined as 3.58MHz ceramic resonator, internal R or external R type oscillator by mask option.16. HALT function.17. STOP function.APPLICATIONTimer / Calendar/Calculator / Thermometer2 tenx technology, inc.BLOCK DIAGRAM3 tenx technology, inc.4 tenx technology, inc.PAD DIAGRAMThe substrate of chip should be connected to GND.110203040506066PAD COORDINATENo Name X Y No Name X Y1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930313233BAKXINXOUTCFINCFOUTGNDVDD1VDD2VDD3VDD4CUP0CUP1CUP2COM1COM2COM3COM4COM5COM6COM7COM8COM9SEG1(K1)SEG2(K2)SEG3(K3)SEG4(K4)SEG5(K5)SEG6(K6)SEG7(K7)SEG8(K8)SEG9(K9)SEG10(K10)SEG11(K11)72.5072.5072.5072.5072.5072.5072.5072.5072.5072.5089.50204.50319.50434.50549.50669.50789.50909.501029.501149.501269.501389.501509.501629.501677.501677.501677.501677.501677.501677.501677.501677.501677.501229.501114.50999.50884.50769.50654.50539.50424.50309.50194.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.50197.50322.50439.50554.50669.50784.50899.501014.501129.50343536373839404142434445464748495051525354555657585960616263646566SEG12(K12)SEG13(K13)SEG14(K14)SEG15(K15)SEG16(K16)SEG17SEG18SEG19SEG20SEG21SEG22SEG23SEG24/IOA1/CXSEG25/IOA2/RRSEG26/IOA3/RTSEG27/IOA4/RHSEG28/IOB1/ELCSEG29/IOB2/ELPSEG30/IOB3/BZBSEG31/IOB4/BZSEG32/IOC1/KI1SEG33/IOC2/KI2SEG34/IOC3/KI3SEG35/IOC4/KI4SEG36/IOD1SEG37/IOD2SEG38/IOD3SEG39/IOD4SEG40SEG41RESETINTTEST1677.501677.501677.501677.501677.501677.501677.501677.501677.501677.501677.501558.501430.451305.001164.501024.00881.50766.50651.50536.50421.50306.50191.5072.5072.5072.5072.5072.5072.5072.5072.5072.5072.501244.501359.501474.501589.501704.501819.501934.502049.502175.002300.002477.002507.502507.502507.502507.502507.502507.502507.502507.502507.502507.502507.502507.502477.002300.002175.002049.501934.501819.501704.501589.501474.501359.505 tenx technology, inc.PIN DESCRIPTIONName I/O DescriptionBAK P Positive Back-up voltage.At Li power mode, connect a 0.1u capacitor to GND.VDD1,2,3,4P LCD supply voltage, and positive supply voltage..In Ag Mode, connect positive power to VDD1..In Li or ExtV power mode, connect positive power to VDD2.RESET I Input pin for external reset request signal, built-in internal pull-down resistor.INT I Input pin for external INT request signal.. Falling edge or rising edge triggered is defined by mask option.. Internal pull-down or pull-up resistor is defined by mask option.TEST Test signal input pin.CUP0,1,2O Switching pins for supply the LCD driving voltage to the VDD1, 2,3,4 pins.. Connect the CUP0, CUP1 and CUP2 pins with non-polarized electrolytic capacitorswhen chip operated in 1/2, 1/3 or 1/4 bias mode.. In no BIAS mode application, leave these pins opened.XIN XOUT IOTime base counter frequency (clock specified. LCD alternating frequency. Alarm signal frequency) or system clock oscillation.. The usage of 32KHz Crystal oscillator or external RC oscillator is defined by mask option.CFIN CFOUT IOSystem clock oscillation for FAST clock only or DUAL clock operation.. The usage of 3.58MHz ceramic/resonator oscillator or external R type oscillator is defined by mask optionCOM1~9O Output pins for driving the common pins of the LCD panel.COM5~9 could be defined as COMS or Open Drain type output. SEG1-41O Output pins for driving the LCD panel segment.IOA1-4I/O Input / Output port A, (muxed with SEG24~27)IOB1-4I/O Input / Output port B, (muxed with SEG28~31)IOC1-4I/O Input / Output port C, (muxed with SEG32~35)IOD1~4 I/O Input / Output port D, (muxed with SEG36~39)CXRR/RT/RH IO1 input pin and 3 output pins for RFC application. (muxed with SEG24~27)ELC/ELP O Output port for El panel driver. (muxed with SEG28~29)BZB/BZ O Output port for alarm, clock or single tone melody generator. (muxed with SEG30~31) K1~K16 O Output port for key matrix scanning.(Shared with SEG1~SEG16)KI1~4 I Input port for key matrix scanning.(Muxed with SEG32~SEG35)GND P Negative supply voltage.ABSOLOUTE MAXIMUM RATINGSGND= 0VName Symbol Range UnitVDD1 -0.3 to 5.5 VVDD2 -0.3 to 5.5 VVDD3 -0.3 to 8.5 VMaximum Supply VoltageVDD4 -0.3 to 8.5 VMaximum Input Voltage Vin -0.3 to VDD1/2+0.3 VVout1 -0.3 to VDD1/2+0.3 VVout2 -0.3 to VDD3+0.3 VMaximum output VoltageVout3 -0.3 to VDD4+0.3 VMaximum Operating Temperature Topg -20 to +70 ℃Maximum Storage Temperature Tstg -25 to +125 ℃6 tenx technology, inc.7 tenx technology, inc.POWER CONSUMPTIONat Ta=-20℃ to 70℃,GND= 0VName Sym. Condition Min.Typ. Max. Unit I HALT1 Only 32.768KHz Crystal oscillator operating, without loading.Ag mode, VDD1=1.5V, BCF = 02 uAHALT mode I HALT2 Only 32.768KHz Crystal oscillator operating, without loading. Li mode, VDD2=3.0V, BCF = 02 uASTOP mode I STOP 1 uA Note : When RC oscillator function is operating, the current consumption will depend on the frequency ofoscillation.ALLOWABLE OPERATING CONDITIONSat Ta=-20℃ to 70℃,GND= 0VName Symb. Condition Min. Max. UnitVDD1 1.2 5.25 V VDD2 2.4 5.25 VVDD3 2.4 8.0 V Supply Voltage VDD4 2.4 8.0 V Oscillator Start-Up Voltage VDDB Crystal Mode 1.3VOscillator Sustain Voltage VDDB Crystal Mode 1.2V Supply Voltage VDD1 Ag Mode 1.2 1.65 V Supply Voltage VDD2 EXT-V, Li Mode 2.4 5.25 V Input “H” Voltage Vih1 VDD1-0.7VDD1+0.7V Input “L” Voltage Vil1 Ag Battery Mode -0.7 0.7 VInput “H” Voltage Vih2 VDD2-0.7VDD2+0.7V Input “L” Voltage Vil2 Li Battery Mode -0.7 0.7 V Input “H” Voltage Vih3 0.8xVDD1VDD1 V Input “L” Voltage Vil3 OSCIN at AgBattery Mode 0 0.2xVDD1VInput “H” Voltage Vih4 0.8xVDD2VDD2 V Input “L” Voltage Vil4 OSCIN at LiBattery Mode 0 0.2xVDD2VInput “H” Voltage Vih5 0.8xVDD2VDD2 V Input “L” Voltage Vil5 CFIN at Li Batteryor EXT-V Mode 0 0.2xVDD2VInput “H” Voltage Vih6 0.8xVDDO VDDO V Input “L” Voltage Vil6 RC Mode 0 0.2xVDDO V Fopg1 Crystal Mode 32 KHZFopg2 RC Mode 10 1000 KHZ Operating Freq Fopg3 CF Mode 1000 3580 KHzALLOWABLE OPERATING FREQUENCYat Ta=-20℃ to 70℃,GND= 0VConditionMax, Operating FrequencyBAK=1.5V (VDD1) 800KHz BAK=3V (VDD2) 4MHz8 tenx technology, inc.INTERNAL RC FREQUENCY RANGEOption Mode BAKMin. Typ. Max.1.5V 200KHz 300KHz 400KHz 250KHz 3.0V 200KHz 250KHz 300KHz 1.5V 450KHz 600KHz 750KHz 500KHz 3.0V400KHz 500KHz 600KHzELECTRICAL CHARACTERISTICSat#1:VDD1=1.2V(Ag); at#2:VDD2=2.4V(Li): at#3:VDD2=4V(Ext-V);Input ResistanceName Symb. Condition Min.Typ.Max. UnitRllh1 Vi=0.2VDD1,#1 10 40 100 KohmRllh2 Vi=0.2VDD2,#2 10 40 100 Kohm “L” Level Hold Tr(IOC) Rllh3 Vi=0.2VDD2,#3 5 20 50 KohmRmad1 Vi=VDD1,#1 200500 1000 KohmRmad2 Vi=VDD2,#2 200500 1000 Kohm IOC Pull-Down Tr Rmad3 Vi=VDD2,#3 100250 500 KohmRintu1 Vi=VDD1,#1 200500 1000 KohmRintu2 Vi=VDD2,#2 200500 1000 Kohm INT Pull-up Tr Rintu3 Vi=VDD2,#3 100250 500 KohmRintd1 Vi=GND,#1 200500 1000 KohmRintd2 Vi=GND,#2 200500 1000 Kohm INT Pull-Down Tr Rintd3 Vi=GND,#3 100250 500 KohmRres1 Vi=GND or VDD1,#110 40 100 KohmRres2 Vi=GND or VDD2,#210 40 100 Kohm RES Pull-Down R Rres3 Vi=GND or VDD2,#310 40 100 KohmDC Output CharacteristicsName Symb. Condition Port Min.Typ.Max. UnitVoh1c Ioh=-200uA,#1 0.8 0.9 1.0 V Voh2c Ioh=-1mA,#2 1.5 1.8 2.1 VOutput ”H” Voltage Voh3c Ioh=-3mA,#3 2.5 3.0 3.5 VVol1c Iol=400uA,#1 0.2 0.3 0.4 V Vol2c Iol=2mA,#2 0.3 0.6 0.9 VOutput ”L” Voltage Vol3c Iol=6mA,#3 COM5~9 SEG1~410.5 1.0 1.5 V9 tenx technology, inc.Segment Driver Output CharacteristicsNameSymb.Condition For Min.Typ.Max. Unit. Static Display ModeVoh1d Ioh=-1uA,#1 1.0 V Voh2d Ioh=-1uA,#2 2.2 VOutput ”H” Voltage Voh3d Ioh=-1uA,#3 3.8 V Vol1d Iol=1uA,#1 0.2 VVol2d Iol=1uA,#2 0.2 VOutput ”L” Voltage Vol3d Iol=1uA,#3 SEG-n 0.2 VVoh1e Ioh=-10uA,#1 1.0 V Voh2e Ioh=-10uA,#2 2.2 VOutput ”H” Voltage Voh3e Ioh=-10uA,#3 3.8 VVol1e Iol=10uA,#1 0.2 VVol2e Iol=10uA,#2 0.2 VOutput ”L” VoltageVol3e Iol=10uA,#3 COM-n 0.2 V1/2 Bias Display ModeVoh12f Ioh=-1uA,#1,#2 2.2 V Output ”H” Voltage Voh3f Ioh=-1uA,#3 3.8 V Vol12f Iol=1uA,#1,#2 0.2 VOutput ”L” Voltage Vol3f Iol=1uA,#3 SEG-n 0.2 VVoh12g Ioh=-10uA,#1,#2 2.2 VOutput ”H” Voltage Voh3g Ioh=-10uA,#3COM-n 3.8 V Vom12g Iol/h=+/-10uA,#1,#2 1.0 1.4 V Output ”M” VoltageVom3g Iol/h=+/-10uA,#3 COM-n 1.8 2.2 V1/3 Bias display ModeVoh12h Ioh=-1uA,#1,#2 3.4 V Output ”H” Voltage Voh3h Ioh=-1uA,#3 5.8 V Vom1h Iol/h=+/-10uA,#1,#2 1.0 1.4 V Output ”M1” Voltage Vom13h Iol/h=+/-10uA,#3 1.8 2.2 VVom22h Iol/h=+/-10uA,#1,#2 2.2 2.6 V Output ”M2” Voltage Vom23h Iol/h=+/-10uA,#3 3.8 4.2 VVol12h Iol=1uA,#1,#2 0.2 V Output ”L” Voltage Vol3h Iol=1uA,#3 SEG-n 0.2 VVoh12i Ioh=-10uA,#1,#2 3.4 V Output ”H” Voltage Voh3i Ioh=-10uA,#3 5.8 V Vom12i Iol/h=+/-10uA,#1,#2 1.0 1.4 V Output ”M1” Voltage Vom13i Iol/h=+/-10uA,#3 1.8 2.2 VVom22i Iol/h=+/-10uA,#1,#2 2.2 2.6 V Output ”M2” Voltage Vom23i Iol/h=+/-10uA,#3 3.8 4.2 VVol12i Iol=10uA,#1,#2 0.2 V Output ”L” VoltageVol3i Iol=10uA,#3 COM-n 0.2 V1/4 Bias display ModeOutput ”H” VoltageVoh12j Ioh=-1uA,#1,#2 4.6 V Output ”M2” Voltage Vom22j Iol/h=+/-10uA,#1,#2 2.2 2.6 VOutput ”L” Voltage Vol12j Iol=1uA,#1,#2 SEG-n 0.2 VOutput ”H” Voltage Voh12k Ioh=-10uA,#1,#2 4.6 VOutput ”M1” Voltage Vom12k Iol/h=+/-10uA,#1,#2 1.0 1.4 V Output ”M3” Voltage Vom22k Iol/h=+/-10uA,#1,#2 3.4 3.8 VOutput ”L” VoltageVol12k Iol=10uA,#1,#2 COM-n 0.2 VTYPICAL APPLICATION CIRCUITMatrixLi power mode, 1/4 Bias, 1/9 Duty10 tenx technology, inc.。

mos管8726参数

mos管8726参数摘要：1.mos 管简介2.8726 参数概述3.8726 参数详细解读4.8726 参数在实际应用中的意义正文：MOS 管，全称为金属- 氧化物- 半导体场效应晶体管，是一种广泛应用于电子设备中的半导体器件。

它具有高输入阻抗、低噪声、低失真等优点，在电路设计中有着重要地位。

8726 是一种特定的MOS 管型号，具有多种参数。

接下来，我们将详细解读这些参数，并探讨它们在实际应用中的意义。

一、mos 管简介金属- 氧化物- 半导体场效应晶体管（MOSFET）是一种半导体器件，具有高输入阻抗、低噪声和低失真等优点。

它由源极、漏极和栅极三个端口组成，通过改变栅极电压来控制源漏电流的大小。

在电路设计中，MOS 管被广泛应用于放大器、开关、振荡器等电子设备。

二、8726 参数概述8726 是一种N 沟道增强型MOS 管，具有以下主要参数：1.静态漏极电压（VDS）：30V2.最大漏极电流（ID）：26A3.栅极漏极电压（VGS）：-20V to 20V4.输入电容（Ciss）：1.8pF5.导通电阻（RDS(on)）：0.028Ω三、8726 参数详细解读1.静态漏极电压（VDS）：30V静态漏极电压是指在栅极电压为0V 时，漏极所能承受的最大电压。

8726 的静态漏极电压为30V，意味着在正常工作范围内，漏极电压不会超过30V，从而保证了器件的安全稳定运行。

2.最大漏极电流（ID）：26A最大漏极电流是指在栅极电压达到最大值时，漏极所能流过的最大电流。

8726 的最大漏极电流为26A，表明该型号的MOS 管具有较高的电流驱动能力。

3.栅极漏极电压（VGS）：-20V to 20V栅极漏极电压是指在漏极电压不变的情况下，栅极电压的变化范围。

8726 的栅极漏极电压为-20V to 20V，意味着在正常工作范围内，栅极电压可以在-20V 至20V 之间变化。

4.输入电容（Ciss）：1.8pF输入电容是指MOS 管栅极与源极之间的电容。

irlr8726场效应管参数

irlr8726场效应管参数
场效应管（Field Effect Transistor，简称FET）是一种三端
元件，常用于放大或开关电路中。

IRLR8726是一种N沟道场效应管，具有以下参数：
1. 饱和漏-源电压（VDS），这是场效应管在完全导通状态下的
漏-源电压。

对于IRLR8726，这个参数通常在数据手册中给出。

2. 饱和漏-源电流（IDS），这是场效应管在饱和状态下的漏-
源电流。

同样，这个参数也会在数据手册中有详细说明。

3. 静态工作点，静态工作点是指场效应管在特定电压和电流条
件下的工作状态，通常由漏-源电流和漏-源电压来描述。

4. 输入电容（Ciss），这是场效应管的输入电容，影响着场效
应管的高频特性和输入阻抗。

5. 输出电容（Coss），这是场效应管的输出电容，影响着场效
应管的高频特性和输出阻抗。

6. 开关时间，开关时间是指场效应管从完全关断到完全导通的时间，通常由上升时间和下降时间来描述。

7. 最大耗散功率（Pd），这是场效应管可以持续耗散的最大功率，超过这个功率会导致场效应管过热损坏。

以上是IRLR8726场效应管的一些基本参数，这些参数对于设计电路和选择合适的场效应管都非常重要。

当然，实际使用时还需要参考数据手册中的具体参数和曲线图来进行综合考虑。

希望这些信息能够帮助到你。

AML8726-MX UART Interface User Guide 20120522

Application NotesAML 8726-MXUART Interface User GuideAMLOGIC, Inc.3930 Freedom Circle Santa Clara, CA 95054U.S.A.AMLOGIC reserves the right to change any information described herein at any time without notice.AMLOGIC assumes no responsibility or liability from use of such information.Di s t ri bu t et oE md o o r!Table of Content1. GENERAL DESCRIPTION ............................................................................................................................................. 42. OVERVIEW ....................................................................................................................................................................... 43. FEATURES ........................................................................................................................................................................ 44.UART SIGNAL AND PIN MAPPING ............................................................................................................................ 5 4.1. S IGNAL ......................................................................................................................................................................... 5 4.2. P IN M APPING . (5)5. INTERRUPT (6)6. POWER MANAGEMENT ............................................................................................................................................... 77. RESET ................................................................................................................................................................................ 78.BAUD RATE ...................................................................................................................................................................... 8 8.1. I NPUT C LOCK ................................................................................................................................................................ 8 8.2.B AUD R ATE G ENERATION ............................................................................................................................................ 8 9. REGISTER DESCRIPTIONS (9)9.1. UART_A ...................................................................................................................................................................... 9 9.2. UART_B .................................................................................................................................................................... 14 9.3. UART_C .................................................................................................................................................................... 19 9.4. UART_AO ................................................................................................................................................................. 24 10. ADDRESS MAPPING ................................................................................................................................................. 29 11.ANDROID™/LINUX KERNE L (30)11.1. O PERATION M ACRO D EFINITION ............................................................................................................................ 30 11.2.R EGISTER M ACRO D EFINITION (30)Di s t ri bu t et oE md o o r!Revision HistoryRevision Number Revised Date By Changes0.1 Feb. 15, 2012 Kevin Zhu Initial release draft0.2 May. 22,2012 Kevin Zhu UART0~2 renamed to UART_A, UART_B and UART_CDi s t ri bu t et oE md o o r!1. General DescriptionAmlogic AML8726-MX is a highly integrated multimedia application processor SoC for Multimedia Internet Device (MID), tablet and Set Top Box (STB). It integrates a powerful CPU, a 2D/3D graphics subsystem and a state-of-the-art video decoding engine together with all major peripherals.This document is a user guide of universal asynchronous receiver/transmitter (UART) serial ports integrated in AML8726-MX.The guide provides:● An overview of UART interface ● The feature of UART● The UART interface pin selection ● The baud rate generation● The register definition that control and operate UART interface ● AML8726-MX UART in Android/Linux Amlogic porting2. OverviewEach AML8726-MX has four fully functional UARTs which use the same programming model. They are named as UART_A, UART_B, UART_C and UART_AO. The one with ‘AO ’ in the naming are located at the Always-On (AO) power domain, which cannot be powered off unless AML8726-MX is disconnected from power supply.The four UARTs are controlled separately. Each UART has a build-in standalone register set for controlling and data exchange.The UARTs in AML8726-MX can only operate in FIFO mode. UART_A has a 128-byte RX/TX FIFO and UART_B/UART_C/UART_AO has a 64-byte FIFO. If non-FIFO mode is required, the registers of UART should be fine tuned and a polling mechanism should be used to fulfill.Each UART has programmable interrupt generation circuit which will reduce the loading of processor and to improve communication performance.A baud-rate generator is also contained in each UART to provide flexible division of input clock by 1 to (216-1) or 1to (223-1) according to the setting in the internal register.3. FeaturesThe UARTs share the following features:● Each UART independent control register set● Independently controlled transmit and receive interrupts with FIFO threshold ● Programmable serial interface:⏹ 5-, 6-, 7- or 8-bit characters⏹ Even, odd or no parity detection ⏹ 1 stop bit generation⏹ Programmable baud rate● 64-byte transmit and receive FIFO (UART_B/UART_C/UART_AO) ● 128-byte transmit and receive FIFO (UART_A) ● Automatic frame error detection● Programmable RX, TX, RTS, CTS signal polarityDi s t ri bu t et oE md o o r!4. UART Signal and Pin Mapping4.1. SignalEach AML8726-MX UART function module has 4 external signals which can be connected to a series of GPIO pins via pin multiplex mapping circuit. The pins transmit digital CMOS-level signals only.The signals are described in the table below:Table 1. UART Signal DescriptionsName Type Description RX Input Serial data input to the receive shift register and Receive FIFO. TX Output Serial data output to external data set. CTS Input Clear to Send.When asserted, it indicates that the receiver is ready to exchange data.RTS Output Request to Send.When asserted, it notifies the receiver that the sender is ready to exchange data.4.2. Pin MappingIn AML8726-MX, only UART RX and TX signal are available. If CTS and RTS signal are required, please contact with Amlogic Sales.AML8726-MX has 11 GPIO banks. UART_A, UART_B and UART_C are located in Bank X and UART_AO is in the dedicated Bank AO. RX and TX signals of the UART function blocks can be multiplexed to the corresponding bank in pair.The relationship between pins and registers of each UART signal and GPIO bank is shown in the table below:Table 2. UART Signal Pin out MappingUART Module UART Signal Bank X Bank AOUART_AUART_RX_A GPIOX_14 UART_TX_A GPIOX_13UART_CTS_A GPIOX_15 UART_RTS_A GPIOX_16 UART_BUART_RX_B GPIOX_18 UART_TX_B GPIOX_17UART_CTS_B GPIOX_19 UART_RTS_B GPIOX_20 UART_CUART_RX_C GPIOX_22 UART_TX_C GPIOX_21UART_CTS_C GPIOX_23 UART_RTS_C GPIOX_24 UART_AOUART_RX_AO GPIOAO_1 UART_TX_AO GPIOAO_0UART_CTS_AO GPIOAO_2 UART_RTS_AO GPIOAO_3About GPIO function settings, please refer to AML8726-MX GPIO User Guide for detailed description.Di s t ri bu t et oE md o o r!5. InterruptThe UART interrupts are controlled in two levels: CPU and Function.In CPU level, the UART interrupts can be controlled and programmed by using the registers below:Table 3. Interrupt Control Register UART CPU LevelUART Module Offset Bit R/WUART_A 0x2690 bit 26 R UART_A interrupt flag. When interrupt happens, it will beset to 1.0x2691 bit 26 R/W Write 1 to this register bit to clean UART_A interrupt flag.0x2692 bit 26 R/W Interrupt mask. Set to 1 to mask UART_A interrupt (disableUART_A interrupt).0x2693 bit 26 R/W Fast interrupt enable. Set to 1 to enable UART_A interruptmultiplexing to CPU FAST interruptUART_B 0x2698 bit 11 R UART_B interrupt flag. When interrupt happens, it will beset to 1.0x2699 bit 11 R/W Write 1 to this register bit to clean UART_B interrupt flag.0x269A bit 11 R/W Interrupt mask. Set to 1 to mask UART_B interrupt (disableUART_A interrupt).0x269B bit 11 R/W Fast interrupt enable. Set to 1 to enable UART_B interruptmultiplexing to CPU FAST interruptUART_C 0x2698 bit 29 R UART_C interrupt flag. When interrupt happens, it will beset to 1.0x2699 bit 29 R/W Write 1 to this register bit to clean UART_C interrupt flag.0x269A bit 29 R/W Interrupt mask. Set to 1 to mask UART_C interrupt (disableUART_AO interrupt).0x269B bit 29 R/W Fast interrupt enable. Set to 1 to enable UART_C interruptmultiplexing to CPU FAST interruptUART_AO 0x2698 bit 26 R UART_AO interrupt flag. When interrupt happens, it will beset to 1.0x2699 bit 26 R/W Write 1 to this register bit to clean UART_AO interrupt flag.0x269A bit 26 R/W Interrupt mask. Set to 1 to mask UART_AO interrupt(disable UART_AO interrupt).0x269B bit 26 R/W Fast interrupt enable. Set to 1 to enable UART_AO interruptmultiplexing to CPU FAST interruptIn Function Level, the block registers need to be set to enable UART interrupt. ● UART_A: UART_A_CONTROL[27] and [28] must be set to 1. ● UART_B: UART_B_CONTROL[27] and [28] must be set to 1. ● UART_C: UART_C_CONTROL[27] and [28] must be set to 1. ● UART_AO: AO_UART_CONTROL[27] and [28] must be set to 1.For more details and other register setup, please refer to the Register Descriptions section.Di s t ri bu t et oE md o o r!6. Power ManagementThe UARTs in AML8726-MX can be shut down to save power consumption by using the register bits described below:Need verify● UART_A: i n EE domain; ● UART_B: i n EE domain; ● UART_C: in EE domain; ● UART_AO: in AO domain;Setting these bits to 0 will disable the UARTs function blocks and 1 will enable them. After system power-on or reset, UART modules are enabled on default.7. ResetFor the UART module in the AO power domain, it is possible to reset it by programming the register bit 0x0010[17] which is also in AO domain. Setting this bit to 1 will reset the I2C AO function blocks.Note: The receivers and transmitters of UARTs are disabled after system power-on or reset. Therefore software must program the registers to enable them, e.g., bit 12 and 13 in the corresponding control register should be set to 1.Di s t ri bu t et oE md oo r!8. Baud RateA build-in baud rate generator is implemented in AML8726-MX for each UART interface. The generator contains an input clock, a divider circuits and control registers.8.1. Input ClockThe input clock of the generator, named as UART_Clock, is configurable. The exact value of UART_Clock is based on AML8726-MX system software implementation.In Amlogic Android/Linux porting for AML8726-MX, the value of UART_Clock can be obtained by using the following process in software.1. Include clkdev.h at [linux_kernel_root]/arch/arm/include/asm/.2. Include clock.h at [linux_kernel_root]/arch/arm/mach-meson/include/mach/.3. Define a variable type struct clk.4. Define an unsigned int type variable uart_clock_rate.5. Use API clk_get_sys(“clk81”, NULL) to get clock structure.6. Use API clk_get_rate() to get the value of UART_Clock.The sample code is illustrated as below:#include <linux/clk.h> #include <asm/clkdev.h> #include <mach/clock.h>unsigned int uart_clock_rate; struct clk *uart_clockuart_clock = clk_get_sys(“clk81”, NULL); uart_clock_rate = clk_get_rate(uart_clock);8.2. Baud Rate GenerationAfter obtaining the uart_clock_rate, software can use the equation as shown below to generate correct baud rate.● UART_A:oror● UART_B:oror● UART_C:oror● UART_AO:ororDi s t ri bu t et oE md o o r!9. Register DescriptionsThese are 6 registers are defined and implemented in AML8726-MX for each UART. They are all 32-bit.9.1. UART_AWrite Buffer Register (UART_A_WFIFO)UART_A_WFIFO is the data entry of UART_A transmit FIFO. Writing to the register puts a byte data into the top of transmit FIFO. The data at the front of the FIFO transmits automatically until transmit FIFO empty.Table 4. UART_A_WFIFO register definitionName UART_A_WFIFO Offset 0x2130 Width 32-bit Bit R/W Name Default Description 31:8 R - 0 Reserved 7:0 W FIFO_WDATA - Write UART Transmit FIFO. The Write FIFO holds 64 bytesRead Buffer Register (UART_A_RFIFO)UART_A_RFIFO is the data entry of UART Read FIFO. It latches the value of data byte at the front of UART Read FIFO.Table 5. UART_A_RFIFO register definitionName UART_A_RFIFO Offset 0x2131 Width 32-bit Bit R/W Name Default Description 31:8 R - 0 Reserved 7:0 R FIFO_RDATA 0x00 Read a byte from UART FIFO.Di s t ri bu t et oE md o o r!UART_A Mode Register (UART_A_CONTROL)UART_A_CONTROL is a control register.Table 6. UART_A_CONTROL register definitionName UART_A_CONTROL Offset 0x2132 Width 32-bit Bit R/W Name Default Description 31 R/W RTS_INV 0 Invert RTS signal. 0: RTS active LOW. 1: RTS active HIGH 30 R/W ERR_MASK_EN 0 Error Mask enable. 0: disable error mask. 1: enable error mask. 29 R/W CTS_INV 0 Invert CTS signal. 0: CTS active LOW 1: CTS active HIGH. 28 R/W UART_TX_INT_EN 0 Transmit byte interrupt enable. When enabled, an interrupt will begenerated whenever a byte is read from Transmit FIFO. 0: disable transmit byte interrupt 1: enable transmit byte interrupt27 R/W UART_RX_INT_EN 0 Receive byte interrupt enable. When enabled, an interrupt will begenerated whenever a byte is written to Read FIFO. 0: disable receive byte interrupt 1: enable receive byte interrupt26 R/W UART_TX_INV 0 Invert TX signal. 0: TX active HIGH. 1: TX active LOW 25 R/W UART_RX_INV 0 Invert RX signal. 0: RX active HIGH. 1: RX active LOW 24 R/W UART_CLR_ERR 0 Clear error. Writing 1 to this register bit clears error.Note: This bit does not clear to 0 automatically. Please set the bit to 0 after clearing error manually.23 R/W UART_RX_RST 0 Reset receive state machine. Writing 1 to this register bit resetsreceive state machine.22 R/W UART_TX_RST 0 Reset transmit state machine. Write 1 to this register bit resettransmit state machine.21:20 R/W UART_DATA_LEN 00 Character length of data.00: 8-bit 01: 7-bit 10: 6-bit 11: 5-bit19 R/W PARITY_EN 1 Parity enable bit. 0: disable parity bit. 1: enable parity bit 18 R/W PARITY_TYPE 0 Parity type bit. 0: even parity. 1: odd parity 17:16 R/W STOP_BIT_LEN 0 Stop bit length.00: 1 stop bit 01: 2 stop bit 10-11: reserved.15 R/W TWO_WIRE_EN 0 Two-wire mode enables. 0: four-wire mode. 1: Two-wire mode 14 - - 0 Reserved 13 R/W UART_RX_EN 0 Receive enable. 0: disable receive function. 1: enable receivefunction12 R/W UART_TX_EN 0 Transmit enable. 0: disable transmit function. 1: enabletransmit function11:0 R/W BAUD_RATE 0x120 Baud rate setup. Please refer to Baud Rate Generation Sectionfor detail.Di s t ri bu t et oE md o o r!UART_A Status Register (UART_A_STATUS)UART_A_STATUS is a read-only register to indicate the status of UART interface.Table 7. UART_A_STATUS register definition Name UART_A_STATUS Offset 0x2133Width 32-bit Bit R/W Name Default Description31:27 - - 0x00 Reserved26 R UART_RECV_BUSY 0 Receive state machine busy indicator. Being set to 1indicates receive state machine is busy25 R UART_XMIT_BUSY 0 Transmit state machine busy indicator. Being set to 1indicates transmit state machine is busy24 R RECV_FIFO_OVERFLOW 0 Receive FIFO overflow indicator. Being set to 1 indicatesreceive FIFO overflows23 R CTS_LEVEL 0 CTS signal level.22 R TX_FIFO_EMPTY 0 Transmit FIFO Empty indicator. Being set to 1 indicatesTransmit FIFO is empty21 R TX_FIFO_FULL 0 Transmit FIFO Full indicator. Being set to1 indicatesTransmit FIFO is full.20 R RX_FIFO_EMPTY 0 Receive FIFO Empty indicator. Being set to 1 indicatesReceive FIFO is empty19 R RX_FIFO_FULL 0 Receive FIFO Full indicator. Being set to 1 indicatesReceive FIFO is full.18 R TX_FIFO_WERR 0 Transmit FIFO writing error indicator. The bit is set to 1 ifwriting data to Transmit FIFO when Transmit FIFO is full.Note: Please use register UART_A_CONTROL bit 24 toclear this bit. Refer to UART_A_CONTROL registerdefinition.17 R FRAME_ERR 0 Frame Error indicator. The bit is set to 1 if frame errordetected.Note: Please use register UART_A_CONTROL bit 24 toclear this bit. Refer to UART_A_CONTROL registerdefinition.16 R PARITY_ERR 0 Parity Error indicator. The bit is set to 1 if parity errordetected.Note: Please use register UART_CONTROL bit 24 to clearthis bit. Refer to UART_A_CONTROL register definition.15 - - 0 Reserved14:8 R TX_FIFO_DCNT 0 Transmit FIFO data count. The value is the number ofbytes in the Transmit FIFO.7 R - 0 Reserved6:0 R RX_FIFO_DCNT 0 Receive FIFO data count. The value is the number ofbytes in the Receive FIFO.Di s t r i b u t e t o E m d o o r !UART_A Interrupt Control Register (UART_A_MISC)UART_A_MISC is the register to control UART related interrupt.Table 8. UART_A_MISC register definition Name UART_A_MISC Offset 0x2134Width 32-bit Bit R/W Name Default Description31 - - 0 Reserved30 R/W USE old Rx Baud 0 he Rx baud rate generator was re-designed to compute abaud rate correctly. If you want to use the old (stupid) logic,you can set this bit to 1.29 R/W ASYNC_FIFO_PURGE 0 Set to 1 after all UART bytes have been received in order topurge the data into the async FIFO28 R/W ASYNC_FIFO_EN 0 Automatically send to async FIFO module enable1: enable automatic sending0:disable automatic sending27 R/W CTS_FIL_TB_SEL 0 CTS input filter time base selection.A digital signal filter can be used to filter the UART CTS signalinput.The filter has two parameters, the time base and the numberof time base.0: The time base is 111nS.1: The time base is 1uS.26-24 R/W CTS_FIL_SEL 0 CTS input filter times000: No filter.…111: Maximum filter time. The time is 7x 111= 777nS(CTS_FIL_TB_SEL = 0) or 7x 1=7uS (CTS_FIL_TB_SEL = 1)23-20 R/W BAUD_RATE_EXT 0 Extend the baud rate divider to 16-bits together withUART_A_STATUS[11:0]Baud_Rate = {Reg4[23:20],Reg2[11:0]}19 R/W RX_FIL_TB_SEL 0 RX input filter time base selection.A digital signal filter can be used to filter the UART RX signalinput.The filter has two parameters, the time base and the times oftime base.0: The time base is 111nS.1: The time base is 1uS.18:16 R/W RX_FIL_SEL 0 RX input filter times000: No filter.…111: Maximum filter time. The time is 7x 111= 777nS(RX_FIL_TB_SEL = 0) or 7x 1=7uS (RX_FIL_TB_SEL = 1)15:8 R/W XMIT_IRQ_CNT 32 Transmit FIFO threshold.UART generates an interrupt when the number of bytes inTransmit FIFO is below the value of these bits.7:0 R/W RECV_IRQ_CNT 15 Receive FIFO threshold.UART generates an interrupt when the number bytes inReceive FIFO is large than the value of these bits.Di s t ri b u t e t o E m d o o r !UART_A_REG5Table 9. UART_A_REG5 register definition Name UART_A_REG5 Offset 0x2135Width 32-bit Bit R/W Name Default Description31-24 R/W - 0 unused23 R/W USE New Baud rate. 0 Over the years, the baud rate has been extended byconcatenating bits from different registers. To takeadvantage of the full 23-bit baud rate generate (extended to23 bits to accommodate very low baud rates), you must setthis bit. If this bit is set, then the baud rate is configuredusing bits [22:0] below22:0 R/W NEW_BAUD_RATE: 0 If bit[23] = 1 above, then the baud rate for the UART iscomputed using these bits. This was added in MX toaccommodate lower baud rates.Di s t r i b u t e t o E m d o o r !9.2. UART_BWrite Buffer Register (UART_B_WFIFO)UART_B_WFIFO is the data entry of UART_B transmit FIFO. Writing to the register puts a byte data into the top of transmit FIFO. The data at the front of the FIFO transmits automatically until transmit FIFO empty.Table 10. UART_B_WFIFO register definition Name UART_B_WFIFO Offset 0x2137 Width 32-bitBit R/W Name Default Description31:8 R - 0 Reserved7:0 W FIFO_WDATA - Write UART Transmit FIFO.Read Buffer Register (UART_B_RFIFO)UART_B_RFIFO is the data entry of UART Read FIFO. It latches the value of data byte at the front of UART Read FIFO. Table 9. UART_B_RFIFO register definition Name UART_B_RFIFO Offset 0x2138 Width 32-bit Bit R/W Name Default Description 31:8 R - 0 Reserved 7:0 R FIFO_RDATA 0x00 Read a byte from UART FIFO.Di s t r i b u t e t o E m d o o r !UART_B Mode Register (UART_B_CONTROL)UART_B_CONTROL is a control register.Table 10. UART_B_CONTROL register definition Name UART_B_CONTROL Offset 0x2139Width 32-bit Bit R/W Name Default Description31 R/W RTS_INV 0 Invert RTS signal. 0: RTS active LOW. 1: RTS active HIGH30 R/W ERR_MASK_EN 0 Error Mask enable. 0: disable error mask. 1: enable error mask. 29 R/W CTS_INV 0 Invert CTS signal. 0: CTS active LOW 1: CTS active HIGH.28 R/W UART_TX_INT_EN 0 Transmit byte interrupt enable. When enabled, an interrupt will begenerated whenever a byte is read from Transmit FIFO.0: disable transmit byte interrupt1: enable transmit byte interrupt27 R/W UART_RX_INT_EN 0 Receive byte interrupt enable. When enabled, an interrupt will begenerated whenever a byte is written to Read FIFO.0: disable receive byte interrupt1: enable receive byte interrupt26 R/W UART_TX_INV 0 Invert TX signal. 0: TX active HIGH. 1: TX active LOW 25 R/W UART_RX_INV 0 Invert RX signal. 0: RX active HIGH. 1: RX active LOW 24 R/W UART_CLR_ERR 0 Clear error. Writing 1 to this register bit clears error.Note: This bit does not clear to 0 automatically. Please set the bitto 0 after clearing error manually.23 R/W UART_RX_RST 0 Reset receive state machine. Writing 1 to this register bit resetsreceive state machine.22 R/W UART_TX_RST 0 Reset transmit state machine. Write 1 to this register bit resettransmit state machine.21:20 R/W UART_DATA_LEN 00 Character length of data.00: 8-bit01: 7-bit10: 6-bit11: 5-bit19 R/W PARITY_EN 1 Parity enable bit. 0: disable parity bit. 1: enable parity bit 18 R/W PARITY_TYPE 0 Parity type bit. 0: even parity. 1: odd parity17:16 R/W STOP_BIT_LEN 0 Stop bit length.00: 1 stop bit01: 2 stop bit10-11: reserved.15 R/W TWO_WIRE_EN 0 Two-wire mode enables. 0: four-wire mode. 1: Two-wire mode 14 - - 0 Reserved13 R/W UART_RX_EN 0 Receive enable. 0: disable receive function. 1: enable receivefunction12 R/W UART_TX_EN 0 Transmit enable. 0: disable transmit function. 1: enabletransmit function11:0 R/W BAUD_RATE 0x120 Baud rate setup. Please refer to Baud Rate Generation Sectionfor detail.D i s t ri b u t e t o E m d o o r !UART_B Status Register (UART_STATUS)UART_B_STATUS is a read-only register to indicate the status of UART interface.Table 13. UART_B_STATUS register definition Name UART_B_STATUS Offset 0x213AWidth 32-bit Bit R/W Name Default Description31:27 - - 0x00 Reserved26 R UART_RECV_BUSY 0 Receive state machine busy indicator. Being set to 1indicates receive state machine is busy25 R UART_XMIT_BUSY 0 Transmit state machine busy indicator. Being set to 1indicates transmit state machine is busy24 R RECV_FIFO_OVERFLOW 0 Receive FIFO overflow indicator. Being set to 1 indicatesreceive FIFO overflows23 R CTS_LEVEL 0 CTS signal level.22 R TX_FIFO_EMPTY 0 Transmit FIFO Empty indicator. Being set to 1 indicatesTransmit FIFO is empty21 R TX_FIFO_FULL 0 Transmit FIFO Full indicator. Being set to1 indicatesTransmit FIFO is full.20 R RX_FIFO_EMPTY 0 Receive FIFO Empty indicator. Being set to 1 indicatesReceive FIFO is empty19 R RX_FIFO_FULL 0 Receive FIFO Full indicator. Being set to 1 indicatesReceive FIFO is full.18 R TX_FIFO_WERR 0 Transmit FIFO writing error indicator. The bit is set to 1 ifwriting data to Transmit FIFO when Transmit FIFO is full.Note: Please use register UART_B_CONTROL bit 24 toclear this bit. Refer to UART_B_CONTROL registerdefinition.17 R FRAME_ERR 0 Frame Error indicator. The bit is set to 1if frame errordetected.Note: Please use register UART_B_CONTROL bit 24 toclear this bit. Refer to UART_B_CONTROL registerdefinition.16 R PARITY_ERR 0 Parity Error indicator. The bit is set to 1 if parity errordetected.Note: Please use register UART_CONTROL bit 24 to clearthis bit. Refer to UART_B_CONTROL register definition.15 - - 0 Reserved14:8 R TX_FIFO_DCNT 0 Transmit FIFO data count. The value is the number ofbytes in the Transmit FIFO.7 R - 0 Reserved6:0 R RX_FIFO_DCNT 0 Receive FIFO data count. The value is the number ofbytes in the Receive FIFO.Di s t r i b u t e t o E m d o o r !UART_B Interrupt Control Register (UART_B_MISC)UART_B_MISC is the register to control UART related interrupt.Table 11. UART_B_MISC register definition Name UART_B_MISC Offset 0x213BWidth 32-bit Bit R/W Name Default Description31 - - 0 Reserved30 R/W USE old Rx Baud 0 he Rx baud rate generator was re-designed to compute abaud rate correctly. If you want to use the old (stupid) logic,you can set this bit to 1.29 R/W ASYNC_FIFO_PURGE 0 Set to 1 after all UART bytes have been received in order topurge the data into the async FIFO28 R/W ASYNC_FIFO_EN 0 Automatically send to async FIFO module enable1: enable automatic sending0:disable automatic sending27 R/W CTS_FIL_TB_SEL 0 CTS input filter time base selection.A digital signal filter can be used to filter the UART CTS signalinput.The filter has two parameters, the time base and the numberof time base.0: The time base is 111nS.1: The time base is 1uS.26-24 R/W CTS_FIL_SEL 0 CTS input filter times000: No filter.…111: Maximum filter time. The time is 7x 111= 777nS(CTS_FIL_TB_SEL = 0) or 7x 1=7uS (CTS_FIL_TB_SEL = 1)23-20 R/W BAUD_RATE_EXT 0 Extend the baud rate divider to 16-bits together withUART_B_STATUS[11:0]Baud_Rate = [BAUD_RATE_EXT: BAUD_RATE]19 R/W RX_FIL_TB_SEL 0 RX input filter time base selection.A digital signal filter can be used to filter the UART RX signalinput.The filter has two parameters, the time base and the times oftime base.0: The time base is 111nS.1: The time base is 1uS.18:16 R/W RX_FIL_SEL 0 RX input filter times000: No filter.…111: Maximum filter time. The time is 7x 111= 777nS(RX_FIL_TB_SEL = 0) or 7x 1=7uS (RX_FIL_TB_SEL = 1)15:8 R/W XMIT_IRQ_CNT 32 Transmit FIFO threshold.UART generates an interrupt when the number of bytes inTransmit FIFO is below the value of these bits.7:0 R/W RECV_IRQ_CNT 15 Receive FIFO threshold.UART generates an interrupt when the number bytes inReceive FIFO is large than the value of these bits.Di s t r i b u t e t o E m d o o r !。

IR6216;IR6216S;中文规格书,Datasheet资料

Max. Units Test Conditions
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o
C
o
C/W
Lead Assignments
3 (Vcc) 3 (Vcc) 1 2 3 4 5 - Ground - In - Vcc - DG - Out
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12345
5 Lead - TO-220 IR6216 Part Number
The IR6216 is a 5 terminal monolithic HIGH SIDE SWITCH with built in short circuit, over- temperature, ESD protections, inductive load turn off capability and diagnostic feedback. The on-chip protection circuit limits the average current during short circuit if the drain current exceeds 10A. The protection circuit latches off the high side switch if the junction temperature exceeds 170oC and latches on after the junction temperature falls by 10oC. The Vcc (drain) to out (source) voltage is actively clamped at 55V, improving its performance during turn off with inductive loads. The on-chip charge pump high side driver stage is floating and referenced to the source of the Power MOSFET. Thus the logic to power ground isolation can be as high as 50V. This allows operation with larger offset as well as controlling the switch during load energy recirculation or regeneration. A diagnostic pin is provided for status feedback of short circuit, over temperature and open load detection.

EG8026芯片数据手册说明书

版本变更记录版本号日期描述V1.0 2022年01月20日EG8026数据手册初稿。

目录目录 (3)1.特点 (5)2.描述 (6)3.应用领域 (6)4.引脚 (7)4.1QFN70封装引脚定义 (7)4.2LQFP80封装引脚定义 (8)4.3引脚描述 (9)5.结构框图 (12)6.典型应用电路 (13)6.1EG8026 QFN70封装应用原理图 (13)6.2EG8026 LQFP80封装应用原理图 (14)6.348V/2KW双向逆变器主板应用图 (15)6.4EG1615 DC/DC控制板原理图 (16)7.电气特性 (17)7.1极限参数 (17)7.2典型参数 (18)8.应用设计 (20)8.1双向逆变器的主拓扑结构 (20)8.2EG8026实现的传统型Boost无桥PFC结构 (21)8.3EG8026实现的DC/AC Inverter结构 (22)8.4PFC和DC/AC Inverter、UPS功能切换 (23)8.5PWM调制方式 (23)8.6输出电压反馈 (24)8.7输出电流反馈 (26)8.8温度反馈 (27)8.9直流母线电压反馈和硬件过压保护 (27)8.10死区时间 (28)8.11H桥的左、右桥臂互换控制 (29)9.保护功能 (30)9.1输出过载保护 (30)9.2输出过流保护 (30)9.3直流母线电压过压保护 (30)9.4PCB过温保护 (30)9.5功率管过温保护 (30)9.6短路保护 (30)9.7MOS管峰值电流保护 (31)10.测试模式 (32)11.通讯功能（UART） (33)11.1串口描述 (33)11.2APP功能 (33)屹晶微电子有限公司11.2.1APP消息发送 (33)11.2.2APP消息接收 (34)11.3CFG功能 (36)11.3.1CFG请求消息 (36)11.3.2CFG应答消息 (36)11.3.30x10服务-会话切换 (37)11.3.40x22服务-读DID (38)11.3.50x2E服务-写DID (38)11.3.60x21 服务-读CFG (39)11.3.70x2D 服务-写CFG (39)11.3.80x2F服务-IO控制 (40)12.封装尺寸 (41)12.1LQFP80 (41)12.2QFN70 (42)屹晶微电子有限公司EG8026芯片数据手册V1.01. 特点集成了DC/AC逆变器和PFC升压两大功能支持UPS功能作逆变器DC/AC时的功能：⏹采用电流模式、中心对齐PWM调制方式，能带感性和容性负载⏹SPWM载波频率20KHz，适合大功率MOS管和IGBT管的应用⏹集成了两路600V半桥高压MOS管驱动器，驱动能力为±2A⏹集成四路独立的MOS管峰值电流保护电路及内置四路200mV基准源的比较器供用户设定保护值⏹集成了四路高速运放及一路高速比较器，两路运放用于交流电流放大器，一路运放用于交流输出电压反馈，一路运放用于短路保护和一路比较器用于限流保护⏹输出电压和输出电流是每个PWM周期实时处理，能实现精确跟踪⏹引脚可配置功能：●H桥左、右桥臂互换控制●4种死区时间可选配置: 300nS、500nS、1uS、1.5uS●2种固定正弦波频率可选配置：50Hz、60Hz●软启动开启和关闭⏹逆变器保护功能：●直流母线电压过压保护●交流输出欠压保护●输出过载保护●输出过流保护●PCB过温保护和IGBT过温保护●输出短路保护⏹串口通讯可设置参数：●50Hz纯正弦波固定频率●60Hz纯正弦波固定频率●交流输出电压●温度保护值●额定功率保护值●额定电流保护值●故障复位⏹串口通讯可读参数：●交流输出电压●交流输出频率●交流输出功率●交流输出电流●直流母线电压●故障代码作PFC升压时的功能：⏹采用传统型Boost无桥PFC结构，平均电流控制算法⏹SPWM载波频率20KHz，适合大功率MOS管和IGBT管的应用⏹升压输出电压由恒功率大小进行自动调节，正常电压为400V，可调电压范围为330V到450V⏹外部可设的硬件输出过压保护⏹交流输入电压欠压保护⏹输出过载和过流保护⏹支持UART串口通讯，实现跟前级DC/DC EG1615芯片进行通讯，读取充电电压和电流等信息⏹PF值可达0.98以上2. 描述EG8026芯片是一款专用于双向逆变器（同一套电路可作逆变器功能，又可作电池充电器功能）中的DC/AC逆变和PFC升压的控制芯片，集成了两路600V半桥高压MOS驱动器，驱动器的输出电流能力为+/-2A，内置四路独立的逐周PWM关断保护，可有效防止在极端情况下过高的峰值电流而损坏MOS的情况，另外提供了两路SD，分别为SD1，和SD2，SD1是驱动器1 HO1和LO1的逐周关断引脚，SD2是驱动器2 HO2和LO2的逐周关断引脚，结合外部比较器和SD功能可实现过流或短路保护等功能。

itr8402光电开关规格书

【itr8402光电开关规格书】一、产品概述itr8402光电开关是一种常见的传感器设备，主要用于检测物体的存在或运动。

它通常由发射器和接收器两部分组成，通过光学原理实现对目标物体的检测。

itr8402光电开关具有高精度、稳定性好、响应速度快等特点，广泛应用于工业自动化生产线等领域。

二、产品规格1. 工作原理：光电传感器2. 工作电压：DC 5V-24V3. 响应时间：≤1ms4. 最大探测距离：10m5. 工作温度：-25℃~+70℃6. 输出类型：NPN/PNP7. 输出状态：常开/常闭8. 外壳材质：金属/塑料9. 防护等级：IP6510. 安装方式：螺纹/法兰/夹紧三、产品特点1. 高精度：itr8402光电开关采用先进的光电传感技术，能够精准快速地检测目标物体，确保生产线运行的稳定性和效率。

2. 稳定性好：经过精密的工艺制造，具有良好的防尘、防水性能，能够在恶劣环境下长时间稳定工作。

3. 响应速度快：响应时间快，能够及时准确地感知目标物体的运动状态，实现精确的控制。

4. 多种输出类型：支持NPN和PNP两种输出类型，可根据实际需求选择常开或常闭输出状态，灵活适应不同的工作场景。

5. 多种安装方式：可选用螺纹、法兰或夹紧等多种安装方式，方便安装和维护。

四、适用领域itr8402光电开关适用于各种工业自动化生产线，包括但不限于机械设备、包装生产线、输送带系统等领域。

可以实现对物体的准确探测和位置识别，广泛应用于自动化控制、物料检测、计数器等功能。

五、注意事项1. 安装时请确保光电开关与目标物体之间无遮挡物，以免影响探测效果。

2. 使用过程中应定期清洁光电开关的感应窗口，避免灰尘和污物影响传感效果。

3. 请根据实际需求选择合适的输出类型和安装方式，以确保光电开关的稳定工作和准确探测。

六、结语itr8402光电开关是一款性能稳定、功能全面的光电传感器，具有高精度、响应速度快等优点，广泛应用于各种工业自动化生产线。

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Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1000
10000
TJ = 175°C
ISD , Reverse Drain Current (A)
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS(on)
:
Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current l Lead-Free l RoHS compliant
G
D
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature

A 340 1.0 36 78 V ns nC
Ã
e
2
e

IRLR/U8726PbF
1000
TOP
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
VGS 10V 5.0V 4.5V 3.5V 3.3V 3.0V 2.7V 2.5V
Conditions
VGS = 0V, ID = 250µA
mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 25A VGS = 4.5V, ID = 20A
e e
VDS = VGS, ID = 50µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C VGS = 20V VGS = -20V VDS = 15V, ID = 20A
See Fig. 15 VDS = 15V, VGS = 0V VDD = 15V, VGS = 4.5V
e
See Fig. 13 VGS = 0V VDS = 15V ƒ = 1.0MHz Max. 120 20 Units mJ A
Avalanche Characteristics
EAS IAR
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical ቤተ መጻሕፍቲ ባይዱutput Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
TOP
100
BOTTOM
VGS 10V 5.0V 4.5V 3.5V 3.3V 3.0V 2.7V 2.5V
10
10
1
≤ 60µs PULSE WIDTH Tj = 25°C 2.5V
2.5V ≤ 60µs PULSE WIDTH Tj = 175°C
1 0.1 1 10 100
0.1 0.1 1 10 100
3
IRLR/U8726PbF
10000
VGS, Gate-to-Source Voltage (V)
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
12 10 8 6 4 2 0
ID= 20A VDS= 24V VDS= 15V
Ã
d
Diode Characteristics
Parameter
IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
S G D
S
D-Pak IRLR8726PbF G D
I-Pak IRLU8726PbF S
Gate
Drain
Max.
30 ± 20 86 61
Source
Units
V
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
C, Capacitance (pF)
Ciss
1000
Coss
Crss
100 1 10 100
0
4
8
12 16 20 24 28 32 36 40
VDS , Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Min. Typ. Max. Units
30 ––– ––– ––– 1.35 ––– ––– ––– ––– ––– 73 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 20 4.0 5.8 1.80 -8.6 ––– ––– ––– ––– ––– 15 3.7 1.9 5.7 3.7 7.6 10 2.0 12 49 15 16 2150 480 205 ––– ––– 5.8 8.0 2.35 ––– 1.0 150 100 -100 ––– 23 ––– ––– ––– ––– ––– ––– 3.5 ––– ––– ––– ––– ––– ––– ––– Typ. ––– ––– pF ns nC Ω ID = 20A RG = 1.8Ω nC VDS = 15V VGS = 4.5V ID = 20A S nA V mV/°C µA V
ID, Drain-to-Source Current (A)
ID = 25A VGS = 10V
1.5
100
10
TJ = 175°C TJ = 25°C
1
1.0
VDS = 15V
0.1 0.0 2.0 4.0
≤ 60µs PULSE WIDTH
6.0 8.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

1
11/23/09
IRLR/U8726PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS ∆ΒVDSS/∆TJ RDS(on) VGS(th) ∆VGS(th)/∆TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss RG td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Parameter Single Pulse Avalanche Energy Avalanche Current
h
ghÃ
––– ––– –––
Notes through are on page 11
ORDERING INFORMATION: See detailed ordering and shipping information on the last page of this data sheet.