74F646BSDMSACX中文资料

TL F 958054F 74F646 74F646B 54F 74F648 Octal Transceiver Register with TRI-STATE OutputsDecember1994 54F 74F646 74F646B 54F 74F648Octal Transceiver Register with TRI-STATE Outputs General DescriptionThese devices consist of bus transceiver circuits with TRI-STATE D-type flip-flops and control circuitry arranged formultiplexed transmission of data directly from the input busor from the internal registers Data on the A or B bus will beclocked into the registers as the appropriate clock pin goesto a high logic level Control G and direction pins are provid-ed to control the transceiver function In the transceivermode data present at the high impedance port may bestored in either the A or the B register or in both The selectcontrols can multiplex stored and real-time(transparentmode)data The direction control determines which bus willreceive data when the enable control G is Active LOW Inthe isolation mode(control G HIGH) A data may be storedin the B register and or B data may be stored in the A regis-terFeaturesY Independent registers for A and B busesY Multiplexed real-time and stored dataY’F648has inverting data pathsY’F646 ’F646B have non-inverting data pathsY’F646B is a faster version of the’F646Y TRI-STATE outputsY300mil slim DIPY Guaranteed4000V minimum ESD protection Commercial MilitaryPackagePackage DescriptionNumber74F646SPC N24C24-Lead(0 300 Wide)Molded Dual-In-Line54F646DM(Note2)J24F24-Lead(0 300 Wide)Ceramic Dual-In-Line 74F646SC(Note1)M24B24-Lead(0 300 Wide)Molded Small Outline JEDEC 74F646MSA(Note1)MSA2424-Lead Molded Shrink Small Outline EIAJ Type II54F646FM(Note2)W24C24-Lead Cerpack54F646LM(Note2)E28A28-Lead Ceramic Leadless Chip Carrier Type C 74F646BSPC N24C24-Lead(0 300 Wide)Molded Dual-In-Line74F646BSC(Note1)M24B24-Lead(0 300 Wide)Molded Small Outline JEDEC 74F648SPC N24C24-Lead(0 300 Wide)Molded Dual-In-Line54F648SDM(Note2)J24F24-Lead(0 300 Wide)Ceramic Dual-In-Line 74F648SC(Note1)M24B24-Lead(0 300 Wide)Molded Small Outline JEDEC54F648FM(Note2)W24C24-Lead Cerpack54F648LM(Note2)E28A24-Lead Ceramic Leadless Chip Carrier Type C Note1 Devices also available in13 reel Use suffix e SCXNote2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQBLogic Symbols’F646 ’F646BTL F 9580–1’F648TL F 9580–7 TRI-STATE is a registered trademark of National Semiconductor CorporationC1995National Semiconductor Corporation RRD-B30M75 Printed in U S ALogic Symbols(Continued)IEEE IEC’F646 ’F646BTL F 9580–4IEEE IEC’F648TL F 9580–9Connection DiagramsPin Assignmentfor DIP SOIC and Flatpak’F646 ’F646BTL F 9580–2 Pin Assignmentfor LCC’F646 ’F646BTL F 9580–3Pin Assignmentfor DIP SOIC and Flatpak’F648TL F 9580–8Pin Assignmentfor LCC’F648TL F 9580–10 2Unit Loading Fan Out54F 74FPin Names Description U L Input IIH I ILHIGH LOW Output I OH I OLA0–A7Data Register A Inputs 3 5 1 08370m A b650m ATRI-STATE Outputs600 106 6(80)b12mA 64mA(48mA)B0–B7Data Register B Inputs 3 5 1 08370m A b650m ATRI-STATE Outputs600 106 6(80)b12mA 64mA(48mA)CPAB CPBA Clock Pulse Inputs1 0 1 020m A b0 6mASAB SBA Select Inputs1 0 1 020m A b0 6mAG Output Enable Input1 0 1 020m A b0 6mADIR Direction Control Input1 0 1 020m A b0 6mAFunction TableInputs Data I OFunctionG DIR CPAB CPBA SAB SBA A0–A7B0–B7H X H or L H or L X X IsolationH X L X X X Input Input Clock A n Data into A RegisterH X X L X X Clock B n Data into B RegisterL H X X L X A n to B n Real Time(Transparent Mode)L H L X L XInput Output Clock A n Data into A RegisterL H H or L X H X A Register to B n(Stored Mode)L H L X H X Clock A n Data into A Register and Output to B n L L X X X L B n to A n Real Time(Transparent Mode)L L X L X LOutput Input Clock B n Data into B RegisterL L X H or L X H B Register to A n(Stored Mode)L L X L X H Clock B n Data into B Register and Output to A n The data output functions may be enabled or disabled by various signals at the G and DIR Inputs Data input functions are always enabled i e data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputsH e HIGH Voltage LevelL e LOW Voltage LevelX e IrrelevantL e LOW-to-HIGH Transition3Logic Diagrams(Continued)’F646 ’F646BTL F 9580–5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays4Logic Diagrams(Continued)’F648TL F 9580–6 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays5Absolute Maximum Ratings(Note1)If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature b65 C to a150 CAmbient Temperature under Bias b55 C to a125 CJunction Temperature under Bias b55 C to a175 C Plastic b55 C to a150 CV CC Pin Potential toGround Pin b0 5V to a7 0V Input Voltage(Note2)b0 5V to a7 0V Input Current(Note2)b30mA to a5 0mA Voltage Applied to Outputin HIGH State(with V CC e0V)Standard Output b0 5V to V CC TRI-STATE Output b0 5V to a5 5V Current Applied to Outputin LOW State(Max)twice the rated I OL(mA) ESD Last Passing Voltage(Min)4000V Note1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not impliedNote2 Either voltage limit or current limit is sufficient to protect inputs Recommended Operating ConditionsFree Air Ambient TemperatureMilitary b55 C to a125 C Commercial0 C to a70 C Supply VoltageMilitary a4 5V to a5 5V Commercial a4 5V to a5 5VDC Electrical CharacteristicsSymbol Parameter54F 74FUnits V CC Conditions Min Typ MaxV IH Input HIGH Voltage2 0V Recognized as a HIGH Signal V IL Input LOW Voltage0 8V Recognized as a LOW Signal V CD Input Clamp Diode Voltage b1 2V Min I IN e b18mA(Non I O Pins)V OH Output HIGH54F10%V CC2 0V Min I OH e b12mA(A n B n)Voltage74F10%V CC2 0I OH e b15mA(A n B n)V OL Output LOW54F10%V CC0 55V Min I OL e48mA(A n B n)Voltage74F10%V CC0 55I OL e64mA(A n B n)I IH Input HIGH54F20 0m A Max V IN e2 7V(Non I O Pins)Current74F5 0I BVI Input HIGH Current54F100m A Max V IN e7 0V(Non I O Pins)Breakdown Test74F7 0I BVIT Input HIGH Current54F1 0mA Max V IN e5 5V(A n B n)Breakdown(I O)74F0 5I CEX Output HIGH54F250m A Max V OUT e V CCLeakage Current74F50V ID Input Leakage74F4 75V0 0I ID e1 9m ATest All Other Pins GroundedI OD Output Leakage74F3 75m A0 0V IOD e150mVCircuit Current All Other Pins Grounded I IL Input LOW Current b0 6mA Max V IN e0 5V(Non I O Pins) I IH a I OZH Output Leakage Current70m A Max V OUT e2 7V(A n B n)I IL a I OZL Output Leakage Current b650m A Max V OUT e0 5V(A n B n)I OS Output Short-Circuit Current b100b225mA Max V OUT e0VI ZZ Bus Drainage Test500m A0 0V V OUT e5 25VI CCH Power Supply Current135mA Max V O e HIGHI CCL Power Supply Current150mA Max V O e LOWI CCZ Power Supply Current150mA Max V O e HIGH Z6’F646 ’F648AC Electrical Characteristics74F54F74FT A e a25 CT A V CC e Mil T A V CC e Com Symbol Parameter V CC e a5 0VC L e50pF C L e50pF UnitsC L e50pFMin Max Min Max Min Maxf max Maximum Clock Frequency907590MHzt PLH Propagation Delay2 07 02 08 52 08 0ns t PHL Clock to Bus2 08 02 09 52 09 0t PLH Propagation Delay1 07 01 08 01 07 5ns t PHL Bus to Bus(’F646)1 06 51 08 01 07 0t PLH Propagation Delay2 08 51 010 02 09 0ns t PHL Bus to Bus(’F648)1 07 51 09 01 08 0t PLH Propagation Delay2 08 52 011 02 09 5ns t PHL SBA or SAB to A or B2 08 02 010 02 09 0t PZH Enable Time2 08 52 010 02 09 0ns t PZL OE to A or B2 012 02 013 52 012 5t PHZ Disable Time1 07 51 09 01 08 5ns t PLZ OE to A or B2 09 02 011 02 09 5t PZH Enable Time2 014 02 016 02 015 0ns t PZL DIR to A or B2 013 02 015 02 014 0t PHZ Disable Time1 09 01 010 01 09 5ns t PLZ DIR to A or B2 011 02 012 02 011 5’F646 ’F648AC Operating Requirements74F54F74FSymbol ParameterT A e a25 CT A V CC e Mil T A V CC e Com Units V CC e a5 0VMin Max Min Max Min Maxt s(H)Setup Time HIGH or LOW5 05 05 0ns t s(L)Bus to Clock5 05 05 0t h(H)Hold Time HIGH or LOW2 02 52 0ns t h(L)Bus to Clock2 02 52 0t w(H)Clock Pulse Width5 05 05 0ns t w(L)HIGH or LOW5 05 05 07’F646BAC Electrical Characteristics74F54F74FT A e a25 CT A V CC e Mil T A V CC e Com Symbol Parameter V CC e a5 0VC L e50pF C L e50pF UnitsC L e50pFMin Max Min Max Min Maxf max Maximum Clock Frequency165150MHzt PLH Propagation Delay2 57 02 58 0ns t PHL Clock to Bus3 07 53 08 0t PLH Propagation Delay2 06 02 07 0ns t PHL Bus to Bus2 06 02 07 0t PLH Propagation Delay2 57 52 58 5ns t PHL SBA or SAB to A or B2 57 52 58 5t PZH Enable Time2 56 52 58 0ns t PZL OE to A or B2 59 02 510 0t PHZ Disable Time1 56 51 57 5ns t PLZ OE to A or B2 07 02 08 5t PZH Enable Time2 07 02 08 5ns t PZL DIR to A or B3 09 53 010 0t PHZ Disable Time1 57 51 58 5ns t PLZ DIR to A or B2 58 52 59 5’F646BAC Operating Requirements74F54F74FSymbol ParameterT A e a25 CT A V CC e Mil T A V CC e Com Units V CC e a5 0VMin Max Min Max Min Maxt s(H)Setup Time HIGH or LOW5 04 0ns t s(L)Bus to Clock5 04 0t h(H)Hold Time HIGH or LOW1 51 5ns t h(L)Bus to Clock1 51 5t w(H)Clock Pulse Width5 05 0ns t w(L)HIGH or LOW5 05 0Ordering InformationThe device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows74F646 646B 648S C XTemperature Range Family Special Variations74F e Commercial QB e Military grade device with54F e Military environmental and burn-inprocessing Device Type X e Devices shipped in13 reelPackage Code Temperature RangeSP e Slim Plastic DIP C e CommercialSD e Slim Ceramic DIP(0 C to a70 C)S e Small Outline(SOIC)M e MilitaryMSA e Shrink Small Outline SOIC EIAJ Type II(M646only)(b55 C to a125 C) L e Leadless Chip CarrierF e Flatpak8Physical Dimensions inches(millimeters)28-Lead Ceramic Leadless Chip Carrier Type CNS Package Number E28A24-Lead(0 300 Wide)Ceramic Dual-In-Line Package(SD)NS Package Number J24F9Physical Dimensions inches(millimeters)(Continued)24-Lead(0 300 Wide)Molded Small Outline Package JEDEC(S)NS Package Number M24B10Physical Dimensions inches(millimeters)(Continued)24-Lead Molded Shrink Small Outline Package EIAJ Type IINS Package Number MSA2424-Lead(0 300 Wide)Molded Dual-In-Line Package(SP)NS Package Number N24C1154F 74F 646 74F 646B 54F 74F 648O c t a l T r a n s c e i v e r R e g i s t e r w i t h T R I -S T A T E O u t p u t s Physical Dimensions inches (millimeters)(Continued)24-Lead Cerpack NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which (a)are intended for surgical implant support device or system whose failure to perform can into the body or (b)support or sustain life and whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor CorporationGmbH Japan Ltd Hong Kong Ltd Do Brazil Ltda (Australia)Pty Ltd 2900Semiconductor Drive Livry-Gargan-Str 10Sumitomo Chemical 13th Floor Straight Block Rue Deputado Lacorda Franco Building 16。