8-Alchip_STA_flow

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TSMC 0.18um Electrical Parameters (6LM)
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M1, M2, M3, M4, M5 = 0.101 Ω/ ; M6 = 0.045 Ω/ V1, V2, V3, V4 = 20 Ω; V5 = 13 Ω Cm-m ~= 0.2 fF/um (intra-metal, m1 thru m5, minimum pitch) For a 1000um M1 thru M5 net with 50 Vias, worst case RC ~= (50)(20)*(1000)(0.2) ~= 200 ps
M1, M3, M5 run horizontally (row direction) l M2, M4, M6 run vertically (column direction)
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M1 is almost 100% used within the std cells M2-M6 are the main routing layers M5 & M6 are used mainly for Vdd/Vss M6 is used for main clock trunk with M3 as fish-bone tributaries
Cell output rising edge rate table (in ns)
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Basic STA Concepts -2
n Fundamentals - 2
STA – What are we checking?
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Setup
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Data settling (valid) time required by a flip-flop prior to clock rising edge Setup margin = Tcycle – clock uncertainty – Tsu – Tck-to-d Data valid time required by a flip-flop after the clock rising edge Hold margin = Tck-to-d – (clock skew + Thd) Tcycle: Clock period (Ex: 100MHz clock has Tcycle=10ns) clock uncertainty: clock skew + clock jitter clock skew: difference in clock arrival time (destination – source)=(CK2-CK1) Tck-to-d delay time from source CK to “d” input of destination flip-flop Tsu: setup time spec of destination flip-flop Thd: hold time spec of destination flip-flop Difference in clock arrival time between destination flip-flop & source flip-flop Point-to-point delay Slow nets: <= 80% of clock cycle
n Physical Synthesis (PC) n IPO & ECO flow
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IPO ECO Auto hold fix 2
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Introduction
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What is STA?
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STA stands for “Static Timing Analysis” STA does not require dynamic test vectors It is an alternative way to check timing (as opposed to checking timing with functional/dynamic simulator)
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Basic Std Cell P&R Knowledge
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Today’s standard cells are based on
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Rows with fixed height (ex. Artisan’s TSMC 0.18um library is 5.04um – 8 0.63um grids) based grid size for column is 0.66um) Column is variable (Artisan, TSMC 0.18um library based grid size is 0.66um) Routing layers are directional
Has much faster run time (easily 20x or more) l Provides much higher timing coverage (100% for synchronous design) l Easier to debug timing faults
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Why STA is needed?
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What are the other benefits?
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It can be integrated to tie to RC-extractor tools, physical P&R tools & design libraries to automatically perform timing analysis & optimization (Physical Compiler)
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Basic STA Concepts – 1
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Fundamentals - 1
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We MUST understand the complete “Design Space”
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Design Space
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Process/Device/Interconnect Technologies
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P&R Knowledge
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Design Libraries
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Design Space - Interconnect
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Examples
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(B)
R
(C)
Cwire
Cgate
Cell Delay = tA-to-B Interconnect Delay = t B-to-C ~= R(Cwire+Cgate)
Output Load X X ↑ ↓
Cell Delay ↓ ↑ ↑ ↓
Output Edge Rate ↑ ↓ ↓ ↑
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Timing Dependencies
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Edge Rate Dependency
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Cell delay of Complex gates are less affected by INPUT edge rate
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Process design rules (metal width & spacing) Corner Models – Slow/Slow (min Vdd, max Tj, spsn) Corner Models – Fast/Fast (max Vdd, min Tj, fpfn) Via resistivity Metal resistivity Inter-Metal & Intra-Metal capacitances Preferred metal direction Grid/Row based standard cell P&R Power & Clock implementation Block design best practices Corner libraries (slow/slow & fast/fast) Basic timing format (I/O slew rates & loading dependencies) Basic timing arcs, timing relationship Logic type & drive strength (LP, 1x, 2x,…)
Static Timing Analysis Flow
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Topics
n Introduction n Basic STA Concepts & Technology Readiness
uign space STA basic Crosstalk Timing constraint (SDC) Timing optimization methods Flow & Methodology PT Run Scripts Useful PT Commands ILM model
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Timing Dependencies
(B) (A) C wire Cgate R (C)