W3EG7218S202BD4中文资料

White Electronic DesignsW3EG7218S-AD4-BD4PRELIMINARY*128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLLDESCRIPTIONThe W3EG7218S is a 16Mx72 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM component. The module consists of nine 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate.Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow thesame device to be useful for a variety of high bandwidth, high performance memory system applications.* T his product is under development, is not qualifi ed or characterized and is subject to change without notice.FEATURESDouble-data-rate architecture DDR200 and DDR266Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8)Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power Supply: 2.5V ± 0.20VJEDEC standard 200 pin SO-DIMM package•Package height options: AD4: 35.5mm (1.38") and BD4: 31.75mm (1.25")OPERATING FREQUENCIESDDR266 @CL=2DDR266 @CL=2.5DDR200 @CL=2Clock Speed 133MHz 133MHz 100MHz CL-t RCD -t RP2-2-22.5-3-32-2-2White Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4PIN NAMESA0-A11Address input (Multiplexed)BA0-BA1Bank Select Address DQ0-DQ63Data Input/Output CB0-CB7Check bitsDQS0-DQS8Data Strobe Input/Output CK0Clock Input CK0#Clock Input CKE0Clock Enable Input CS0#Chip Select Input RAS#Row Address Strobe CAS#Column Address Strobe WE#Write Enable DQM0-DQM8Data-In MaskV CC Power Supply (2.5V)V CCQ Power Supply for DQS (2.5V)V SS GroundV REF Power Supply for Reference V CCSPD Serial EEPROM Power Supply (2.3V to 3.6V)SDA Serial Data I/O SCL Serial ClockSA0-SA2Address in EEPROM V CCID V CC Identifi cation Flag NCNo ConnectPIN CONFIGURATIONPin Symbol Pin Symbol Pin Symbol Pin Symbol 1V REF 51V SS 101A9151DQ422V REF 52V SS 102AB 152DQ463V SS 53DQ19103V SS 153DQ434V SS 54DQ23104V SS 154DQ475DQ055DQ24105A7155V CC 6DQ456DQ28106A6156V CC 7DQ157V CC 107A5157V CC 8DQ558V CC 108A4158NC 9V CC 59DQ25109A3159V SS 10V CC 60DQ29110A2160NC 11DQS061DQS3111A1161V SS 12DQM062DQM3112A0162V SS 13DQ263V SS 113V CC 163DQ4814DQ664V SS 114V CC 164DQ5215V SS 65DQ26115A10/AP 165DQ4916V SS 66DQ30116BA1166DQ5317DQ367DQ27117RA0167V CC 18DQ768DQ31118RAS#168V CC 19DQ869V CC 119WE#169DQS620DQ1270V CC 120CAS#170DQM621V CC 71CB0121CS0171DQ5022V CC 72CB4122NC 172DQ5423DQ973CB1123NC 173V SS 24DQ1374CB5124NC 174V SS 25DQS175V SS 125V SS 175DQ5126DQM176V SS 126V SS 176DQ5527V SS 77DQS8127DQ32177DQ5628V SS 78DQM8128DQ36178DQ6029DQ1079CB2129DQ33179V CC 30DQ1480CB6130DQ37180V CC 31DQ1181V CC 131V CC 181DQ5732DQ1582V CC 132V CC 182DQ6133V CC 83CB3133DQS4183DQS734V CC 84CB7134DQM4184DQM735CK085NC 135DQ34185V SS 36V CC 86NC 136DQ38186V SS 37CK0#87V SS 137V SS 187DQ5838V SS 88V SS 138V SS 188DQ6239V SS 89NC 139DQ35189DQ5940V SS 90V SS 140DQ39190DQ6341DQ1691NC 141DQ40191V CC 42DQ2092V CC 142DQ44192V CC 43DQ1793V CC 143V CC 193SDA 44DQ2194V CC 144V CC 194SA045V CC 95NC 145DQ41195SCL 46V CC 96CKE0146DQ45196SA147DQS297NC 147DQS5197V CCSPD 48DQM298NC 148DQM5198SA249DQ1899NC 149V SS 199V CCID 50DQ22100A11150V SS200NCWhite Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4FUNCTIONAL BLOCK DIAGRAMWhite Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4ABSOLUTE MAXIMUM RATINGSParameterSymbol Value Units Voltage on any pin relative to V SS V IN , V OUT – 0.5 ~ 3.6V Voltage on V CC supply relative to V SS V CC , V CCQ –1.0 ~ 3.6V Storage Temperature T STG – 55 ~ +150°C Power Dissipation P D 9W Short Circuit CurrentI OS50mANote:Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC CHARACTERISTICS0°C ≤ T A ≤ 70°C, V CC = 2.5V ± 0.2VCAPACITANCET A = 25°C, f = 1MHz, V CC = 2.5VParameter Symbol Min Max Unit Supply Voltage V CC 2.3 2.7V Supply Voltage V CCQ 2.3 2.7V Reference Voltage V REF 1.15 1.35V Termination Voltage V TT 1.15 1.35V Input High Voltage V IH V REF + 0.15V CCQ + 0.3V Input Low Voltage V IL – 0.3V REF – 0.15V Output High Voltage V OH V TT + 0.76—V Output Low VoltageV OL—V TT – 0.76VParameterSymbol Max Unit Input Capacitance (A0-A11)C IN129pF Input Capacitance (RAS#,CAS#,WE#)C IN229pF Input Capacitance (CKE0,CKE1)C IN329pF Input Capacitance (CK0,CK0#)C IN4 5.5pF Input Capacitance (CS0#,CS1#)C IN529pF Input Capacitance (DQM0-DQM8)C IN68pF Input Capacitance (BA0-BA1)C IN729pF Data input/output Capacitance (DQ0-DQ63)(DQS)C OUT 8pF Data input/output Capacitance (CB0-CB7)C OUT8pFWhite Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4I DD SPECIFICATIONS AND TEST CONDITIONS(Recommended operating conditions, 0°C ≤ T A ≤ 70°C, V CCQ = 2.5V ± 0.2V, V CC = 2.5V ± 0.2V)Parameter Symbol Conditions DDR266 @CL=2DDR266 @CL=2.5DDR200 @CL=2Units Max Max Max Operating CurrentI DD0One device bank; Active - Precharge; (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. t RC =t RC (MIN); t CK =t CK 1125990990mAOperating Current I DD1One device bank; Active-Read-Precharge; Burst = 2;t RC =t RC (MIN);t CK =t CK (MIN); Iout = 0mA; Address and control inputs changing once per clock cycle.121510801080mAPrecharge Power-Down Standby Current I DD2P All device banks idle; Power-down mode; t CK =t CK (MIN); CKE=(low)272727mA Idle Standby CurrentI DD2FCS# = High; All device banks idle; t CK =t CK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. V IN = V REF for DQ, DQS and DM.405405405mAActive Power-Down Standby Current I DD3P One device bank active; Power-down mode; t CK (MIN); CKE=(low)225225225mA Active Standby CurrentI DD3NCS# = High; CKE = High; One device bank; Active-Precharge; t RC =t RAS (MAX); t CK =t CK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle.450450450mAOperating Current I DD4R Burst = 2; Reads; Continous burst; One device bankactive;Address andcontrol inputs changing once per clock cycle; t CK =t CK (MIN); I OUT = 0mA.126011701170mAOperating Current I DD4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; t CK =t CK (MIN); DQ,DM and DQS inputs changing twice per clock cycle.126011251125mAAuto Refresh Current I DD5t RC =t RC (MIN)238519801980mA Self Refresh Current I DD6CKE ≤ 0.2V272727mA Operating CurrentI DD7AFour bank interleaving Reads (BL=4) with auto precharge with t RC =t RC (MIN); t CK =t CK (MIN); Address and control inputs change only during Active Read or Write commands319529702970mAWhite Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4I DD1 : OPERATING CURRENT : ONE BANK1. Typical Case : V CC =2.5V, T=25°C 2. Worst Case : V CC =2.7V, T=10°C3. Only one bank is accessed with t RC (min), BurstMode, Address and Control inputs on NOP edge are changing once per clock cycle. I OUT = 0mA 4. Timing Patterns :•DDR200 (100 MHz, CL=2) : t CK=10ns, CL2,BL=4, t RCD=2*t CK , t RAS=5*t CKRead : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst•DDR266 (133MHz, CL=2.5) : t CK=7.5ns,CL=2.5, BL=4, t RCD=3*t CK , t RC=9*t CK , t RAS=5*t CK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random addresschanging; 50% of data changing at every burst •DDR266 (133MHz, CL=2) : t CK =7.5ns, CL=2, BL=4, t RCD =3*t CK , t RC =9*t CK , t RAS =5*t CKRead : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random addresschanging; 50% of data changing at every burstI DD7A : OPERATING CURRENT : FOUR BANKS1. Typical Case : V CC =2.5V, T=25°C 2. Worst Case : V CC =2.7V, T=10°C3. Four banks are being interleaved with t RC (min),Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns :•DDR200 (100 MHz, CL=2) : t CK =10ns, CL2,BL=4, t RRD =2*t CK , t RCD =3*t CK , Read with AutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst•DDR266 (133MHz, CL=2.5) : t CK =7.5ns, CL=2.5, BL=4, t RRD =3*t CK , t RCD =3*t CK Read with AutoprechargeRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst•DDR266 (133MHz, CL=2) : t CK =7.5ns, CL2=2, BL=4, t RRD =2*t CK , t RCD =2*t CKRead : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burstDETAILED TEST CONDITIONS FOR DDR SDRAM I DD1 & I DD7ALegend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3R (0-3) = Read Bank 0-3White Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONSAC CHARACTERISTICS 262265/202UNITS NOTESPARAMETERSYMBOL MIN MAX MIN MAX Access window of DQs from CK/CK#t AC -0.75+0.75-0.75+0.75ns CK high-level width t CH 0.450.550.450.55t CK 26CK low-level width t CL 0.450.550.450.55t CK 26Clock cycle timeCL = 2.5t CK (2.5)7.5137.513ns 40, 45CL = 2t CK (2)7.5131013ns 40, 45DQ and DM input hold time relative to DQS t DH 0.50.5ns 23, 27DQ and DM input setup time relative to DQS t DS 0.50.5ns 23, 27DQ and DM input pulse width (for each input)t DIPW 1.75 1.75ns 27Access window of DQS from CK/CK#t DQSCK -0.60+0.75-0.75+0.75ns DQS input high pulse width t DQSH 0.350.35t CK DQS input low pulse widtht DQSL 0.350.35t CK DQS-DQ skew, DQS to last DQ valid, per group, per access t DQSQ 0.50.6ns 22, 23Write command to fi rst DQS latching transition t DQSS 0.75 1.250.75 1.25t CK DQS falling edge to CK rising - setup time t DSS 0.20.2t CK DQS falling edge from CK rising - hold time t DSH 0.20.2t CK Half clock periodt HP t CH, t CLt CH, t CLns 30Data-out high-impedance window from CK/CK#t HZ +0.75+0.75ns 16, 37Data-out low-impedance window from CK/CK#t LZ -0.75-0.75ns 16, 37Address and control input hold time (slow slew rate)t IHS 0.90 1.1ns 12Address and control input setup time (slow slew rate)t ISS 0.90 1.1ns 12Address and Control input pulse width (for each input)t IPW 2.2 2.2ns LOAD MODE REGISTER command cycle timet MRD1515nsWhite Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued)AC CHARACTERISTICS 262265/202UNITS NOTESPARAMETERSYMBOL MIN MAXMINMAXDQ-DQS hold, DQS to fi rst DQ to go non-valid, per access t QH t HP - t QHSt HP - t QHSns 22, 23Data Hold Skew Factort QHS 0.750.75ns ACTIVE to PRECHARGE commandt RAS 40120,00040120,000ns 31, 48ACTIVE to READ with Auto precharge command t RAP 1520ns ACTIVE to ACTIVE/AUTO REFRESH command period t RC 6065ns AUTO REFRESH command period t RFC 7575ns 43ACTIVE to READ or WRITE delay t RCD 1520ns PRECHARGE command period t RP 1520nsDQS read preamble t RPRE 0.9 1.10.9 1.1t CK 38DQS read postamblet RPST 0.40.60.40.6t CK 38ACTIVE bank a to ACTIVE bank b command t RRD 1515ns DQS write preamblet WPRE 0.250.25t CK DQS write preamble setup time t WPRES 00ns18, 19DQS write postamble t WPST 0.40.60.40.6tCK 17Write recovery timet WR 1515ns Internal WRITE to READ command delay t WTR11t CKData valid output window (DVW)nat QH - t DQSQt QH - t DQSQns 22REFRESH to REFRESH command interval t REFC 140.6140.6µs 21Average periodic refresh interval t REFI 15.615.6µs 21Terminating voltage delay to VDDt VTD 00ns Exit SELF REFRESH to non-READ command t XSNR 7575ns Exit SELF REFRESH to READ commandt XSRD200200t CKWhite Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4Notes1. All voltages referenced to V SS .2. Tests for AC timing, I DD , and electrical AC and DC characteristics may beconducted at nominal reference/supply voltage levels, but the related specifi cations and device operation are guaranteed for the full voltage range specifi ed.3. Outputs measured with equivalent load:Output (V OUT )Ω4. AC timing and I DD tests may use a V IL -to-V IH swing of up to 1.5V in the testenvironment, but input timing is still referenced to V REF (or to the crossing point for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between V IL (AC) and V IH (AC).5. The AC and DC input level specifi cations are as defi ned in the SSTL_2 Standard(i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level).6. V REF is expected to equal V CCQ/2 of the transmitting device and to track variationsin the DC level of the same. Peak-to-peak noise (non-common mode) on Vref may not exceed ±2 percent of the DC value. Thus, from V CCQ/2, Vref is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest V REF bypass capacitor.7. V TT is not applied directly to the device. V TT is a system supply for signaltermination resistors, is expected to be set equal to V REF and must track variations in the DC level of V REF .8. I DD is dependent on output loading and cycle rates. Specifi ed values are obtainedwith mini-mum cycle time at CL = 2 for -26A and -202, CL = 2.5 for -335 and -265 with the outputs open.9. Enables on-chip refresh and address counters.10. I DD specifi cations are tested after the device is properly initialized, and is averagedat the defi ned cycle rate.11. This parameter is sampled. V CC = +2.5V ±0.2V, V CCQ = +2.5V ±0.2V, V REF = V SS , f= 100 MHz, TA = 25°C, V OUT (DC) = V CCQ/2, V OUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, refl ecting the fact that they are matched in loading.12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timingmust be derated: t IS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while t IH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -335, slew rates must be 0.5 V/ns.13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point atwhich CK and CK# cross; the input reference level for signals other than CK/CK# is V REF .14. Inputs are not recognized as valid until V REF stabilizes. Exception: during the periodbefore V REF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW.15. The output timing reference level, as measured at the timing reference pointindicated in Note 3, is V TT .16. t HZ and t LZ transitions occur in the same access time windows as data validtransitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).17. The intent of the Don’t Care state after completion of the postamble is the DQS-driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high [above V IHDC (MIN)] then it must not transition low (below V IHDC ) prior to t DQSH (MIN).18. This is not a device limit. The device will operate with a negative value, but systemperformance could be degraded due to bus turnaround.19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITEcommand. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.20. MIN (t RC or t RFC ) for I DD measurements is the smallest multiple of t CK that meetsthe minimum absolute value for the respective parameter. t RAS (MAX) for I DDmeasurements is the largest multiple of t CK that meets the maximum absolute value for t RAS .21. The refresh period 64ms. This equates to an average refresh rate of 15.625µs128MB. However, an AUTO REFRESH command must be asserted at least once every 140.6µs 128MB; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed.22. The valid data window is derived by achieving other specifi cations: t HP (t CK/2), t DQSQ ,and t QH (t QH = t HP - t QHS ). The data valid window derates in direct porportion with the clock duty cycle and a practical data valid window can be derived, as shown in Figure 7, Derating Data Valid Window. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.23. Each byte lane has a corresponding DQS.24. This limit is actually a nominal value and does not result in a fail value. CKE isHIGH during REFRESH command period (t RFC [MIN]) else CKE is LOW (i.e., during standby).25. To maintain a valid level, the transitioning edge of the input must: a. S ustain a constant slew rate from the current AC level through to the target AClevel, V IL (AC) or V IH (AC).b. Reach at least the target AC level.c. A fter the AC target level is reached, continue to maintain at least the target DClevel, V IL (DC) or V IH (DC).26. JEDEC specifi es CK and CK# input slew rate must be ≤ 1V/ns (2V/nsdifferentially).27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100 mv/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns.28. V CC must not vary more than 4 percent if CKE is not active while any bank is active.29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to varyby the same amount.30. t HP min is the lesser of t CL minimum and t CH minimum actually applied to the deviceCK and CK# inputs, collectively during bank active.31. READs and WRITEs with auto precharge are not allowed to be issued untilt RAS (min) can be satisfi ed prior to the internal precharge command being issued.32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or2.9V, which ever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either - 300mV or 2.2V, whichever is more positive.White Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD433. Normal Output Drive Curves: a. T he full variation in driver pull-down current from minimum to maximum process,temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics.b. T he variation in driver pull-down current within nominal limits of voltage andtemperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics.c. T he full variation in driver pull-up current from minimum to maximum process,temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics d. T he variation in driver pull-up current within nominal limits of voltage andtemperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics.e. T he full variation in the ratio of the maximum to minimum pull-up and pull-downcurrent should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature.f. T he full variation in the ratio of the nominal pull-up to pull-down current shouldbe unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V.34. The voltage levels used are derived from a mini-mum V CC level and the referencedtest load. In practice, the voltage levels obtained from a properly terminated bus will provide signifi cantly different voltage values.35. V IH overshoot: V IH (MAX) = V CCQ + 1.5V for a pulse width !5 3ns and the pulse widthcan not be greater than 1/3 of the cycle rate. V IL undershoot: V IL (MIN) = -1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate.36. V CC and V CCQ must track each other.37. t HZ (MAX) will prevail over t DQSCK (MAX) + t RPST (MAX) condition. t LZ (MIN) willprevail over t DQSCK (MIN) + t RPRE (MAX) condition.38. t RPST end point and t RPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (t RPST ), or begins driving (t RPRE ).39. During initialization, V CCQ , V TT , and V REF must be equal to or less than V CC + 0.3V.Alternatively, V TT may be 1.35V maximum during power up, even if V CC /V CCQ are 0Vs, provided a minimum of 42 0 of series resistance is used between the V TT supply and the input pin.40. The part operates below the slowest JEDEC operating frequency of 83 MHz. Assuch, future die may not refl ect this option.41. Random addressing changing and 50 percent of data changing at every transfer.42. Random addressing changing and 100 percent of data changing at every transfer.43. CKE must be active (high) during the entire time a refresh command is executed.That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later.44. I DD2N specifi es the DQ, DQS, and DM to be driven to a valid high or low logic level.I DD2Q is similar to I DD2F except I DD2Q specifi es the address and control inputs to remain stable. Although I DD2F , I DD2N , and I DD2Q are similar, I DD2F is “worst case.”45. Whenever the operating frequency is altered, not including jitter, the DLL is requiredto be reset. This is followed by 200 clock cycles.46. Leakage number refl ects the worst case leakage possible through the module pin,not what each memory device contributes.47. When an input signal is HIGH or LOW, it is defi ned as a steady state logic HIGH orLOW.48. The -335 speed grade will operate with t RAS (MIN) = 40ns and t RAS (MAX) =120,000ns at any slower frequency.White Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4PACKAGE DIMENSIONS FOR AD4ORDERING INFORMATION FOR AD4* All dimensions are in MILLIMETERS AND (INCHES)Part Number SpeedHeight*W3EG7218S262AD4133MHz/266Mbps, CL=235.05 (1.38")W3EG7218S265AD4133MHz/266Mbps, CL=2.535.05 (1.38")W3EG7218S202AD4100MHz/200Mbps, CL=235.05 (1.38")White Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)PACKAGE DIMENSIONS FOR BD4ORDERING INFORMATION FOR BD4Part Number SpeedHeight*W3EG7218S262BD4133MHz/266Mbps, CL=231.75 (1.25")W3EG7218S265BD4133MHz/266Mbps, CL=2.531.75 (1.25")W3EG7218S202BD4100MHz/200Mbps, CL=231.75 (1.25")White Electronic DesignsPRELIMINARYW3EG7218S-AD4-BD4Document Title128MB – 16Mx72 DDR SDRAM UNBUFFERED w/PLLRevision History Rev #HistoryRelease DateStatusRev A Created7-23-03Advanced Rev 00.1 Data sheet spec updates0.2 Changed datasheet from Advanced to Preliminary 0.3 Added “BD4” package optionr9-04PreliminaryRev 1 1.1 Updated new I DD and CAP specs 11-04Preliminary。