SN74LVC2G04YZPR中文资料

DESCRIPTION/ORDERING INFORMATION (CONTINUED)
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
Copyright © 1999–2005, Texas Instruments Incorporated
元器件交易网
SN74LVC2G04 DUAL INVERTER GATE
SCES195J – APRIL 1999 – REVISED JULY 2005

VCC
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
VO
Voltage range applied to any output in the high or low state(2)(3)
SN74LVC2G04 DUAL INVERTER GATE
SCES195J – APRIL 1999 – REVISED JULY 2005
DBV OR DCK PACKAGE (TOP VIEW)
1A 1 GND 2
2A 3
6 1Y 5 VCC 4 2Y
YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW)
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
2
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Recommended Operating Conditions(1)
SN74LVC2G04 DUAL INVERTER GATE
SCES195J – APRIL 1999 – REVISED JULY 2005
VCC
Supply voltage
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
IO
Continuous output current
Continuous current through VCC or GND
DBV impedance(4)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
DCK package YEA/YZA package
YEP/YZP package
Tstg
Storage temperature range
MIN
MAX
–0.5
6.5
–0.5
6.5
–0.5
6.5
–0.5 VCC + 0.5 –50
–50
±50
±100
165
259
143
123
–65
150
UNIT V V V V mA mA mA mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v Input transition rise or fall rate
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The value of VCC is provided in the recommended operating conditions table. (4) The package thermal impedance is calculated in accordance with JESD 51-7.
ORDERING INFORMATION
TA
PACKAGE (1)
NanoStar™ – WCSP (DSBGA) 0.17-mm Small Bump – YEA
ORDERABLE PART NUMBER SN74LVC2G04YEAR
–40°C to 85°C
NanoFree™ – WCSP (DSBGA) 0.17-mm Small Bump – YZA (Pb-free)
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA,YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP
NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000
SN74LVC2G04YZAR SN74LVC2G04YEPR
TOP-SIDE MARKING(2) _ _ _CC_
C04_ CC_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at /sc/package.
TA
Operating free-air temperature
Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V
FUNCTION TABLE (EACH INVERTER)
INPUT A
H
L
OUTPUT Y
L
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1 1A
6 1Y
3 2A
4 2Y
Absolute Maximum Ratings(1)