MSP430单片机IO引脚的宏定义
单片机430
MSP430单片机介绍一．C简介1．数据类型int，unsigned int，char, float, long, unsigned long了解表示数据范围。
2．运算符：算法的实现，牢记。
3．程序结构：顺序，分支，循环。
4．函数：重要。
C语言程序都是函数构成的，在main函数中可以很清楚的看到整个程序的结构和功能。
其它函数可以放在当前文件也可以放在其他文件中，若在其他的C文件中，需要建立同名的H文件，然在main文件中包含H文件，H文件相当于接口。
函数是由语句和参数构成的，理解局部变量全局变量，形参实参概念。
举例说明。
5．宏定义：#define PI 3.14#define S（r）PI*(r)*（r）宏调用：int r；Int area;Area= S（r）;6.头文件：两个同名的h文件和c文件，c文件中定义函数，h文件为接口。
7条件编译：控制汇编过程。
是否对以下代码就行汇编？？#ifdef ……..如果条件满足则对以下程序段进行汇编程序段#endif总结：C语言结构清晰，很容易理解程序的编程思路，特别适用于程序较大，使用函数多的情况。
特别注意头文件，一般要包含器件的h 文件，例如#include <msp430x16x.h>，其中主要提供寄存器的声明，另外输入输出，算术运算头文件也可能用到，当然也可以自己编写头文件和对应的c文件。
二．430介绍重点：时钟；I/O；定时器其次：键盘显示；AD; DA其他内容自己了解。
概述：430和51相比外围模块更丰富，功能更强大，学习起来更麻烦，但方法仍然是查看特殊功能寄存器说明，同时要结合例程来理解，因为我们不学汇编语言，所以一定要掌握在c语言中正确设置寄存器。
430的资料大多是C语言的，较好的网络资源：利尔达论坛，微控论坛，可以再TI官网上下载例程。
1．C语言软件延时程序。
用汇编语言可以很精确的计算出软件延时时间，因为每条指令的指令周期是已知的。
MSP430单片机IO引脚的宏定义
MSP430单片机IO引脚的宏定义相信不少人都有在不同CPU间移植程序的经历，在移植过程中，对IO引脚的移植又占据了移植工作的大部分。
那么，是否能在编码过程中采用一种较好的方法来减少将来移植中的工作量呢？假设MSP430单片机的P40，P41，P42分别接在I2C的WP，SCK，SDL引脚上。
通常，你可能会最先想到下面这种办法：.H#define I2C_WP 1#define I2C_SCK 2#define I2C_SDA 4#define I2C_PDIR P4DIR#define I2C_POUT P4OUT#define I2C_PIN P4IN.CI2C_PDIR |= (I2C_WP | I2C_SCK | I2C_SDA);I2C_POUT |= I2C_WP;….若WP是由P30经反相器接到WP脚上的，那么移植的工作量仍然是比较多，#define IO_I2C_WP(m) m(3, 0, Y)#define IO_I2C_SCK(m) m(4, 1, N)#define IO_I2C_SDA (m) m(4, 2, N)#define IO_SET(name) IO_##name(SET_)#define IO_SET_(port, bit, inv) IO_SET_##inv(port, bit)#define IO_SET_Y(port, bit) P##port##OUT &= ~(1<<bit)< bdsfid="82" p=""></bit)<>#define IO_SET_N(port, bit) P##port##OUT |= (1<<bit)< bdsfid="84" p=""></bit)<>#define IO_CLR(name) IO_##name(CLR_)#define IO_CLR_(port, bit, inv) IO_CLR_##inv(port, bit)#define IO_CLR_Y(port, bit) P##port##OUT |= (1<<bit)< bdsfid="88" p=""></bit)<>#define IO_CLR_N(port, bit) P##port##OUT &= ~(1<<bit)< bdsfid="90" p=""></bit)<>#define IO_DIR_O(name) IO_##name(DIR_O_)#define IO_DIR_I(name) IO_##name(DIR_I_)#define IO_DIR_O_(port, bit, inv) P##port##DIR |= (1<<bit)< bdsfid="94" p=""></bit)<>#define IO_DIR_I_(port, bit, inv) P##port##DIR &=~ (1<<bit)< bdsfid="96" p=""></bit)<>#define IO_TEST(name) IO_#name(TEST_)#define IO_TEST_(port, bit, inv) IO_TEST_##inv(port, bit)#define IO_TEST_Y(port, bit) ((P##port##IN & (1<#define IO_TEST_N(port, bit) ((P##port##IN & (1<#define IO_PORT(name) IO_##name(PORT_)#define IO_PORT_(port, bit, inv) port#define IO_BIT(name) IO_##name(BIT_)#define IO_BIT_(port, bit, inv) (1<<bit)< bdsfid="107" p=""></bit)<>#define IO_P4_MASK(m)(m(I2C_SCK)| m(I2C_SDA))…..如上所示，你可以按照上面的方式增加自己的功能。
MSP430单片机IO端口控制特点
MSP430单片机IO端口控制特点与8031单片机相比，MSP430的I/O端口的功能要强大的多，其控制的方法也更为复杂。
MSP430的I/O端口可以实现双向的输入、输出;完成一些特殊功能如：驱动LCD、A/D转换、捕获比较等;实现I/O各种中断。
MSP430采用了传统的8位端口方式保证其兼容性，即每个I/O端口控制8个I/O引脚。
为了实现对I/O端口每一个引脚的复杂控制，MSP430中的每个I/O口都对应一组8位的控制寄存器(如图1)。
寄存器中的每一位对应一个I/O引脚，实现对该引脚的独立控制。
寄存器的功能和数目是由该I/O口所能完成的功能以及类型确定的。
图1为MSP430的一个I/O端口的控制结构示意图。
对于最基本的只能完成输入、输出功能的I/O端口其控制寄存器只有3个。
其中，输入寄存器保存输入状态;输出寄存器保存输出的状态，方向寄存器控制对应引脚的输入、输出状态。
本文中用来实现I2C总线接口的P6.6、P6.7都属于这类的端口。
此外，有些I/O端口不但可以用作基本的输入输出，而且可以用作其他用途，比如可以作为LCD的驱动控制引脚。
这类端口的控制功能寄存器实现引脚功能状态的切换。
再者，有一类端口不但可以完成上述两种端口的功能，而且可以实现中断功能。
该类端口拥有图1中所有的寄存器，中断触发的方式以及中断的屏蔽性都可以通过相应的寄存器控制。
本文中使用的P2.0就属于该类端口，利用它来接收LM92发出的中断。
通过上述的控制结构，MSP430的I/O端口可以实现很丰富的功能。
不仅如此，其中一些I/O口还可以与MSP430中的特殊模块相结合完成更为复杂的工作。
如与捕获比较模块相结合可以实现串行通信，与A/D模块结合实现A/D转换等。
此外，MSP430 I/O端口的电器特性也十分突出，几乎所有的I/O口都有20mA的驱动能力，对于一般的LED、蜂鸣器可以直接驱动无需辅助电路。
许多端口内部都集成了上拉电阻，可以方便与外围器件的接口。
MSP430系列单片机简介
MSP430系列单片机简介MSP430系列单片机是美国德州仪器(TI)推向市场的一个16位、具有精简指令集、超低功耗的混合型单片机，自1996年问世，由于它具有极低的功耗、丰富的片内外设备和方便灵活的开发手段，成为许多电子产品设计的首选，1999年进入中国就受到了中国广大设计工程师的青睐。
目前，该系列单片机不仅在电子工程、测控技术与仪器、自动控制、机电一体化等方面得到广泛应用，而且逐渐走进校园，被越来越多的使用在硕士研究生和高年级本科生的科技实践和毕业设计中，在2005年暑期全国大学生电子设计竞赛中就选用了该系列的单片机[5]。
MSP430系列单片机的型号很多，TI公司用3或4位数字表示单片机型号，其中一位数字表示一个系列。
目前有四大系列：带有液晶驱动的MSP430F4xx 系列单片机、不带液晶驱动器的MSP430F1xx系列单片机、16MIPS高速MSP430F2xx系列单片机、一次性写入（OTP）型低价MSP430C系列单片机，每个系列中又含有许多子系列。
单片机型号的第二位数字表示子系列号，一般子系列号越大包含的功能模块越多，最后一或两位数字表示存储器容量，数字越大表示ROM和RAM的容量越大。
此外，MSP430系列单片机还针对许多热门应用设计了一系列专用单片机，如水表专用单片机、医疗仪器专用单片机，电能计量专用单片机，这些单片机都是在相同型号的通用单片机的基础上增加专用模块构成的[5]。
MSP430F449单片机的主要性能有：●低供电电压范围：1.8V-3.6V及欠电压检测器●超低功耗，具有五种省电模式：活动模式：1MHz，2.2V时为280uA；等待模式：1.6uA；关闭模式（RAM保持）：0.1uA●数字控制的振荡器（DCO）可以在6us内将CPU从休眠中唤醒，这也是实现低功耗的重要手段之一●16位精简指令结构，125ns指令时间周期，10个16位的寄存器以及常数发生器，能够最大限度的提高代码的效率●具有内部参考电平，采样保持和自动扫描的12位A/D转换器●带有三个或七个捕捉/比较影子寄存器的16位定时器B●带有三个捕捉/比较寄存器的16位定时器A● 串行通讯接口（USART ），软件选择异步UART 或者同步SPI 接口，对于MSP430F44x 系列的单片机有两个UART （UART0，UART1）● 可编程电平检测的供电电压管理器/监视器● 串行在线编程无需外部编程电压，可编程的安全熔丝代码保护● 集成多达160段的LCD 驱动器如图2.1所示为MSP430F449单片机的引脚图。
Msp430f149头文件宏定义汇总
Msp430f149.h中的宏定义/************************************************************ * STANDARD BITS************************************************************/#define BIT0 (0x0001u)#define BIT1 (0x0002u)#define BIT2 (0x0004u)#define BIT3 (0x0008u)#define BIT4 (0x0010u)#define BIT5 (0x0020u)#define BIT6 (0x0040u)#define BIT7 (0x0080u)#define BIT8 (0x0100u)#define BIT9 (0x0200u)#define BITA (0x0400u)#define BITB (0x0800u)#define BITC (0x1000u)#define BITD (0x2000u)#define BITE (0x4000u)#define BITF (0x8000u)/************************************************************ * STATUS REGISTER BITS************************************************************/#define C (0x0001u)#define Z (0x0002u)#define N (0x0004u)#define V (0x0100u)#define GIE (0x0008u)#define CPUOFF (0x0010u)#define OSCOFF (0x0020u)#define SCG0 (0x0040u)#define SCG1 (0x0080u)/* Low Power Modes coded with Bits 4-7 in SR */#ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */#define LPM0 (CPUOFF)#define LPM1 (SCG0+CPUOFF)#define LPM2 (SCG1+CPUOFF)#define LPM3 (SCG1+SCG0+CPUOFF)#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)/* End #defines for assembler */#else /* Begin #defines for C */#define LPM0_bits (CPUOFF)#define LPM1_bits (SCG0+CPUOFF)#define LPM2_bits (SCG1+CPUOFF)#define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)#include "in430.h"#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */#endif /* End #defines for C *//************************************************************* PERIPHERAL FILE MAP************************************************************//************************************************************* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS************************************************************/#define IE1_ (0x0000u) /* Interrupt Enable 1 */DEFC( IE1 , IE1_)#define U0IE IE1 /* UART0 Interrupt Enable Register */ #define WDTIE (0x01)#define OFIE (0x02)#define NMIIE (0x10)#define ACCVIE (0x20)#define URXIE0 (0x40)#define UTXIE0 (0x80)#define IFG1_ (0x0002u) /* Interrupt Flag 1 */DEFC( IFG1 , IFG1_)#define U0IFG IFG1 /* UART0 Interrupt Flag Register */#define WDTIFG (0x01)#define OFIFG (0x02)#define NMIIFG (0x10)#define URXIFG0 (0x40)#define UTXIFG0 (0x80)#define ME1_ (0x0004u) /* Module Enable 1 */DEFC( ME1 , ME1_)#define U0ME ME1 /* UART0 Module Enable Register */#define URXE0 (0x40)#define UTXE0 (0x80)#define USPIE0 (0x40)#define IE2_ (0x0001u) /* Interrupt Enable 2 */DEFC( IE2 , IE2_)#define U1IE IE2 /* UART1 Interrupt Enable Register */#define URXIE1 (0x10)#define UTXIE1 (0x20)#define IFG2_ (0x0003u) /* Interrupt Flag 2 */DEFC( IFG2 , IFG2_)#define U1IFG IFG2 /* UART1 Interrupt Flag Register */#define URXIFG1 (0x10)#define UTXIFG1 (0x20)#define ME2_ (0x0005u) /* Module Enable 2 */DEFC( ME2 , ME2_)#define U1ME ME2 /* UART1 Module Enable Register */#define URXE1 (0x10)#define UTXE1 (0x20)#define USPIE1 (0x10)/************************************************************* WATCHDOG TIMER************************************************************/#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */#define WDTCTL_ (0x0120u) /* Watchdog Timer Control */DEFW( WDTCTL , WDTCTL_)/* The bit names have been prefixed with "WDT" */#define WDTIS0 (0x0001u)#define WDTIS1 (0x0002u)#define WDTSSEL (0x0004u)#define WDTCNTCL (0x0008u)#define WDTTMSEL (0x0010u)#define WDTNMI (0x0020u)#define WDTNMIES (0x0040u)#define WDTHOLD (0x0080u)#define WDTPW (0x5A00u)/* WDT-interval times [1ms] coded with Bits 0-2 *//* WDT is clocked by fSMCLK (assumed 1MHz) */#define WDT_MDL Y_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */#define WDT_MDL Y_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */#define WDT_MDL Y_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */#define WDT_MDL Y_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " *//* WDT is clocked by fACLK (assumed 32KHz) */#define WDT_ADL Y_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */#define WDT_ADL Y_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */#define WDT_ADL Y_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */#define WDT_ADL Y_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " *//* Watchdog mode -> reset after expired time *//* WDT is clocked by fSMCLK (assumed 1MHz) */#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " *//* WDT is clocked by fACLK (assumed 32KHz) */#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " *//* INTERRUPT CONTROL *//* These two bits are defined in the Special Function Registers *//* #define WDTIE 0x01 *//* #define WDTIFG 0x01 *//************************************************************* HARDWARE MULTIPLIER************************************************************/#define __MSP430_HAS_MPY__ /* Definition to show that Module is available */#define MPY_ (0x0130u) /* Multiply Unsigned/Operand 1 */DEFW( MPY , MPY_)#define MPYS_ (0x0132u) /* Multiply Signed/Operand 1 */DEFW( MPYS , MPYS_)#define MAC_ (0x0134u) /* Multiply Unsigned and Accumulate/Operand 1 */DEFW( MAC , MAC_)#define MACS_ (0x0136u) /* Multiply Signed and Accumulate/Operand 1 */ DEFW( MACS , MACS_)#define OP2_ (0x0138u) /* Operand 2 */DEFW( OP2 , OP2_)#define RESLO_ (0x013Au) /* Result Low Word */DEFW( RESLO , RESLO_)#define RESHI_ (0x013Cu) /* Result High Word */DEFW( RESHI , RESHI_)#define SUMEXT_ (0x013Eu) /* Sum Extend */READ_ONL Y DEFW( SUMEXT , SUMEXT_)/************************************************************* DIGITAL I/O Port1/2************************************************************/#define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */ #define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */#define P1IN_ (0x0020u) /* Port 1 Input */READ_ONL Y DEFC( P1IN , P1IN_)#define P1OUT_ (0x0021u) /* Port 1 Output */DEFC( P1OUT , P1OUT_)#define P1DIR_ (0x0022u) /* Port 1 Direction */DEFC( P1DIR , P1DIR_)#define P1IFG_ (0x0023u) /* Port 1 Interrupt Flag */DEFC( P1IFG , P1IFG_)#define P1IES_ (0x0024u) /* Port 1 Interrupt Edge Select */DEFC( P1IES , P1IES_)#define P1IE_ (0x0025u) /* Port 1 Interrupt Enable */DEFC( P1IE , P1IE_)#define P1SEL_ (0x0026u) /* Port 1 Selection */DEFC( P1SEL , P1SEL_)#define P2IN_ (0x0028u) /* Port 2 Input */READ_ONL Y DEFC( P2IN , P2IN_)#define P2OUT_ (0x0029u) /* Port 2 Output */DEFC( P2OUT , P2OUT_)#define P2DIR_ (0x002Au) /* Port 2 Direction */DEFC( P2DIR , P2DIR_)#define P2IFG_ (0x002Bu) /* Port 2 Interrupt Flag */DEFC( P2IFG , P2IFG_)#define P2IES_ (0x002Cu) /* Port 2 Interrupt Edge Select */DEFC( P2IES , P2IES_)#define P2IE_ (0x002Du) /* Port 2 Interrupt Enable */DEFC( P2IE , P2IE_)#define P2SEL_ (0x002Eu) /* Port 2 Selection */DEFC( P2SEL , P2SEL_)/************************************************************* DIGITAL I/O Port3/4************************************************************/#define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */ #define __MSP430_HAS_PORT4__ /* Definition to show that Module is available */#define P3IN_ (0x0018u) /* Port 3 Input */READ_ONL Y DEFC( P3IN , P3IN_)#define P3OUT_ (0x0019u) /* Port 3 Output */DEFC( P3OUT , P3OUT_)#define P3DIR_ (0x001Au) /* Port 3 Direction */DEFC( P3DIR , P3DIR_)#define P3SEL_ (0x001Bu) /* Port 3 Selection */DEFC( P3SEL , P3SEL_)#define P4IN_ (0x001Cu) /* Port 4 Input */READ_ONL Y DEFC( P4IN , P4IN_)#define P4OUT_ (0x001Du) /* Port 4 Output */DEFC( P4OUT , P4OUT_)#define P4DIR_ (0x001Eu) /* Port 4 Direction */DEFC( P4DIR , P4DIR_)#define P4SEL_ (0x001Fu) /* Port 4 Selection */DEFC( P4SEL , P4SEL_)/************************************************************* DIGITAL I/O Port5/6************************************************************/#define __MSP430_HAS_PORT5__ /* Definition to show that Module is available */ #define __MSP430_HAS_PORT6__ /* Definition to show that Module is available */#define P5IN_ (0x0030u) /* Port 5 Input */READ_ONL Y DEFC( P5IN , P5IN_)#define P5OUT_ (0x0031u) /* Port 5 Output */DEFC( P5OUT , P5OUT_)#define P5DIR_ (0x0032u) /* Port 5 Direction */DEFC( P5DIR , P5DIR_)#define P5SEL_ (0x0033u) /* Port 5 Selection */DEFC( P5SEL , P5SEL_)#define P6IN_ (0x0034u) /* Port 6 Input */READ_ONL Y DEFC( P6IN , P6IN_)#define P6OUT_ (0x0035u) /* Port 6 Output */DEFC( P6OUT , P6OUT_)#define P6DIR_ (0x0036u) /* Port 6 Direction */DEFC( P6DIR , P6DIR_)#define P6SEL_ (0x0037u) /* Port 6 Selection */DEFC( P6SEL , P6SEL_)/************************************************************* USART************************************************************//* UxCTL */#define PENA (0x80) /* Parity enable */#define PEV (0x40) /* Parity 0:odd / 1:even */#define SPB (0x20) /* Stop Bits 0:one / 1: two */#define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */#define LISTEN (0x08) /* Listen mode */#define SYNC (0x04) /* UART / SPI mode */#define MM (0x02) /* Master Mode off/on */#define SWRST (0x01) /* USART Software Reset *//* UxTCTL */#define CKPH (0x80) /* SPI: Clock Phase */#define CKPL (0x40) /* Clock Polarity */#define SSEL1 (0x20) /* Clock Source Select 1 */#define SSEL0 (0x10) /* Clock Source Select 0 */#define URXSE (0x08) /* Receive Start edge select */#define TXW AKE (0x04) /* TX Wake up mode */#define STC (0x02) /* SPI: STC enable 0:on / 1:off */#define TXEPT (0x01) /* TX Buffer empty *//* UxRCTL */#define FE (0x80) /* Frame Error */#define PE (0x40) /* Parity Error */#define OE (0x20) /* Overrun Error */#define BRK (0x10) /* Break detected */#define URXEIE (0x08) /* RX Error interrupt enable */#define URXWIE (0x04) /* RX Wake up interrupt enable */#define RXW AKE (0x02) /* RX Wake up detect */#define RXERR (0x01) /* RX Error Error *//************************************************************* USART 0************************************************************/#define __MSP430_HAS_UART0__ /* Definition to show that Module is available */#define U0CTL_ (0x0070u) /* USART 0 Control */DEFC( U0CTL , U0CTL_)#define U0TCTL_ (0x0071u) /* USART 0 Transmit Control */DEFC( U0TCTL , U0TCTL_)#define U0RCTL_ (0x0072u) /* USART 0 Receive Control */DEFC( U0RCTL , U0RCTL_)#define U0MCTL_ (0x0073u) /* USART 0 Modulation Control */DEFC( U0MCTL , U0MCTL_)#define U0BR0_ (0x0074u) /* USART 0 Baud Rate 0 */DEFC( U0BR0 , U0BR0_)#define U0BR1_ (0x0075u) /* USART 0 Baud Rate 1 */DEFC( U0BR1 , U0BR1_)#define U0RXBUF_ (0x0076u) /* USART 0 Receive Buffer */READ_ONL Y DEFC( U0RXBUF , U0RXBUF_)#define U0TXBUF_ (0x0077u) /* USART 0 Transmit Buffer */DEFC( U0TXBUF , U0TXBUF_)/* Alternate register names */#define UCTL0 U0CTL /* USART 0 Control */#define UTCTL0 U0TCTL /* USART 0 Transmit Control */#define URCTL0 U0RCTL /* USART 0 Receive Control */#define UMCTL0 U0MCTL /* USART 0 Modulation Control */#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */#define UCTL0_ U0CTL_ /* USART 0 Control */#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */#define UCTL_0 U0CTL /* USART 0 Control */#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */#define URCTL_0 U0RCTL /* USART 0 Receive Control */#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */#define UCTL_0_ U0CTL_ /* USART 0 Control */#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer *//************************************************************* USART 1************************************************************/#define __MSP430_HAS_UART1__ /* Definition to show that Module is available */#define U1CTL_ (0x0078u) /* USART 1 Control */DEFC( U1CTL , U1CTL_)#define U1TCTL_ (0x0079u) /* USART 1 Transmit Control */DEFC( U1TCTL , U1TCTL_)#define U1RCTL_ (0x007Au) /* USART 1 Receive Control */DEFC( U1RCTL , U1RCTL_)#define U1MCTL_ (0x007Bu) /* USART 1 Modulation Control */DEFC( U1MCTL , U1MCTL_)#define U1BR0_ (0x007Cu) /* USART 1 Baud Rate 0 */DEFC( U1BR0 , U1BR0_)#define U1BR1_ (0x007Du) /* USART 1 Baud Rate 1 */DEFC( U1BR1 , U1BR1_)#define U1RXBUF_ (0x007Eu) /* USART 1 Receive Buffer */ READ_ONL Y DEFC( U1RXBUF , U1RXBUF_)#define U1TXBUF_ (0x007Fu) /* USART 1 Transmit Buffer */ DEFC( U1TXBUF , U1TXBUF_)/* Alternate register names */#define UCTL1 U1CTL /* USART 1 Control */#define UTCTL1 U1TCTL /* USART 1 Transmit Control */#define URCTL1 U1RCTL /* USART 1 Receive Control */#define UMCTL1 U1MCTL /* USART 1 Modulation Control */ #define UBR01 U1BR0 /* USART 1 Baud Rate 0 */#define UBR11 U1BR1 /* USART 1 Baud Rate 1 */#define RXBUF1 U1RXBUF /* USART 1 Receive Buffer */#define TXBUF1 U1TXBUF /* USART 1 Transmit Buffer */#define UCTL1_ U1CTL_ /* USART 1 Control */#define UTCTL1_ U1TCTL_ /* USART 1 Transmit Control */#define URCTL1_ U1RCTL_ /* USART 1 Receive Control */#define UMCTL1_ U1MCTL_ /* USART 1 Modulation Control */ #define UBR01_ U1BR0_ /* USART 1 Baud Rate 0 */#define UBR11_ U1BR1_ /* USART 1 Baud Rate 1 */#define RXBUF1_ U1RXBUF_ /* USART 1 Receive Buffer */#define TXBUF1_ U1TXBUF_ /* USART 1 Transmit Buffer */#define UCTL_1 U1CTL /* USART 1 Control */#define UTCTL_1 U1TCTL /* USART 1 Transmit Control */#define URCTL_1 U1RCTL /* USART 1 Receive Control */#define UMCTL_1 U1MCTL /* USART 1 Modulation Control */ #define UBR0_1 U1BR0 /* USART 1 Baud Rate 0 */#define UBR1_1 U1BR1 /* USART 1 Baud Rate 1 */#define RXBUF_1 U1RXBUF /* USART 1 Receive Buffer */#define TXBUF_1 U1TXBUF /* USART 1 Transmit Buffer */#define UCTL_1_ U1CTL_ /* USART 1 Control */#define UTCTL_1_ U1TCTL_ /* USART 1 Transmit Control */#define URCTL_1_ U1RCTL_ /* USART 1 Receive Control */#define UMCTL_1_ U1MCTL_ /* USART 1 Modulation Control */ #define UBR0_1_ U1BR0_ /* USART 1 Baud Rate 0 */#define UBR1_1_ U1BR1_ /* USART 1 Baud Rate 1 */#define RXBUF_1_ U1RXBUF_ /* USART 1 Receive Buffer */#define TXBUF_1_ U1TXBUF_ /* USART 1 Transmit Buffer *//************************************************************* Timer A3************************************************************/#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */#define TAIV_ (0x012Eu) /* Timer A Interrupt Vector Word */READ_ONL Y DEFW( TAIV , TAIV_)#define TACTL_ (0x0160u) /* Timer A Control */DEFW( TACTL , TACTL_)#define TACCTL0_ (0x0162u) /* Timer A Capture/Compare Control 0 */ DEFW( TACCTL0 , TACCTL0_)#define TACCTL1_ (0x0164u) /* Timer A Capture/Compare Control 1 */ DEFW( TACCTL1 , TACCTL1_)#define TACCTL2_ (0x0166u) /* Timer A Capture/Compare Control 2 */ DEFW( TACCTL2 , TACCTL2_)#define TAR_ (0x0170u) /* Timer A Counter Register */DEFW( TAR , TAR_)#define TACCR0_ (0x0172u) /* Timer A Capture/Compare 0 */DEFW( TACCR0 , TACCR0_)#define TACCR1_ (0x0174u) /* Timer A Capture/Compare 1 */DEFW( TACCR1 , TACCR1_)#define TACCR2_ (0x0176u) /* Timer A Capture/Compare 2 */DEFW( TACCR2 , TACCR2_)/* Alternate register names */#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 *//* Alternate register names - 5xx style */#define TA0IV TAIV /* Timer A Interrupt Vector Word */#define TA0CTL TACTL /* Timer A Control */#define TA0CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */#define TA0CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */#define TA0CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */#define TA0R TAR /* Timer A Counter Register */#define TA0CCR0 TACCR0 /* Timer A Capture/Compare 0 */#define TA0CCR1 TACCR1 /* Timer A Capture/Compare 1 */#define TA0CCR2 TACCR2 /* Timer A Capture/Compare 2 */#define TA0IV_ TAIV_ /* Timer A Interrupt Vector Word */#define TA0CTL_ TACTL_ /* Timer A Control */#define TA0CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */#define TA0CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */#define TA0CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */#define TA0R_ TAR_ /* Timer A Counter Register */#define TA0CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */#define TA0CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */#define TA0CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */#define TIMER0_A1_VECTOR TIMERA1_VECTOR /* Int. Vector: Timer A CC1-2, TA */ #define TIMER0_A0_VECTOR TIMERA0_VECTOR /* Int. Vector: Timer A CC0 */#define TASSEL1 (0x0200u) /* Timer A clock source select 1 */#define TASSEL0 (0x0100u) /* Timer A clock source select 0 */#define ID1 (0x0080u) /* Timer A clock input divider 1 */#define ID0 (0x0040u) /* Timer A clock input divider 0 */#define MC1 (0x0020u) /* Timer A mode control 1 */#define MC0 (0x0010u) /* Timer A mode control 0 */#define TACLR (0x0004u) /* Timer A counter clear */#define TAIE (0x0002u) /* Timer A counter interrupt enable */#define TAIFG (0x0001u) /* Timer A counter interrupt flag */#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */#define CM1 (0x8000u) /* Capture mode 1 */#define CM0 (0x4000u) /* Capture mode 0 */#define CCIS1 (0x2000u) /* Capture input select 1 */#define CCIS0 (0x1000u) /* Capture input select 0 */#define SCS (0x0800u) /* Capture sychronize */#define SCCI (0x0400u) /* Latched capture signal (read) */#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */#define OUTMOD2 (0x0080u) /* Output mode 2 */#define OUTMOD1 (0x0040u) /* Output mode 1 */#define OUTMOD0 (0x0020u) /* Output mode 0 */#define CCIE (0x0010u) /* Capture/compare interrupt enable */#define CCI (0x0008u) /* Capture input signal (read) */#define OUT (0x0004u) /* PWM Output signal if output mode 0 */#define COV (0x0002u) /* Capture/compare overflow flag */#define CCIFG (0x0001u) /* Capture/compare interrupt flag */#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges *//* TA3IV Definitions */#define TAIV_NONE (0x0000u) /* No Interrupt pending */#define TAIV_TACCR1 (0x0002u) /* TACCR1_CCIFG */#define TAIV_TACCR2 (0x0004u) /* TACCR2_CCIFG */#define TAIV_6 (0x0006u) /* Reserved */#define TAIV_8 (0x0008u) /* Reserved */#define TAIV_TAIFG (0x000Au) /* TAIFG *//************************************************************* Timer B7************************************************************/#define __MSP430_HAS_TB7__ /* Definition to show that Module is available */#define TBIV_ (0x011Eu) /* Timer B Interrupt Vector Word */READ_ONL Y DEFW( TBIV , TBIV_)#define TBCTL_ (0x0180u) /* Timer B Control */DEFW( TBCTL , TBCTL_)#define TBCCTL0_ (0x0182u) /* Timer B Capture/Compare Control 0 */ DEFW( TBCCTL0 , TBCCTL0_)#define TBCCTL1_ (0x0184u) /* Timer B Capture/Compare Control 1 */ DEFW( TBCCTL1 , TBCCTL1_)#define TBCCTL2_ (0x0186u) /* Timer B Capture/Compare Control 2 */ DEFW( TBCCTL2 , TBCCTL2_)#define TBCCTL3_ (0x0188u) /* Timer B Capture/Compare Control 3 */ DEFW( TBCCTL3 , TBCCTL3_)#define TBCCTL4_ (0x018Au) /* Timer B Capture/Compare Control 4 */ DEFW( TBCCTL4 , TBCCTL4_)#define TBCCTL5_ (0x018Cu) /* Timer B Capture/Compare Control 5 */ DEFW( TBCCTL5 , TBCCTL5_)#define TBCCTL6_ (0x018Eu) /* Timer B Capture/Compare Control 6 */ DEFW( TBCCTL6 , TBCCTL6_)#define TBR_ (0x0190u) /* Timer B Counter Register */DEFW( TBR , TBR_)#define TBCCR0_ (0x0192u) /* Timer B Capture/Compare 0 */DEFW( TBCCR0 , TBCCR0_)#define TBCCR1_ (0x0194u) /* Timer B Capture/Compare 1 */DEFW( TBCCR1 , TBCCR1_)#define TBCCR2_ (0x0196u) /* Timer B Capture/Compare 2 */DEFW( TBCCR2 , TBCCR2_)#define TBCCR3_ (0x0198u) /* Timer B Capture/Compare 3 */DEFW( TBCCR3 , TBCCR3_)#define TBCCR4_ (0x019Au) /* Timer B Capture/Compare 4 */DEFW( TBCCR4 , TBCCR4_)#define TBCCR5_ (0x019Cu) /* Timer B Capture/Compare 5 */DEFW( TBCCR5 , TBCCR5_)#define TBCCR6_ (0x019Eu) /* Timer B Capture/Compare 6 */DEFW( TBCCR6 , TBCCR6_)/* Alternate register names - 5xx style */#define TB0IV TBIV /* Timer B Interrupt Vector Word */#define TB0CTL TBCTL /* Timer B Control */#define TB0CCTL0 TBCCTL0 /* Timer B Capture/Compare Control 0 */ #define TB0CCTL1 TBCCTL1 /* Timer B Capture/Compare Control 1 */ #define TB0CCTL2 TBCCTL2 /* Timer B Capture/Compare Control 2 */ #define TB0CCTL3 TBCCTL3 /* Timer B Capture/Compare Control 3 */ #define TB0CCTL4 TBCCTL4 /* Timer B Capture/Compare Control 4 */ #define TB0CCTL5 TBCCTL5 /* Timer B Capture/Compare Control 5 */ #define TB0CCTL6 TBCCTL6 /* Timer B Capture/Compare Control 6 */ #define TB0R TBR /* Timer B Counter Register */#define TB0CCR0 TBCCR0 /* Timer B Capture/Compare 0 */#define TB0CCR1 TBCCR1 /* Timer B Capture/Compare 1 */#define TB0CCR2 TBCCR2 /* Timer B Capture/Compare 2 */#define TB0CCR3 TBCCR3 /* Timer B Capture/Compare 3 */#define TB0CCR4 TBCCR4 /* Timer B Capture/Compare 4 */#define TB0CCR5 TBCCR5 /* Timer B Capture/Compare 5 */#define TB0CCR6 TBCCR6 /* Timer B Capture/Compare 6 */#define TB0IV_ TBIV_ /* Timer B Interrupt Vector Word */#define TB0CTL_ TBCTL_ /* Timer B Control */#define TB0CCTL0_ TBCCTL0_ /* Timer B Capture/Compare Control 0 */ #define TB0CCTL1_ TBCCTL1_ /* Timer B Capture/Compare Control 1 */ #define TB0CCTL2_ TBCCTL2_ /* Timer B Capture/Compare Control 2 */ #define TB0CCTL3_ TBCCTL3_ /* Timer B Capture/Compare Control 3 */ #define TB0CCTL4_ TBCCTL4_ /* Timer B Capture/Compare Control 4 */ #define TB0CCTL5_ TBCCTL5_ /* Timer B Capture/Compare Control 5 */ #define TB0CCTL6_ TBCCTL6_ /* Timer B Capture/Compare Control 6 */ #define TB0R_ TBR_ /* Timer B Counter Register */#define TB0CCR0_ TBCCR0_ /* Timer B Capture/Compare 0 */#define TB0CCR1_ TBCCR1_ /* Timer B Capture/Compare 1 */#define TB0CCR2_ TBCCR2_ /* Timer B Capture/Compare 2 */#define TB0CCR3_ TBCCR3_ /* Timer B Capture/Compare 3 */#define TB0CCR4_ TBCCR4_ /* Timer B Capture/Compare 4 */#define TB0CCR5_ TBCCR5_ /* Timer B Capture/Compare 5 */#define TB0CCR6_ TBCCR6_ /* Timer B Capture/Compare 6 */#define TBCLGRP1 (0x4000u) /* Timer B Compare latch load group 1 */ #define TBCLGRP0 (0x2000u) /* Timer B Compare latch load group 0 */ #define CNTL1 (0x1000u) /* Counter lenght 1 */#define CNTL0 (0x0800u) /* Counter lenght 0 */#define TBSSEL1 (0x0200u) /* Clock source 1 */#define TBSSEL0 (0x0100u) /* Clock source 0 */#define TBCLR (0x0004u) /* Timer B counter clear */#define TBIE (0x0002u) /* Timer B interrupt enable */#define TBIFG (0x0001u) /* Timer B interrupt flag */#define SHR1 (0x4000u) /* Timer B Compare latch load group 1 */ #define SHR0 (0x2000u) /* Timer B Compare latch load group 0 */#define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */#define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */#define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */#define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */#define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */#define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */#define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */#define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */。
MSP430x14x系列单片机头文件注释
MSP430x14x系列单片机头文件注释MSP430F149单片机的头文件详细的注释#ifndef__msp430x14x_h#define__msp430x14x_h/************************************************************ *STANDARD BITS************************************************************/ #define BIT00x0001#define BIT10x0002#define BIT20x0004#define BIT30x0008#define BIT40x0010#define BIT50x0020#define BIT60x0040#define BIT70x0080#define BIT80x0100#define BIT90x0200#define BITA0x0400#define BITB0x0800#define BITC0x1000#define BITD0x2000#define BITE0x4000#define BITF0x8000/************************************************************ *STATUS REGISTER BITS************************************************************/ #define C0x0001#define Z0x0002#define N0x0004#define V0x0100#define GIE0x0008#define CPUOFF0x0010#define OSCOFF0x0020#define SCG00x0040#define SCG10x0080/*Low Power Modes coded with Bits4-7in SR*/#ifndef__IAR_SYSTEMS_ICC/*Begin#defines for assembler*/ #define LPM0CPUOFF#define LPM1SCG0+CPUOFF#define LPM2SCG1+CPUOFF#define LPM3SCG1+SCG0+CPUOFF#define LPM4SCG1+SCG0+OSCOFF+CPUOFF/*End#defines for assembler*/#else/*Begin#defines for C*/#define LPM0_bits CPUOFF#define LPM1_bits SCG0+CPUOFF#define LPM2_bits SCG1+CPUOFF#define LPM3_bits SCG1+SCG0+CPUOFF#define LPM4_bits SCG1+SCG0+OSCOFF+CPUOFF#include#define LPM0_BIS_SR(LPM0_bits)/*Enter Low Power Mode0*/#define LPM0_EXIT_BIC_SR(LPM0_bits)/*Exit Low Power Mode0*/#define LPM1_BIS_SR(LPM1_bits)/*Enter Low Power Mode1*/#define LPM1_EXIT_BIC_SR(LPM1_bits)/*Exit Low Power Mode1*/#define LPM2_BIS_SR(LPM2_bits)/*Enter Low PowerMode2*/#define LPM2_EXIT_BIC_SR(LPM2_bits)/*Exit Low Power Mode2*/#define LPM3_BIS_SR(LPM3_bits)/*Enter Low Power Mode3*/#define LPM3_EXIT_BIC_SR(LPM3_bits)/*Exit Low Power Mode3*/#define LPM4_BIS_SR(LPM4_bits)/*Enter Low Power Mode4*/#define LPM4_EXIT_BIC_SR(LPM4_bits)/*Exit Low Power Mode4*/#endif/*End#defines for C*//************************************************************ *PERIPHERAL FILE MAP************************************************************/ /************************************************************ *特殊功能寄存器地址和控制位************************************************************/ /*中断使能1*/#define IE1_0x0000sfrb IE1=IE1_;#define WDTIE0x01/*看门狗中断使能*/#define OFIE0x02/*外部晶振故障中断使能*/#define NMIIE0x10/*非屏蔽中断使能*/#define ACCVIE0x20/*可屏蔽中断使能/flash写中断错误*/ #define URXIE00x40/*串口0接收中断使能*/#define UTXIE00x80/*串口0发送中断使能*//*中断标志1*/#define IFG1_0x0002sfrb IFG1=IFG1_;#define WDTIFG0x01/*看门狗中断标志*/#define OFIFG0x02/*外部晶振故障中断标志*/#define NMIIFG0x10/*非屏蔽中断标志*/#define URXIFG00x40/*串口0接收中断标志*/#define UTXIFG00x80/*串口0发送中断标志*//*中断模式使能1*/#define ME1_0x0004sfrb ME1=ME1_;#define URXE00x40/*串口0接收中断模式使能*/#define USPIE00x40/*同步中断模式使能*/#define UTXE00x80/*串口0发送中断模式使能*//*中断使能2*/#define IE2_0x0001sfrb IE2=IE2_;#define URXIE10x10/*串口1接收中断使能*/#define UTXIE10x20/*串口1发送中断使能*//*中断标志2*/#define IFG2_0x0003sfrb IFG2=IFG2_;#define URXIFG10x10/*串口1接收中断标志*/#define UTXIFG10x20/*串口1发送中断标志*//*中断模式使能2*/#define ME2_0x0005sfrb ME2=ME2_;#define URXE10x10/*串口1接收中断模式使能*/ #define USPIE10x10/*同步中断模式使能*/#define UTXE10x20/*串口1发送中断模式使能*//************************************************************ *看门狗定时器的寄存器定义************************************************************/#define WDTCTL_0x0120sfrw WDTCTL=WDTCTL_;#define WDTIS00x0001/*选择WDTCNT的四个输出端之一*/ #define WDTIS10x0002/*选择WDTCNT的四个输出端之一*/ #define WDTSSEL0x0004/*选择WDTCNT的时钟源*/#define WDTCNTCL0x0008/*清除WDTCNT端:为1时从0开始计数*/#define WDTTMSEL0x0010/*选择模式0:看门狗模式;1:定时器模式*/#define WDTNMI0x0020/*选择NMI/RST引脚功能0:为RST;1:为NMI*/#define WDTNMIES0x0040/*WDTNMI=1时.选择触发延0:为上升延1:为下降延*/#define WDTHOLD0x0080/*停止看门狗定时器工作0:启动;1:停止*/#define WDTPW0x5A00/*写密码:高八位*//*SMCLK=1MHz定时器模式*/#defineWDT_MDLY_32WDTPW+WDTTMSEL+WDTCNTCL/* TSMCLK*2POWER15=32ms复位状态*/#defineWDT_MDLY_8WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0/* TSMCLK*2POWER13=8.192ms"*/#defineWDT_MDLY_0_5WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms"*/#defineWDT_MDLY_0_064WDTPW+WDTTMSEL+WDTCNTCL+WDTI S1+WDTIS0/* TSMCLK*2POWER6=0.512ms"*//*ACLK=32.768KHz定时器模式*/#defineWDT_ADLY_1000WDTPW+WDTTMSEL+WDTCNTCL+WDTSS EL/* TACLK*2POWER15=1000ms"*/#defineWDT_ADLY_250WDTPW+WDTTMSEL+WDTCNTCL+WDTSSE L+WDTIS0/* TACLK*2POWER13=250ms"*/#defineWDT_ADLY_16WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL +WDTIS1/* TACLK*2POWER9=16ms"*/#defineWDT_ADLY_1_9WDTPW+WDTTMSEL+WDTCNTCL+WDTSSE L+WDTIS1+WDTIS0/* TACLK*2POWER6=1.9ms"*//*SMCLK=1MHz看门狗模式*/#defineWDT_MRST_32WDTPW+WDTCNTCL/*TSMCLK*2POWER15=32ms复位状态*/#defineWDT_MRST_8WDTPW+WDTCNTCL+WDTIS0/*TSMCLK*2POWER13=8.192ms"*/#defineWDT_MRST_0_5WDTPW+WDTCNTCL+WDTIS1/* TSMCLK*2POWER9=0.512ms"*/#defineWDT_MRST_0_064WDTPW+WDTCNTCL+WDTIS1+WDTIS0/ * TSMCLK*2POWER6=0.512ms"*//*ACLK=32KHz看门狗模式*/#defineWDT_ARST_1000WDTPW+WDTCNTCL+WDTSSEL/* TACLK*2POWER15=1000ms"*/#defineWDT_ARST_250WDTPW+WDTCNTCL+WDTSSEL+WDTIS0/* TACLK*2POWER13=250ms"*/#defineWDT_ARST_16WDTPW+WDTCNTCL+WDTSSEL+WDTIS1/* TACLK*2POWER9=16ms"*/#defineWDT_ARST_1_9WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+ WDTIS0/* TACLK*2POWER6=1.9ms"*//************************************************************ 硬件乘法器的寄存器定义************************************************************/ #define MPY_0x0130/*无符号乘法*/sfrw MPY=MPY_;#define MPYS_0x0132/*有符号乘法*/sfrw MPYS=MPYS_;#define MAC_0x0134/*无符号乘加*/sfrw MAC=MAC_;#define MACS_0x0136/*有符号乘加*/sfrw MACS=MACS_;#define OP2_0x0138/*第二乘数*/sfrw OP2=OP2_;#define RESLO_0x013A/*低6位结果寄存器*/sfrw RESLO=RESLO_;#define RESHI_0x013C/*高6位结果寄存器*/sfrw RESHI=RESHI_;#define SUMEXT_0x013E/*结果扩展寄存器*/const sfrw SUMEXT=SUMEXT_;/************************************************************ *DIGITAL I/O Port1/2寄存器定义有中断功能************************************************************/#define P1IN_0x0020/*P1输入寄存器*/const sfrb P1IN=P1IN_;#define P1OUT_0x0021/*P1输出寄存器*/sfrb P1OUT=P1OUT_;#define P1DIR_0x0022/*P1方向选择寄存器*/sfrb P1DIR=P1DIR_;#define P1IFG_0x0023/*P1中断标志寄存器*/sfrb P1IFG=P1IFG_;#define P1IES_0x0024/*P1中断边沿选择寄存器*/ sfrb P1IES=P1IES_;#define P1IE_0x0025/*P1中断使能寄存器*/sfrb P1IE=P1IE_;#define P1SEL_0x0026/*P1功能选择寄存器*/sfrb P1SEL=P1SEL_;#define P2IN_0x0028/*P2输入寄存器*/const sfrb P2IN=P2IN_;#define P2OUT_0x0029/*P2输出寄存器*/sfrb P2OUT=P2OUT_;#define P2DIR_0x002A/*P2方向选择寄存器*/sfrb P2DIR=P2DIR_;#define P2IFG_0x002B/*P2中断标志寄存器*/sfrb P2IFG=P2IFG_;#define P2IES_0x002C/*P2中断边沿选择寄存器*/ sfrb P2IES=P2IES_;#define P2IE_0x002D/*P2中断使能寄存器*/sfrb P2IE=P2IE_;#define P2SEL_0x002E/*P2功能选择寄存器*/sfrb P2SEL=P2SEL_;/************************************************************ *DIGITAL I/O Port3/4寄存器定义无中断功能************************************************************/ #define P3IN_0x0018/*P3输入寄存器*/const sfrb P3IN=P3IN_;#define P3OUT_0x0019/*P3输出寄存器*/sfrb P3OUT=P3OUT_;#define P3DIR_0x001A/*P3方向选择寄存器*/sfrb P3DIR=P3DIR_;#define P3SEL_0x001B/*P3功能选择寄存器*/sfrb P3SEL=P3SEL_;#define P4IN_0x001C/*P4输入寄存器*/const sfrb P4IN=P4IN_;#define P4OUT_0x001D/*P4输出寄存器*/sfrb P4OUT=P4OUT_;#define P4DIR_0x001E/*P4方向选择寄存器*/sfrb P4DIR=P4DIR_;#define P4SEL_0x001F/*P4功能选择寄存器*/sfrb P4SEL=P4SEL_;/************************************************************ *DIGITAL I/O Port5/6I/O口寄存器定义PORT5和6无中断功能************************************************************/ #define P5IN_0x0030/*P5输入寄存器*/const sfrb P5IN=P5IN_;#define P5OUT_0x0031/*P5输出寄存器*/sfrb P5OUT=P5OUT_;#define P5DIR_0x0032/*P5方向选择寄存器*/sfrb P5DIR=P5DIR_;#define P5SEL_0x0033/*P5功能选择寄存器*/sfrb P5SEL=P5SEL_;#define P6IN_0x0034/*P6输入寄存器*/const sfrb P6IN=P6IN_;#define P6OUT_0x0035/*P6输出寄存器*/sfrb P6OUT=P6OUT_;#define P6DIR_0x0036/*P6方向选择寄存器*/sfrb P6DIR=P6DIR_;#define P6SEL_0x0037/*P6功能选择寄存器*/sfrb P6SEL=P6SEL_;/************************************************************ *USART串口寄存器"UCTL","UTCTL","URCTL"定义的各个位可串口1串口2公用************************************************************/ /*UCTL串口控制寄存器*/#define PENA0x80/*校验允许位*/#define PEV0x40/*偶校验为0时为奇校验*/#define SPB0x20/*停止位为2为0时停止位为1*/#define CHAR0x10/*数据位为8位为0时数据位为7位*/#define LISTEN0x08/*自环模式(发数据同时在把发的数据接收回来)*/#define SYNC0x04/*同步模式为0异步模式*/#define MM0x02/*为1时地址位多机协议(异步)主机模式(同步);为0时线路空闲多机协议(异步)从机模式(同步)*/#define SWRST0x01/*控制位*//*UTCTL串口发送控制寄存器*/#define CKPH0x80/*时钟相位控制位(只同步方式用)为1时时钟UCLK延时半个周期*/#define CKPL0x40/*时钟极性控制位为1时异步与UCLK 相反;同步下降延有效*/#define SSEL10x20/*时钟源选择位:与SSEL0组合为0,1,2,3四种方式*/#define SSEL00x10/*"0"选择外部时钟,"1"选择辅助时钟,"2","3"选择系统子时钟*/#define URXSE0x08/*接收触发延控制位(只在异步方式下用)*/ #define TXWAKE0x04/*多处理器通信传送控制位(只在异步方式下用)*/#define STC0x02/*外部引脚STE选择位为0时为4线模式为1时为3线模式*/#define TXEPT0x01/*发送器空标志*//*URCTL串口接收控制寄存器同步模式下只用两位:FE和OE*/ #define FE0x80/*帧错标志*/#define PE0x40/*校验错标志位*/#define OE0x20/*溢出标志位*/#define BRK0x10/*打断检测位*/#define URXEIE0x08/*接收出错中断允许位*/#define URXWIE0x04/*接收唤醒中断允许位*/#define RXWAKE0x02/*接收唤醒检测位*/#define RXERR0x01/*接收错误标志位*//************************************************************ *USART0串口0寄存器定义************************************************************/ #define U0CTL_0x0070/*串口0基本控制寄存器*/sfrb U0CTL=U0CTL_;#define U0TCTL_0x0071/*串口0发送控制寄存器*/sfrb U0TCTL=U0TCTL_;#define U0RCTL_0x0072/*串口0接收控制寄存器*/sfrb U0RCTL=U0RCTL_;#define U0MCTL_0x0073/*波特率调整寄存器*/sfrb U0MCTL=U0MCTL_;#define U0BR0_0x0074/*波特率选择寄存器0*/sfrb U0BR0=U0BR0_;#define U0BR1_0x0075/*波特率选择寄存器1*/sfrb U0BR1=U0BR1_;#define U0RXBUF_0x0076/*接收缓存寄存器*/const sfrb U0RXBUF=U0RXBUF_;#define U0TXBUF_0x0077/*发送缓存寄存器*/sfrb U0TXBUF=U0TXBUF_;/*改变的寄存器名定义*/#define UCTL0_0x0070/*UART0Control*/sfrb UCTL0=UCTL0_;#define UTCTL0_0x0071/*UART0Transmit Control*/ sfrb UTCTL0=UTCTL0_;#define URCTL0_0x0072/*UART0Receive Control*/ sfrb URCTL0=URCTL0_;#define UMCTL0_0x0073/*UART0Modulation Control*/ sfrb UMCTL0=UMCTL0_;#define UBR00_0x0074/*UART0Baud Rate0*/sfrb UBR00=UBR00_;#define UBR10_0x0075/*UART0Baud Rate1*/sfrb UBR10=UBR10_;#define RXBUF0_0x0076/*UART0Receive Buffer*/ const sfrb RXBUF0=RXBUF0_;#define TXBUF0_0x0077/*UART0Transmit Buffer*/ sfrb TXBUF0=TXBUF0_;#define UCTL_0_0x0070/*UART0Control*/sfrb UCTL_0=UCTL_0_;#define UTCTL_0_0x0071/*UART0Transmit Control*/ sfrb UTCTL_0=UTCTL_0_;#define URCTL_0_0x0072/*UART0Receive Control*/ sfrb URCTL_0=URCTL_0_;#define UMCTL_0_0x0073/*UART0Modulation Control*/ sfrb UMCTL_0=UMCTL_0_;#define UBR0_0_0x0074/*UART0Baud Rate0*/sfrb UBR0_0=UBR0_0_;#define UBR1_0_0x0075/*UART0Baud Rate1*/sfrb UBR1_0=UBR1_0_;#define RXBUF_0_0x0076/*UART0Receive Buffer*/ const sfrb RXBUF_0=RXBUF_0_;#define TXBUF_0_0x0077/*UART0Transmit Buffer*/sfrb TXBUF_0=TXBUF_0_;/************************************************************ *USART1串口1寄存器定义************************************************************/ #define U1CTL_0x0078/*串口1基本控制寄存器*/sfrb U1CTL=U1CTL_;#define U1TCTL_0x0079/*串口1发送控制寄存器*/sfrb U1TCTL=U1TCTL_;#define U1RCTL_0x007A/*串口1接收控制寄存器*/sfrb U1RCTL=U1RCTL_;#define U1MCTL_0x007B/*波特率调整控制寄存器*/sfrb U1MCTL=U1MCTL_;#define U1BR0_0x007C/*波特率选择寄存器0*/sfrb U1BR0=U1BR0_;#define U1BR1_0x007D/*波特率选择寄存器1*/sfrb U1BR1=U1BR1_;#define U1RXBUF_0x007E/*接收缓存*/const sfrb U1RXBUF=U1RXBUF_;#define U1TXBUF_0x007F/*发送缓存*/sfrb U1TXBUF=U1TXBUF_;/*改变的寄存器名定义*/#define UCTL1_0x0078/*UART1Control*/sfrb UCTL1=UCTL1_;#define UTCTL1_0x0079/*UART1Transmit Control*/ sfrbUTCTL1=UTCTL1_;#define URCTL1_0x007A/*UART1Receive Control*/ sfrb URCTL1=URCTL1_;#define UMCTL1_0x007B/*UART1Modulation Control*/ sfrb UMCTL1=UMCTL1_;#define UBR01_0x007C/*UART1Baud Rate0*/sfrb UBR01=UBR01_;#define UBR11_0x007D/*UART1Baud Rate1*/sfrb UBR11=UBR11_;#define RXBUF1_0x007E/*UART1Receive Buffer*/ const sfrb RXBUF1=RXBUF1_;#define TXBUF1_0x007F/*UART1Transmit Buffer*/ sfrb TXBUF1=TXBUF1_;#define UCTL_1_0x0078/*UART1Control*/sfrb UCTL_1=UCTL_1_;#define UTCTL_1_0x0079/*UART1Transmit Control*/sfrb UTCTL_1=UTCTL_1_;#define URCTL_1_0x007A/*UART1Receive Control*/sfrb URCTL_1=URCTL_1_;#define UMCTL_1_0x007B/*UART1Modulation Control*/sfrb UMCTL_1=UMCTL_1_;#define UBR0_1_0x007C/*UART1Baud Rate0*/sfrb UBR0_1=UBR0_1_;#define UBR1_1_0x007D/*UART1Baud Rate1*/sfrb UBR1_1=UBR1_1_;#define RXBUF_1_0x007E/*UART1Receive Buffer*/const sfrb RXBUF_1=RXBUF_1_;#define TXBUF_1_0x007F/*UART1Transmit Buffer*/sfrb TXBUF_1=TXBUF_1_;/*************************************************************Timer A定时器A寄存器定义************************************************************/ #define TAIV_0x012E/*Timer A中断向量寄存器*/sfrw TAIV=TAIV_;#define TACTL_0x0160/*Timer A控制寄存器*/sfrw TACTL=TACTL_;#define TACCTL0_0x0162/*Timer A捕获/比较控制寄存器0*/ sfrw TACCTL0=TACCTL0_;#define TACCTL1_0x0164/*Timer A捕获/比较控制寄存器1*/ sfrw TACCTL1=TACCTL1_;#define TACCTL2_0x0166/*Timer A捕获/比较控制寄存器2*/ sfrw TACCTL2=TACCTL2_;#define TAR_0x0170/*Timer A16位计数器内容*/sfrw TAR=TAR_;#define TACCR0_0x0172/*Timer A捕获/比较寄存器0*/sfrw TACCR0=TACCR0_;#define TACCR1_0x0174/*Timer A捕获/比较寄存器1*/sfrw TACCR1=TACCR1_;#define TACCR2_0x0176/*Timer A捕获/比较寄存器2*/sfrw TACCR2=TACCR2_;/*改变的寄存器名定义*/#define CCTL0_0x0162/*Timer A Capture/Compare Control0*/sfrw CCTL0=CCTL0_;#define CCTL1_0x0164/*Timer A Capture/Compare Control1*/sfrw CCTL1=CCTL1_;#define CCTL2_0x0166/*Timer A Capture/Compare Control2*/sfrw CCTL2=CCTL2_;#define CCR0_0x0172/*Timer A Capture/Compare0*/ sfrw CCR0=CCR0_;#define CCR1_0x0174/*Timer A Capture/Compare1*/ sfrw CCR1=CCR1_;#define CCR2_0x0176/*Timer A Capture/Compare2*/ sfrw CCR2=CCR2_;/*TACTL控制寄存器16个位寄存器定义*/#define TASSEL20x0400/*未用*/#define TASSEL10x0200/*时钟输入源控制位1*/#define TASSEL00x0100/*时钟输入源控制位0*/#define ID10x0080/*分频系数选择位1*/#define ID00x0040/*分频系数选择位0*/#define MC10x0020/*计数模式控制位1*/#define MC00x0010/*计数模式控制位0*/#define TACLR0x0004/*置1位清除定时器*/#define TAIE0x0002/*定时器中断允许*/#define TAIFG0x0001/*定时器中断标志*/#define MC_000*0x10/*停止模式*/#define MC_101*0x10/*增计数模式*/#define MC_202*0x10/*连续计数模式*/#define MC_303*0x10/*增/减计数模式*/#define ID_000*0x40/*直通*/#define ID_101*0x40/*2分频*/#define ID_202*0x40/*4分频*/#define ID_303*0x40/*8分频*/#define TASSEL_000*0x100/*时钟源为TACLK*/#define TASSEL_101*0x100/*时钟源为ACLK*/#define TASSEL_202*0x100/*时钟源为SMCLK*/#define TASSEL_303*0x100/*时钟源为INCLK*//*Timer A,Timer B可公用捕获/比较控制寄存器X*/#define CM10x8000/*捕获模式选择位1*/#define CM00x4000/*捕获模式选择位0*/#define CCIS10x2000/*捕获输入信号源选择位1*/#define CCIS00x1000/*捕获输入信号源选择位0*/#define SCS0x0800/*信号同步位0:异步捕获;1:同步捕获*/#define SCCI0x0400/*锁存输入信号*/#define CAP0x0100/*模式选择:0:比较模式;1:捕获模式*/#define OUTMOD20x0080/*输出模式选择位2*/#define OUTMOD10x0040/*输出模式选择位1*/#define OUTMOD00x0020/*输出模式选择位0*/#define CCIE0x0010/*中断允许位*/#define CCI0x0008/*读出输入信号源位ccis0\1*/#define OUT0x0004/*输出信号(选择输出模式0)*/#define COV0x0002/*捕获溢出标志*/#define CCIFG0x0001/*中断标志*/#define OUTMOD_00*0x20/*输出模式*/#define OUTMOD_11*0x20/*置位模式*/#define OUTMOD_22*0x20/*翻转/复位模式*/#define OUTMOD_33*0x20/*置位/复位模式*/#define OUTMOD_44*0x20/*翻转模式*/#define OUTMOD_55*0x20/*复位模式*/#define OUTMOD_66*0x20/*翻转/置位模式*/#define OUTMOD_77*0x20/*复位/置位模式*/#define CCIS_00*0x1000/*选择CCIXA为捕获事件的输入信号源*/#define CCIS_11*0x1000/*选择CCIXB为捕获事件的输入信号源*/#define CCIS_22*0x1000/*选择GND为捕获事件的输入信号源*/#define CCIS_33*0x1000/*选择VCC为捕获事件的输入信号源*/#define CM_00*0x4000/*禁止捕获模式*/#define CM_11*0x4000/*上升延捕获模式*/#define CM_22*0x4000/*下降沿捕获模式*/#define CM_33*0x4000/*上升沿和下降沿都捕获模式*//************************************************************ *Timer B定时器B寄存器定义************************************************************/ #define TBIV_0x011E/*中断向量寄存器:BIT1-BIT3有效*/ sfrw TBIV=TBIV_;#define TBCTL_0x0180/*定时器B控制寄存器:全部控制都集中在这*/sfrw TBCTL=TBCTL_;#define TBCCTL0_0x0182/*定时器B捕获/比较控制寄存器0*/ sfrw TBCCTL0=TBCCTL0_;#define TBCCTL1_0x0184/*定时器B捕获/比较控制寄存器1*/ sfrw TBCCTL1=TBCCTL1_;#define TBCCTL2_0x0186/*定时器B捕获/比较控制寄存器2*/ sfrw TBCCTL2=TBCCTL2_;#define TBCCTL3_0x0188/*定时器B捕获/比较控制寄存器3*/ sfrw TBCCTL3=TBCCTL3_;#define TBCCTL4_0x018A/*定时器B捕获/比较控制寄存器4*/ sfrw TBCCTL4=TBCCTL4_;#define TBCCTL5_0x018C/*定时器B捕获/比较控制寄存器5*/ sfrw TBCCTL5=TBCCTL5_;#define TBCCTL6_0x018E/*定时器B捕获/比较控制寄存器6*/ sfrw TBCCTL6=TBCCTL6_;#define TBR_0x0190/*计数器*/sfrw TBR=TBR_;#define TBCCR0_0x0192/*定时器B捕获/比较寄存器0*/sfrw TBCCR0=TBCCR0_;#define TBCCR1_0x0194/*定时器B捕获/比较寄存器1*/sfrw TBCCR1=TBCCR1_;#define TBCCR2_0x0196/*定时器B捕获/比较寄存器2*/sfrw TBCCR2=TBCCR2_;#define TBCCR3_0x0198/*定时器B捕获/比较寄存器3*/sfrw TBCCR3=TBCCR3_;#define TBCCR4_0x019A/*定时器B捕获/比较寄存器4*/sfrw TBCCR4=TBCCR4_;#define TBCCR5_0x019C/*定时器B捕获/比较寄存器5*/sfrw TBCCR5=TBCCR5_;#define TBCCR6_0x019E/*定时器B捕获/比较寄存器6*/sfrw TBCCR6=TBCCR6_;/*定时器B控制寄存器:全部控制都集中在这*/#define SHR10x4000/*装载比较锁存器控制位1:受TBCCTLx 中的CCLDx位控制*/#define SHR00x2000/*装载比较锁存器控制位0:受TBCCTLx 中的CCLDx位控制*/#define TBCLGRP10x4000/*装载比较锁存器控制位1:受TBCCTLx 中的CCLDx位控制*/#define TBCLGRP00x2000/*装载比较锁存器控制位0:受TBCCTLx 中的CCLDx位控制*/#define CNTL10x1000/*定时器位数长度控制位1*/#define CNTL00x0800/*定时器位数长度控制位0*/#define TBSSEL20x0400/*未用*/#define TBSSEL10x0200/*时钟输入源控制位1*/#define TBSSEL00x0100/*时钟输入源控制位0*/#define TBCLR0x0004/*置1清除定时器*/#define TBIE0x0002/*中断允许*/#define TBIFG0x0001/*中断标志*/#define TBSSEL_00*0x0100/*时钟源为:TBCLK*/#define TBSSEL_11*0x0100/*时钟源为:ACLK*/#define TBSSEL_22*0x0100/*时钟源为:SMCLK*/#define TBSSEL_33*0x0100/*时钟源为:INCLK*/#define CNTL_00*0x0800/*16位计数模式*/#define CNTL_11*0x0800/*12位计数模式*/#define CNTL_22*0x0800/*10位计数模式*/#define CNTL_33*0x0800/*8位计数模式*/#define SHR_00*0x2000/*单独装载(初始值)*/#define SHR_11*0x2000/*分三组装载:1-3groups(1-2,3-4, 5-6)*/#define SHR_22*0x2000/*分二组装载:2-2groups(1-3, 4-6)*/#define SHR_33*0x2000/*不分组装载:3-1group(all)*/#define TBCLGRP_00*0x2000/*单独装载(初始值)*/#define TBCLGRP_11*0x2000/*分三组装载:1-3groups(1-2,3-4, 5-6)*/#define TBCLGRP_22*0x2000/*分二组装载:2-2groups(1-3, 4-6)*/#define TBCLGRP_33*0x2000/*不分组装载:3-1group(all)*/ /*Additional Timer B Control Register bits are defined in Timer A*/#define SLSHR10x0400/*Compare latch load source1*/#define SLSHR00x0200/*Compare latch load source0*/#define CLLD10x0400/*定义比较锁存器TBCLx的装载方式控制位1*/#define CLLD00x0200/*定义比较锁存器TBCLx的装载方式控制位0*/#define SLSHR_00*0x0200/*立即装载*/#define SLSHR_11*0x0200/*TBR计数到0时装载*/#define SLSHR_22*0x0200/*在增减模式下,计数到TBCLx或0时装载;在连续计数模式下,计数到0时装载*/#define SLSHR_33*0x0200/*当计数到TBCL0时装载*/#define CLLD_00*0x0200/*立即装载*/#define CLLD_11*0x0200/*TBR计数到0时装载*/#define CLLD_22*0x0200/*在增减模式下,计数到TBCLx或0时装载;在连续计数模式下,计数到0时装载*/#define CLLD_33*0x0200/*当计数到TBCL0时装载*//************************************************************ *Basic Clock Module************************************************************/ #define DCOCTL_0x0056/*DCO时钟频率控制寄存器:复位后的值位060h*/sfrb DCOCTL=DCOCTL_;#define BCSCTL1_0x0057/*系统时钟控制寄存器1:复位后的值位084h*/sfrb BCSCTL1=BCSCTL1_;#define BCSCTL2_0x0058/*系统时钟控制寄存器2:复位后的值位000h*/sfrb BCSCTL2=BCSCTL2_;/*DCO时钟频率控制寄存器*/#define MOD00x01/*DCO插入周期控制位0*/#define MOD10x02/*DCO插入周期控制位1*/#define MOD20x04/*DCO插入周期控制位2*/#define MOD30x08/*DCO插入周期控制位3*/#define MOD40x10/*DCO插入周期控制位4*/#define DCO00x20/*8种频率控制位0*/#define DCO10x40/*8种频率控制位1*/#define DCO20x80/*8种频率控制位2*//*系统时钟控制寄存器1:复位后的值位084h*/#define RSEL00x01/*选择内部电阻控制位0*/#define RSEL10x02/*选择内部电阻控制位1*/#define RSEL20x04/*选择内部电阻控制位2*/#define XT5V0x08/*必须为0*/#define DIVA00x10/*ACLK分频系数控制位0*/#define DIVA10x20/*ACLK分频系数控制位1*/#define XTS0x40/*LFXT1工作模式控制位0:低频模式./ 1:高频模式.*/#define XT2OFF0x80/*XT2CLK使能控制位0:开启;1:关闭*/#define DIVA_00x00/*ACLK分频系数为:1*/#define DIVA_10x10/*ACLK分频系数为:2*/#define DIVA_20x20/*ACLK分频系数为:4*/#define DIVA_30x30/*ACLK分频系数为:8*//*系统时钟控制寄存器2:复位后的值位000h*/#define DCOR0x01/*内外电阻选择控制位*/#define DIVS00x02/*SMCLK分频控制位0*/#define DIVS10x04/*SMCLK分频控制位1*/#define SELS0x08/*SMCLK时钟源选择位t0COCLK/1:XT2CLK/LFXTCLK*/#define DIVM00x10/*MCLK分频控制位0*/#define DIVM10x20/*MCLK分频控制位1*/#define SELM00x40/*MCLK时钟输入源选择位0*/#define SELM10x80/*MCLK时钟输入源选择位1*/#define DIVS_00x00/*SMCLK分频系数为:1*/#define DIVS_10x02/*SMCLK分频系数为:2*/#define DIVS_20x04/*SMCLK分频系数为:4*/#define DIVS_30x06/*SMCLK分频系数为:8*/#define DIVM_00x00/*MCLK分频系数为:1*/#define DIVM_10x10/*MCLK分频系数为:2*/#define DIVM_20x20/*MCLK分频系数为:4*/#define DIVM_30x30/*MCLK分频系数为:8*/#define SELM_00x00/*MCLK时钟输入源:DCOCLK*/#define SELM_10x40/*MCLK时钟输入源:DCOCLK*/#define SELM_20x80/*MCLK时钟输入源:XT2CLK/LFXTCLK*/ #define SELM_30xC0/*MCLK时钟输入源:LFXTCLK*//************************************************************* *Flash Memory FLASH操作寄存器定义*************************************************************/ #define FCTL1_0x0128/*FLASH控制寄存器1:控制编程、擦除*/ sfrw FCTL1=FCTL1_;#define FCTL2_0x012A/*FLASH控制寄存器2：控制时钟分频*/ sfrw FCTL2=FCTL2_;#define FCTL3_0x012C/*FLASH控制寄存器3：状态标志*/ sfrw FCTL3=FCTL3_;#define FRKEY0x9600/*读FLASH密码*/#define FWKEY0xA500/*写FLASH密码*/#define FXKEY0x3300/*for use with XOR instruction*/ /*FLASH控制寄存器1:控制编程、擦除*/#define ERASE0x0002/*擦除段使能*/#define MERAS0x0004/*主存擦除使能*/#define WRT0x0040/*编程使能*/#define BLKWRT0x0080/*段编程使能*//*FLASH控制寄存器2：控制时钟分频*/#define FN_00x0000/*直通*/#define FN_20x0002/*3分频*/ #define FN_30x0003/*4分频*/ #define FN_40x0004/*5分频*/ #define FN_50x0005/*6分频*/ #define FN_60x0006/*7分频*/ #define FN_70x0007/*8分频*/ #define FN_80x0008/*9分频*/ #define FN_90x0009/*10分频*/ #define FN_100x000A/*11分频*/ #define FN_110x000B/*12分频*/ #define FN_120x000C/*13分频*/ #define FN_130x000D/*14分频*/ #define FN_140x000E/*15分频*/ #define FN_150x000F/*16分频*/ #define FN_160x0010/*17分频*/ #defineFN_170x0011/*18分频*/ #define FN_180x0012/*19分频*/ #define FN_190x0013/*20分频*/ #define FN_200x0014/*21分频*/ #define FN_210x0015/*22分频*/ #define FN_220x0016/*23分频*/ #define FN_230x0017/*24分频*/ #define FN_240x0018/*25分频*/ #define FN_250x0019/*26分频*/ #define FN_260x001A/*27分频*/ #define FN_270x001B/*28分频*/ #define FN_280x001C/*29分频*/ #define FN_290x001D/*30分频*/ #define FN_300x001E/*31分频*/ #define FN_310x001F/*32分频*/ #define FN_320x0020/*33分频*/ #define FN_330x0021/*34分频*/ #define FN_340x0022/*35分频*/ #define FN_350x0023/*36分频*/ #define FN_360x0024/*37分频*/ #define FN_370x0025/*38分频*/ #define FN_380x0026/*39分频*/ #define FN_390x0027/*40分频*/ #define FN_400x0028/*41分频*/ #define FN_410x0029/*42分频*/ #define FN_420x002A/*43分频*/ #define FN_430x002B/*44分频*/ #define FN_440x002C/*45分频*/#define FN_460x002E/*47分频*/#define FN_470x002F/*48分频*/#define FN_480x0030/*49分频*/#define FN_490x0031/*50分频*/#define FN_500x0032/*51分频*/#define FN_510x0033/*52分频*/#define FN_520x0034/*53分频*/#define FN_530x0035/*54分频*/#define FN_540x0036/*55分频*/#define FN_550x0037/*56分频*/#define FN_560x0038/*57分频*/#define FN_570x0039/*58分频*/#define FN_580x003A/*59分频*/#define FN_590x003B/*60分频*/#define FN_600x003C/*61分频*/#define FN_610x003D/*62分频*/#define FN_620x003E/*63分频*/#define FN_630x003F/*64分频*/#define FSSEL_00x0000/*Flash时钟选择:ACLK*/#define FSSEL_10x0040/*Flash时钟选择:MCLK*/#define FSSEL_20x0080/*Flash时钟选择:SMCLK*/ #define FSSEL_30x00C0/*Flash时钟选择:SMCLK*/ /*FLASH控制寄存器3：状态标志*/#define BUSY0x0001/*Flash忙标志*/#define KEYV0x0002/*Flash安全键值出错标志*/ #define ACCVIFG0x0004/*Flash非法访问中断标志*/ #define WAIT0x0008/*等待指示信号位*/#define LOCK0x0010/*锁定位*/#define EMEX0x0020/*紧急退出位*//************************************************************ *Comparator A比较器A寄存器定义************************************************************/ #define CACTL1_0x0059/*比较器A控制寄存器1*/ sfrb CACTL1=CACTL1_;#define CACTL2_0x005A/*比较器A控制寄存器2*/ sfrb CACTL2=CACTL2_;#define CAPD_0x005B/*比较器A端口禁止寄存器*/ sfrb CAPD=CAPD_;/*比较器A控制寄存器1*/#define CAIFG0x01/*比较器A中断标志*/#define CAIE0x02/*比较器A中断使能*/。
MSP 430基础IO口
学习过51单片机的同学都知道，IO口的操作是所有单片机系统的基本操作，单片机作为一个核心的运算和处理器件必须能够对外部的信号做出反应，那么如何让MSP430得知外部信号变化和做出反应就是我们今天要学习的主要内容这里还是以MSP430G2553单片机为例MSP430单片机的IO口都有以下几个相关的寄存器：1、PnDIR：输入输出方向寄存器0-输入1-输出2、PnOUT：输出寄存器0-低电平1-高电平3、PnIN：输入寄存器这是一个只读寄存器用来读取外部电平状态4、PnIFG：中断标志寄存器0-没有中断请求1-有中断请求该寄存器有8个标志位，对应相应的引脚是否有待处理的中断请求这8个中断标志共用一个中断向量，中断标志不会自动复位，必须软件复位外部中断时间的时间必须>=1.5倍的MCLK时间以保证中断请求被接受5、PnIE：中断启用寄存器0-不启用中断1-启用中断6、PnIES：中断触发边沿选择寄存器0-上升沿中断1-下降沿中断7、PnSEL：功能选择寄存器0-选择引脚为普通IO口1-选择引脚为外围模块功能（第二功能引脚）8、PnSEL2：功能选择寄存器2和PnSEL共同作用选择不同功能，当选择引脚作为普通IO口使用时PnSEL和PnSEL2都应该清零（默认）9、PnREN：上拉/下拉电阻使能寄存器0-禁止1-使能OK，以上就介绍完了和IO口相关的寄存器，是不是觉得好多，头晕？不过头晕之余看看描述，还是能够理出一些思绪的。
本篇我们只讨论IO作为普通输入输出口使用所以像PnSEL、PnSEL2、PnIE寄存器就直接写入0x00就好了，或者说可以默认不作修改。
像PnIFG 和PnIES寄存器那就和我们本篇完全无关了。
让我们看看MSP430G2553这个单片机的管脚是如何分布的吧，好让大家有个IO口的存在概念：图片太小？符号密密麻麻看不清？OK，cloud用表格给大家划分一下最简单的引脚图：VCC MSP430G2553GNDP1.0P2.6 / XINP1.1P2.7 / XOUTP1.2TESTP1.3/RSTP1.4P1.7P1.5P1.6P2.0P2.5P2.1P2.4P2.2P2.3看了这张图大家应该都明白了我们的MSP430G2553单片机只引出了P1口和P2口。
MSP430模块系列之一：IO操作
MSP430模块系列之一：IO操作4/15/2013 BY francis_haoyinghao1991@ 在淘宝上买的一块开发板，先秀一下：我很喜欢这块开发板,喜欢它的颜色。
看起来很专业。
好了，开始学习了。
好像每一块单片机都是从点亮小灯开始的。
那这个5438也这么做。
首先查看关于IO的寄存器：这是P1口和P2口的寄存器，这两个IO比较特殊，可以作为中断使用，但是目前先不去管中断。
从最简单的开始。
只看能让小灯点亮的寄存器：输入寄存器输入寄存器是只读的，能够读取相应管脚的电平。
但是首先要设置方向寄存器，使其设置为输入。
输出寄存器向引脚写高低电平，下面的关于上/下拉电阻的暂时不用考虑，与输入寄存器一样，如果要实现输出功能必须先设置方向寄存器使之设置为输出。
方向寄存器这就是前面说的方向寄存器，不多解释。
功能选择寄存器手册里没有详细图示这个寄存器。
PXSEL相应位设置为0时，引脚设置为IO口。
PXSEL相应位设置为1时，引脚设置为外围模式，具体功能参见手册。
我们要点亮小灯，就是要输出高低电平。
理论上将功能选择寄存器设置为IO口，方向寄存器选择为输出，之后在输出寄存器中写入0或1就可以输出高低电平，从而点亮小灯了。
但是，我们必须考虑到开发板上电路，因为你要知道哪个管脚和小灯是连接的。
这个是开发板的原理图：这里的LED PWR有开关的作用，低电平有效，低电平时才能给LED供电，而DIGx是单片机的引脚。
在单片机上对应的是这个：LED PWR为P7.3。
DIG1~4分别为P9.0~P0.3。
DIG5~8分别为P1.4~P1.7。
LED PWR为LED模块的开关，还有一个总开关POWER高电平有效。
所以在程序中还要设置这些位。
下面是我的程序：流水灯因为怕程序的格式乱了，以图片的形式展示了。