03_global_time_const_lab

For Academic Use OnlyLab 3: Global Timing Constraints Lab Targeting Spartan-3E Starter KitThis material exempt per Department of Commerce license exception TSUGlobal Timing Constraints LabIntroductionIn this lab, you will specify your timing requirements by entering global timing constraints, andthen analyze the performance of the design using various timing reports. You will complete aPicoBlaze design, simulate it, and test it in hardware.ObjectivesAfter completing this lab, you will be able to:•Enter global timing constraints using the Xilinx Constraints Editor•Review if the timing constraints are realistic using the Post-Map Static Timing Report•Use the if the timing constraints were met Post-Place and Route Static Timing Report ReferencesThe following pieces of documentation may be referenced during the completion of this lab, whichcan be downloaded from the Xilinx web site at •PicoBlaze User Guide•Spartan-3E Data Sheet•Digilent Spartan-3E Board Data Sheet•Platform Flash In-System Programmable Configuration PROMs data sheetDesign DescriptionIn this lab, you will implement an embedded processor system with several peripherals. From ahardware perspective, most of the system is provided for you. You are encouraged to read thehardware description of the system, however, so that you understand it.Figure 3-1. PicoBlaze SystemThe main task for this lab is to write software in PicoBlaze assembly to implement a loopback test.A loopback test is a test in which a signal is sent to a device and returned back from that samedevice as a way to determine whether the device is working correctly.The first loopback test will echo switch settings on LEDs. Here, you are actuating settings withyour fingers, and viewing with your eyes what is looped back by the system. The second loopbacktest will echo serially received data over an RS232 serial port. Here, a desktop computer istransmitting with its serial port, and receiving with its serial port what is looped back by the system.As shown in Figure 1, the system has a number of inputs. There is a clock and a reset input, plus a4-bit switch input and a serial receive input. The serial receive input originates from the RS232connector on the board and passes through a voltage level translator before reaching the FPGAdevice.clk clock signal, 50 MHz from oscillatorrst reset signalrs232_rx serial receive inputswitches[7:0] 8-bit switch inputAlso shown in Figure 1 are the outputs. There is an 8-bit LED output and a serial transmit output.The serial transmit output originates from the FPGA and passes through a voltage level translatorbefore reaching the RS232 connector on the board.rs232_tx serial transmit outputleds[7:0] 8-bit LED outputYou must successfully implement the system from the provided source files, and then develop asmall software program. The software development is split into three parts. Your final softwareimplementation is required to transmit a short message upon reset, and then concurrently performtwo loopback functions:•Echo switch settings on LEDs•Echo serially received data over an RS232 interfaceWhen you successfully complete this lab, you will have gained an understanding of how to usePicoBlaze to implement a simple embedded processor system.ProcedureIn this lab, you will create a simple embedded system and enter the location and global timingconstraints.This lab comprises three primary steps:1.Assemble a PicoBlaze template2.Enter the global timing constraints3.Enter pin location constraints4.Implement the design and analyze the timing5.Create the software and perform an HDL simulation6.Generate a programming file7.Test the design in hardwareBelow each general instruction for a given procedure, you will find accompanying step-by-stepdirections and illustrated figures that provide more detail for performing the general instruction. Ifyou feel confident about a specific instruction, feel free to skip the step-by-step directions and move on to the next general instruction in the procedure.Note: If you are unable to complete the lab at this time, you can download the lab files for thismodule from the Xilinx University Program site at /university Assemble a Program Template Step 1Assemble the program template, program.psm, that will be used to create the loop-back application later in the lab. Next, extend the PicoBlaze design by adding the generated instruction ROM, program.v.Select Start →All Programs→Xilinx ISE Design Suite 12 →ISE Design Tools→Project NavigatorSelect File → Open Project in the Project NavigatorBrowse to one of the following directories:VHDL users: c:\xup\fpgaflow\labs\VHDL\lab3\time_constVerilog users: c:\xup\fpgaflow\labs\Verilog\lab3\time_constSelect time_const.xise, click Open and review the top-level designOpen a command prompt by going to Start All Programs Accessories Command PromptCD to the Assembler sub-directory (located in project directory), which contains a program template (program.psm) and a batch file (assemble.bat) to assemble it> cd c:\xup\fpgaflow\labs\verilogl\lab3\assembler (Verilog users)> cd c:\xup\fpgaflow\labs\vhdl\lab3\assembler (VHDL users)Enter the following command at the prompt to assemble the program template to generate the program ROM:> kcpsm3 programNote: This template is syntactically correct but functionally useless – you will return tocomplete a meaningful program later.In ISE, add the generated ROM HDL file (PROGRAM.vhd/.v) in lab3\assembler to the projectPerform a syntax check by highlighting the top-level design file and double-clicking on Check Syntax under the Synthesis processSwitch to Behavioral Simulation mode and perform a simulation using the testbench.v/vhd, with a stop time of 25000.After zooming in, you should see results similar to the following figure, where a value of hexAA and followed by hex 55 is input on the switches, and no output is present on the LEDs.Later on, you will enter code to echo the switch settings to the LEDs.Figure 3-2. Switch settings do not echo back to LEDsClose the simulation window ending the simulation without saving the runEnter the Global Timing Constraints Step 2In this step, you will use a graphical tool, called the constraints editor, to enterPERIOD (20 ns) and OFFSET IN/OUT (7 ns and 7.5 ns) constraints.In the Hierarchy in Project window, select the top-level design file loopback.vhd/.v and change the mode to Implementation in View windowIn the Processes for Source window, expand User Constraints and double-click Create Timing Constraints (Figure 3-3)Figure 3-3. Processes for Source WindowThe project does not currently have a UCF file associated with it. The Project Navigator willoffer to create one automaticallyClick Yes to have a new UCF file (loopback.ucf) automatically created and added to the projectIn the Constraint Type under Timing Constraints window, select Clock Domains (see Figure 3-4) to list the clock domains in the designFigure 3-4. Timing Constraints EditorDouble-click Clk entry under the Unconstrained Clocks window on right to open the Clock Period dialogueFigure 3-5. Clock Period dialogueAccept the default settings of 20ns (since we have 50 MHz clock source) and 50% duty cycle by clicking OKSelect Inputs in Constraint Type window, and double-click the white space under the Port column in the right side window to invoke the Offset In Wizard. Leave the default settings (System synchronous, SDR, and Rising edge) and click Next after reviewing the description.Note that the PicoBlaze design is using a single clock for the entire design, where all registers are clocked on the rising edgeFigure 3-6. OFFSET IN Wizard – Clock Edge PageEnter the value of 7 ns for OFFSET IN (see Figure 3-7) and click Finish. Note that this design does not have stringent timing requirements for clocking in external data, so a random value of 7 ns was chosenFigure 3-7. OFFSET IN Wizard – Data PageSimilarly, select Outputs in Constraint Type window, and double -click the white space under Port column to invoke the Offset Out Wizard and enter a value of 7.5 ns(see Figure 3-8) forthe Offset Out constraint. Click OK when finishedFigure 3-8. OFFSET OUT constraints dialogueSave the constraints and close the timing constraints editorEnter the Pin Location Constraints Step 3In this section, you will assign locations to the input/output pins of the design bycopying the LOC constraints from a text file into the UCF file.Click to select loopback.ucf and double-click on Edit Constraints (see Figure 3-9) under User Constraints to open the UCF fileFigure 3-9. Open the UCF FileIn the lab3 directory, open pinouts.txt using a utility such as word padCopy the constraints into the UCF file, underneath the timing constraints entered by the constraints editorFigure 3-10. Enter constraints in the UCF FileSave and close the UCF fileImplement the Design and Analyze the Timing Step 4 Implement the design. Look through the Post-Map Static Timing Report and thePost-Place & Route Static Timing Report to complete Chart 1 and Chart 2 in this section.In the Processes for Source window, expand the Implement Design process, and expand the Map processIf you do not see the Implement Design process, make sure that loopback.vhd/.v is selected inthe Hierarchy in Project window.Expand the Generate Post-Map Static Timing process under Map process and double-click on Analyze Post-Map Static TimingPerforming these steps implements the design through MAP, generates the Post-Map StaticTiming Report, and opens the report in the Timing Analyzer. Use the report to verify that yourtiming constraints are realistic and to avoid wasting Place & Route timeComplete the table below by entering the requested and actual values. When entering the PERIOD, look up the constraint that was placed on CLKFX_BUF as this is the DCM outputused to clock the designChart 1 PERIODconstraint OFFSET INconstraintOFFSET OUTconstraintRequestedActualCompare your answers with those in the Answers section of this lab.Exit the Post-Map Timing AnalyzerIn the Processes for Source window, expand the Place & Route processExpand the Generate Post-Place & Route Static Timing process and double-click Analyze Post-Place & Route Static TimingComplete the table below by entering the requested and actual values. When entering the PERIOD, look up the constraint that was placed on CLKFX_BUF as this is the DCM output used to clock the designChart 2 PERIODconstraint OFFSET INconstraintOFFSET OUTconstraintRequestedActualCompare your answers with those in the Answers section of this labNote: If your design does not meet timing after place & route, then loosen the constraint of the failing path and re-run implementation!Exit the Post-Place & Route Timing AnalyzerCreate the Software and Perform HDL Simulation Step 5Now that the hardware meets timing, you will now develop a PicoBlaze assembly program to complete the first of three loop-back tests. The program templatecontains a number of constant definitions for your convenience and is structured so that you can implement each of the three tests independently. You will enterassembly code in the template and run the assembler to re-generate the programmemory files. You will then simulate the design to verify that the DIP switchsettings are echoed on the LED output.Figure 3-11. PicoBlaze loop-back application templateCreate the code necessary to perform a loop back test for Task #1 and assemble it.Once the ROM file has been generated, you will perform a behavioral simulationto test the loop-back application.Write the code for task #1 by editing program.psm in the Assembler subdirectory to read the switch state into a PicoBlaze register and then write the state to the LED control portNote: Refer to the constants in the assembly template for port values and PicoBlazedocumentation for instructions.Hint: You only have to write two lines of code (refer to the KCPSM3 user manual)Once the code has been written, re-assemble the programSwitch to Behavioral Simulation mode and double-click on Simulate Behavioral ModelAnalyze the wave form output (Figure 3-12) and console (Figure 3-13), noting the switch settings echoed on LEDsFigure 3-12. Switch settings echo back to LEDsFigure 3-13. View messages in the Simulation ConsoleClose the window when finished.Generate a Programming File Step 6The Xilinx platform flash PROMs provide a reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Digilent Spartan-3E board is equipped with a 4 Mbit xcf04s platform flash PROM that can easily store abitstream for an xc3s500e, which requires 2,270,208 configuration bits. In thisstep, you will use iMPACT to generate an Intel formated MCS file to program the PROM.In the Hierarchy in Project window, select the top-level design file loopback.vhd/.v and change the mode to Implementation in View window and double-click on Generate Target PROM/ACE File under the Configure Target Device process.ISE will first generate the bitstream and then open the iMPACTDouble-click Create PROM File (PROM File Formatter) to add the iMPACT project file Select Xilinx Flash/PROM ( ) in a Storage Device Type windowunder Step 1, and click to go to Step 2. Select xcf04s from Device and click on Add Storage DeviceFigure 3-14. Selecting Appropriate Flash Deviceclick to go to Step 3Enter lab3 in the Output File Name field, click on folder icon and browse to lab3\time_const folder and click OK. Leave File Format and Add Non-Configuration Data Files fields values unchanged (Figure 3-15). Click OK to continueFigure 3-15. Specify the PROM File Name and LocationClick OK to start adding deviceSelect loopback.bit to add the file and click OKClick No when the dialog opens so you do NOT add another bitstream. Click OKFigure 3-16. Bitstream is now associated with PROMDouble-click on Generate File… in the Processes window to generate the MCS file. Youshould see the following message displayed “Generate Succeeded”Test the Design in Hardware Step 7In this step, you will switch configuration mode and configure the platform flash PROM using the MCS file generated in the last step. You will then configure the FPGA from the PROM and test the loopback application on the Digilent board.Power up and connect the Spartan-3E boardInitialize the chain by double-clicking Boundary-Scan and selecting Initialize Chain afterright-clicking on the white space (Figure 3-17) and click OKDouble-clickAdd the .mcs file to the xcf04s Platform Flash device, bypassing the Spartan-3E and CPLD devices. Click OK to close the Programming Properties dialog box.Program the PROM. Right-click on the xcf04s in the iMPACT window and select Program.Click OK in the Programming Properties dialog box to erase and program the PROM.Verify that the configuration mode jumpers are set so that the bitstream is loaded from the Platform Flash upon power up (consult with Digilent Spartan-3E user guide). Recycle thepower on the Digilent board to reconfigure the Spartan-3E via the platform flash PROM andflip the switches to turn the LEDs on/off.ConclusionIn this lab, you used the Xilinx Constraints Editor to enter the global timing constraints. You alsoreviewed the Post-Map and Post-Place & Route Timing Reports.Timing constraints are the best way to communicate your performance expectations to theimplementation tools.You must verify that your timing constraints are realistic while the implementation tools are placingand routing your design for the first time. You can get an estimate of the timing performance fromthe Post-Map Static Timing Report.After implementation is complete, timing constraints must be verified with the Post-Place & RouteStatic Timing Report or a custom timing report generated by the Timing Analyzer.AnswersLab answers listed represent sample solutions only. Your results may differ depending on the version of the software, service pack, or operating system that you are using.plete the row titled Post-Map in the following chart:Chart 1 PERIODconstraint OFFSET INconstraintOFFSET OUTconstraintRequested 18.18 ns 7 ns 7.5 nsActual (vhdl) Actual (verilog) ~8.05 ns~8.86 ns~3.8 ns~4.6 ns~4.5 ns~4.5 nsplete the row titled Post-P&R in the following chart:Chart 2 PERIODconstraint OFFSET INconstraintOFFSET OUTconstraintRequested 18.18 ns 7 ns 7.5 nsActual (vhdl) Actual (verilog) ~14.38 ns~13.07 ns~5.86 ns~4.96 ns~6.60 ns~6.18 nsA。