AT91SAM7S64学习资料
AT91SAM7S的中断
AT91SAM7S的中断AT91SAM7S的中断2010年07月02日星期五13：11关于中断大体可以这样理解：处理器内核有两个中断接口FIQ(快速中断请求)和IRQ(标准中断请求),而片内高级中断控制器利用这两个接口将外设的中断请求有序的传递到内核。
而如何将多达32个中断请求只用两根线传递到内核呢?这是借助硬件软件两方面的分发处理来完成的。
首先AIC为每一个外设或中断源提供了一个中断源向量寄存器(AIC_SVR0~AICSVR31)，在配置使能相应外设时用户将设备的中断处理函数地址存入对应的源向量寄存器，而当中断请求发生时AIC将对应的源向量寄存器中的地址复制到中断向量寄存器(AIC_IVR)并向内核发出IRQ请求。
以上是硬件实现的中断分发过程，然而在用户程序中也必须做相关处理才能完成IRQ的分发处理，对于内核来讲IRQ只是一个中断向量，当IRQ中断请求时内核会跳到一个固定的地址(即IRQ向量)处理中断，用户程序(ARM的启动代码)必须在这个IRQ中断程序中分发处理才能分辨不同的设备的中断请求，但有了上面这样硬件的预处理过程,软件分发处理变得比较简单，跳到AIC中断向量寄存器中地址处即可，下面具体看一下启动代码：PROGRAM?RESET RSEG INTRAMSTART_REMAP RSEG INTRAMEND_REMAP RSEG ICODE：CODE：ROOT(2)CODE32；Always ARM mode after reset org 0reset BInitReset；0x00 Reset handler undefvec：B undefvec；0x04 Undefined Instruction swivec：B swivec；0x08 Software Interrupt pabtvec：B pabtvec；0x0C Prefetch Abort dabtvec：B dabtvec；0x10 Data Abort rsvdvec：B rsvdvec；0x14 reserved irqvec：；此处是IRQ向量,它是固定的地址B IRQ_Handler_Entry；0x18 IRQ fiqvec：；0x1c FIQFIQ_Handler_Entry：IRQ_Handler_Entry：；IRQ处理例程；-Manage Exception Entry；-Adjust and save LR_irq in IRQ stack sub lr,lr,#4 stmfd sp！,{lr}；-Save SPSR need to be saved for nested interrupt mrs r14,SPSR stmfd sp！,{r14}；-Save and r0 in IRQ stack stmfd sp！,{r0}；-Write in the IVR to support Protect Mode；-No effect in Normal Mode；-De-assert the NIRQ and clear the source in Protect Mode ldr r14,=AT91C_BASE_AIC ldr r0,[r14,#AIC_IVR]str r14,[r14,#AIC_IVR]；-Enable Interrupt and Switch in Supervisor Mode msr CPSR_c,#ARM_MODE_SVC；-Savescratch/used registers and LR in User Stack stmfd sp！,{r1-r3,r12,r14}；-Branch to the routine pointed by the AIC_IVR跳到AIC_IVR寄存器内地址处,这便是软件分发处理过程mov r14,pc bx r0；-Restore scratch/used registers and LR from User Stack ldmia sp！,{r1-r3,r12,r14}；-Disable Interrupt and switch back in IRQ mode msr CPSR_c,#I_BIT|ARM_MODE_IRQ；-Mark the End of Interrupt on the AIC ldr r14,=AT91C_BASE_AIC str r14,[r14,#AIC_EOICR]；-Restore R0 ldmia sp！,{r0}；-Restore SPSR_irq and r0 from IRQ stack ldmiasp！,{r14}msr SPSR_cxsf,r14；-Restore adjusted LR_irq from IRQ stack directly in the PC ldmia sp！,{pc}^这样，我们就知道：某一片内外设使用了AIC的哪一个输入通道是与内核无关的，它与具体芯片厂家的设计有关。
AT91ARM7S寄存器说明
lib_AT91SAM7S64: 09/01/2004lib_AT91SAM7S64: 01/23/2006//函数使用的方式:1>AT91F_PIO_Enable(AT91C_BASE_PIOA,LED1);2>AT91S_PMC *pPMC = AT91C_BASE_PMC;pPMC->PMC_SCER=AT91C_PMC_PCK0;3>*AT91C_PIOA_PER= LED1;异同:1>对于如下,编译器编译结果会不同:if(AT91F_PIO_GetInput(AT91C_BASE_PIOA) &(LED2)==LED2)与if((AT91F_PIO_GetInput(AT91C_BASE_PIOA) &(LED2))==LED2) [程序中要使用这种方式]其中LED2为(#define LED2 (1<<1))如果LED2为(#define LED2 (1<<0))则没区别2>//基本地址( AT91SAM7S64)#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address #define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address #define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address//外设ID( AT91SAM7S64)#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) #define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface#define AT91C_ID_US0 ((unsigned int) 6) // USART 0#define AT91C_ID_US1 ((unsigned int) 7) // USART 1#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) #define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)//[AT91F_PIO_CfgPeriph]AT91F_PWMC_CH3_CfgPIO:设置PIO控制器驱动PWM3 [AT91F_PIO_CfgPeriph]AT91F_PWMC_CH2_CfgPIO: 设置PIO控制器驱动PWM2 [AT91F_PIO_CfgPeriph]AT91F_PWMC_CH1_CfgPIO: 设置PIO控制器驱动PWM1 [AT91F_PIO_CfgPeriph]AT91F_PWMC_CH0_CfgPIO: 设置PIO控制器驱动PWM0 [AT91F_PMC_EnablePeriphClock]AT91F_SSC_CfgPMC:使能SSC在PMC中的时钟[AT91F_PIO_CfgPeriph]AT91F_SSC_CfgPIO: 设置PIO控制器驱动SSC[AT91F_PMC_EnablePeriphClock]AT91F_SPI_CfgPMC:使能SPI在PMC中的时钟[AT91F_PIO_CfgPeriph]AT91F_SPI_CfgPIO: 设置PIO控制器驱动SPI[AT91F_PMC_EnablePeriphClock]AT91F_PWMC_CfgPMC: 使能PWM在PMC中的时钟[AT91F_PMC_EnablePeriphClock]AT91F_UDP_CfgPMC: 使能UDP在PMC中的时钟1)PIO I/O逻辑:a)时钟使能时读引脚电平才有效b)时钟使能时输入引脚变化中断才有效c)PIO可控制外围引脚(0-31)是由PIO控制还是外设A/B(其中外设A/B是IC内部的功能模块)d) D要注意的是，所有I/O 输出的电流之和不能超过150 mA。
samba-at91sam7s64
ATMEL SAM-BA™ and SAM-PROG用户手册译者：版本：Rev2.0日期：2007-06目录一、SAM-BA™ and SAM-PROG 简介二、SAM-BA™ 工作流程三、SAM-BA™ 安装四、SAM-BA™ 烧写AT91SAM7S的具体操作五、SAM-BA™ 烧写AT91SAM7X系列的注意事项六、SAM-BA™ 烧写AT91SAM9260/9261的具体操作一、SAM-BA™ and SAM-PROG: Atmel's Flasher Tools术语：——SAM-BA GUI（SAM-BA图形用户界面）和SAM-PROG为PC端应用程序——SAM-BA BOOT为固化于微控制器端的应用程序SAM-BA™ BootATMEL的应用程序（SAM-BA GUI和SAM-PRO）均使用了嵌入在ROM 中的SAM-BA Boot固件。
SAM-BA Boot固件对芯片进行如下初始化：——启动PLL输出，为USB外设提供一个48MHz的工作频率，——连接USB外设，——连接USART外设，——等待一个来自于USB或者COM的主机连接（PC）。
SAM-BA的主要特性如下：——通过RS232或者USB接口提供ISP操作，——可以通过基于Windows的GUI或者基于DOS的命令行进行操作，——运行于Win2000和WinXP，——可以显示存储器和外设的内容，——目标器件存储器（FLASH）操作：读、写、擦除、配置、校验等——允许使用用户脚本二、SAM - Boot Assistant (SAM-BA™)——第一点：本快速入门适用于以下器件：——AT91SAM7S32和AT91SAM7S64适用于REV E及以上版本（产品ID：58814E）——AT91SAM7S321适用于REV A及以上版本（产品ID：58837A）——AT91SAM7S128和AT91SAM7S256适用于REV B及以上版本（产品ID：58818B）——第二点：——AT91SAM7S-EK（或者用户自己的基于AT91SAM7S的应用）必须遵从包含两个步骤的“系统恢复程序（System Recovery Procedure）”启动时序。
AT91SAM7S64最小系统原理图
AT91SAM7S64 VBUS 1 C19 100u 4 2 3 C16 33p 3V3 VDDIO PA16 PA15 PA14 PA13 PA24 VDDCORE PA25 PA26 PA12 PA11 PA10 PA9 PA8 PA7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 USB
1 U101 ASM1117-2.5 +5V 3 Vin Vout Vo 2 4 D2V5IN CVDD
2 IOVDD GND R102 0 R101 0 AVDD AGND AVDD AGND 3V3 D2V5IN IOVDD CVDD C119 10u C116 100n C118 10u C114 100n C117 10u CVDD AVDD
3 3V3 C115 100n VDDANA
4
5
6
VDDANA VDDIN VDDFLASH VDDIO VDDIN C5 100n C6 100n
VDDCORE C8 100n C9 100n
GND
C36 10n
R1 1.5k C37 1n
C3 10p
X1 18.432M GND VDDFLASH VDDIO USB_DP USB_DM
R11 100K
R117 1K
C20 10n
TR2 Si12301 R12 1.5K USB_DP U3 ASM1117-3.3 3V3 3 GND Vin Vout Vo 2 4 C23 10u
COM1
S1 P1 SWITCH POWER EXT_VCC
JP11
+5V
LED1 C22 220u R13 2K C21 220u
基于AT91SAM7S64的无线温湿度监控系统
学号：常州大学毕业设计（论文）（2013届）题目基于AT91SAM7S64的无线温湿度监控系统设计学生学院信息科学与工程学院专业班级通信工程091 校内指导教师专业技术职务讲师二○一三年六月学位论文独创性声明本人郑重声明：所提交的学位论文是本人在导师的指导下，独立进行研究工作所取得的成果。
除文中已经注明引用的内容外，本论文不含其他个人或集体已经发表或撰写过的研究成果，也不含为获得常州大学或其它教育机构的学位证书而使用过的材料。
对本文的研究作出重要贡献的个人和集体，均已在文中以明确方式标明。
本人承担本声明的法律责任。
签名：日期：说明：本页签名及日期均为手签。
基于AT91SAM7S64的无线温湿度监控系统设计摘要：在现代科技发展过程中,嵌入式系统在诞生之初就有着独特的地位,进入信息时代,在更多的新技术支持下,走向一个新的发展时代，即从普遍的低端应用进入到一个高、低端并行发展的时代，其主要标志是32位MCU的大范围应用。
随着众多嵌入式系统厂家的参与，基于ARM系列处理器的应用技术广泛的应用到各个领域，更加的方便了人们的生活和工作。
温湿度的自动测量和现实在生活和生产中具有非常重要的意义。
以往的人工采集数据不仅占用人力资源，而且可靠性低，容易发生差错，不能满足现代化的需求。
一般的温湿度采集系统数据显示单调，而且需要在复杂的地区布线，十分的不便。
本文采用应用广泛的ARM系列微处理器AT91SAM7S64作为平台的核心构建系统。
主机负责数据的采集和发送功能，使用51单片机负责数据的接收功能，在计算机上显示数据参数。
温湿度采集模块采用温湿度传感器芯片DHT11，无线收发模块采用无线数传模块nRF24L01。
本项目能够实时采集周围环境的温度和湿度，且不受布线的约束，是适应现代社会的高价值研究。
关键字：AT91SAM7S64；温湿度监测；无线数传模块；温湿度传感器Design of Environmental Monitoring Node on Single-chipAT91SAM7S64 based wireless temperature and humiditymonitoring system designABSTRACT：In the process of development of modern science and technology, embedded system has a unique position near the beginning of the birth , into the information age, more new technology support, toward a new era of development , from the common low-end applications into a high and low end of the era of parallel development, the main sign is the widespread application of 32-bit MCU. As many embedded systems manufacturers participate in, based on ARM series processor application technology is widely applied to various fields, more convenient people's life and work.Temperature and humidity automatic measurement and practical in life and production has very important significance. Previous artificial data not only takes up human resources, and low reliability, prone to error, cannot meet the needs of modernization. Normal temperature and humidity data acquisition system show drab, and needs in areas of complex wiring, very inconvenient.Based on the widely used ARM series microprocessor AT91SAM7S64 at the core of platform build system. Host is responsible for data collection and send function, using 51 MCU is responsible for the receiving function of data, data parameters displayed on the computer. Temperature and humidity acquisition module using DHT11 temperature and humidity sensor chip, nRF24L01 wireless transceiver module USES the wireless data transmission module.This project can collect real-time temperature and humidity of the surroundings, and is not bound by wiring, the high value of research is to adapt to the modern society.Keywords：AT91SAM7S64; Temperature and humidity monitoring; Wireless data transmission module; Temperature and humidity sensor目录摘要： (II)1 引言 (1)1.1课题背景及研究的意义 (1)1.2课题研究的目的 (1)1.3国内外现状及发展趋势 (1)1.4论文结构安排 (2)2系统硬件设计 (3)2.1硬件总体设计 (3)2.2ARM系统板介绍 (3)2.3温湿度采集模块设计 (5)2.4无线收发模块设计 (6)2.4.1数据发送模块设计 (6)2.4.2数据接收模块设计.............................................................................................. 错误！未定义书签。
AT91SAM7_DataSheet
6117AS–ATARM–20-Oct-04Features•Incorporates the ARM7TDMI ® ARM ® Thumb ® Processor–High-performance 32-bit RISC Architecture –High-density 16-bit Instruction Set –Leader in MIPS/Watt–Embedded ICE In-circuit Emulation, Debug Communication Channel Support •256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes –Single Cycle Access at Up to 30 MHz in Worst Case Conditions–Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed–Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms –10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit–Fast Flash Programming Interface for High Volume Production•64 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed •Memory Controller (MC)–Embedded Flash Controller, Abort Status and Misalignment Detection •Reset Controller (RSTC)–Based on Power-on Reset and Low-power Factory-calibrated Brownout Detector –Provides External Reset Signal Shaping and Reset Source Status •Clock Generator (CKGR)–Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL •Power Management Controller (PMC)–Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode–Three Programmable External Clock Signals •Advanced Interrupt Controller (AIC)–Individually Maskable, Eight-level Priority, Vectored Interrupt Sources–Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected•Debug Unit (DBGU)–2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention •Periodic Interval Timer (PIT)–20-bit Programmable Counter plus 12-bit Interval Counter •Windowed Watchdog (WDT)–12-bit key-protected Programmable Counter–Provides Reset or Interrupt Signals to the System–Counter May Be Stopped While the Processor is in Debug State or in Idle Mode •Real-time Timer (RTT)–32-bit Free-running Counter with Alarm –Runs Off the Internal RC Oscillator•One Parallel Input/Output Controller (PIOA)–Thirty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os –Input Change Interrupt Capability on Each I/O Line–Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output •Eleven Peripheral Data Controller (PDC) Channels•One USB 2.0 Full Speed (12 Mbits per second) Device Port–On-chip Transceiver, 328-byte Configurable Integrated FIFOs •One Synchronous Serial Controller (SSC)–Independent Clock and Frame Sync Signals for Each Receiver and Transmitter –I²S Analog Interface Support, Time Division Multiplex Support–High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer •Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)–Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation–Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support –Full Modem Line Support on USART1•One Master/Slave Serial Peripheral Interface (SPI)–8- to 16-bit Programmable Data Length, Four External Peripheral Chip SelectsAT91 ARM ® Thumb ®-based Microcontrollers AT91SAM7S256Summary PreliminaryNote: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office.2AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04•One Three-channel 16-bit Timer/Counter (TC)–Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel –Double PWM Generation, Capture/Waveform Mode, Up/Down Capability •One Four-channel 16-bit PWM Controller (PWMC)•One Two-wire Interface (TWI)–Master Mode Support Only, All Two-wire Atmel EEPROMs Supported•One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os •IEEE 1149.1 JTAG Boundary Scan on All Digital Pins•5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each •Power Supplies–Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components –3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply –1.8V VDDCORE Core Power Supply with Brownout Detector•Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions •Available in a 64-lead LQFP PackageDescriptionAtmel’s AT91SAM7S256 is a member of a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a 256 Kbyte high-speed Flash and a 64 Kbyte SRAM, a large set of peripherals, including a USB 2.0 device, and a com-plete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional per-formance and extended memory.The embedded Flash memory can be programmed in-system via the JTAG-ICE inter-face or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality.The AT91SAM7S256 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.The AT91SAM7S256 is a general-purpose microcontroller. Its integrated USB Device port makes it an ideal device for peripheral applications requiring connectivity to a PC or cellular phone. Its aggressive price point and high level of integration pushes its scope of use far into the cost-sensitive, high-volume consumer market.3AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Block DiagramFigure 1. AT91SAM7S256 Block DiagramTDI TDO TMS TCK NRSTFIQIRQ0-IRQ1PCK0-PCK2PMCPeripheral BridgePeripheral Data ControllerAICPLL RCOSCSRAM64 KbytesARM7TDMI ProcessorICEJT AG SCANJTAGSELPIOAUSART0SSCTimer CounterRXD0TXD0SCK0RTS0CTS0NPCS0NPCS1NPCS2NPCS3MISO MOSI SPCK Flash256 KbytesReset ControllerDRXD DTXDTF TK TD RD RK RF TCLK0TCLK1TCLK2TIOA0TIOB0TIOA1TIOB1TIOA2TIOB2Memory Controller Abort StatusAddress Decoder Misalignment DetectionP I OP I OAPBPOREmbedded Flash ControllerAD0AD1AD2AD3ADTRGPLLRC 11 ChannelsPDCPDC USART1RXD1TXD1SCK1RTS1CTS1DCD1DSR1DTR1RI1PDCPDC PDCPDC SPIPDCADCADVREFPDCPDCTC0TC1TC2TWD TWCKTWIOSC XIN XOUTVDDIN PWMCPWM0PWM1PWM2PWM31.8 V Voltage RegulatorUSB DeviceFIFODDM DDPT r a n s c e i v e rGNDVDDOUT BOD VDDCOREVDDCOREAD4AD5AD6AD7VDDFLASHFast Flash Programming InterfaceERASEP I OPGMD0-PGMD15PGMNCMDPGMEN0-PGMEN1PGMRDY PGMNVALID PGMNOE PGMCKPGMM0-PGMM3VDDIOTST DBGUPDCPDCP I OPIT WDT RTTSystem ControllerVDDCORE4AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Signal DescriptionTable 1. Signal Description ListSignal NameFunctionTypeActive LevelCommentsPowerVDDIN Voltage Regulator Power Supply Input Power 3.0V to 3.6V VDDOUT Voltage Regulator Output Power 1.85V nominal VDDFLASH Flash Power Supply Power 3.0V to 3.6V VDDIO I/O Lines Power Supply Power 3.0V to 3.6V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.95VGNDGroundGroundClocks, Oscillators and PLLsXIN Main Oscillator Input Input XOUT Main Oscillator Output Output PLLRC PLL FilterInput PCK0 - PCK2Programmable Clock OutputOutputICE and JTAGTCK Test Clock Input No pull-up resistor TDI Test Data In Input No pull-up resistor TDO Test Data Out Output TMS Test Mode Select Input No pull-up resistor JT AGSELJTAG SelectionInputPull-down resistor Flash MemoryERASEFlash and NVM Configuration Bits Erase CommandInputHighPull-down resistorReset/TestNRST Microcontroller Reset I/O LowPull-Up resistor TSTTest Mode SelectInputPull-down resistorDebug UnitDRXD Debug Receive Data Input DTXDDebug Transmit DataOutput AICIRQ0 - IRQ1External Interrupt Inputs Input FIQFast Interrupt InputInput5AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04PIOP A0 - P A31Parallel IO Controller AI/OPulled-up input at resetUSB Device PortDDM USB Device Port Data - Analog DDPUSB Device Port Data +Analog USARTSCK0 - SCK1Serial Clock I/O TXD0 - TXD1Transmit Data I/O RXD0 - RXD1 Receive Data Input RTS0 - RTS1Request To Send Output CTS0 - CTS1Clear To Send Input DCD1Data Carrier Detect Input DTR1Data Terminal Ready Output DSR1Data Set Ready Input RI1Ring IndicatorInputSynchronous Serial ControllerTD Transmit Data Output RD Receive Data Input TK Transmit Clock I/O RK Receive Clock I/O TF Transmit Frame Sync I/O RFReceive Frame SyncI/O Timer/CounterTCLK0 - TCLK2External Clock Inputs Input TIOA0 - TIOA2I/O Line A I/O TIOB0 - TIOB2I/O Line BI/O PWM ControllerPWM0 - PWM3PWM ChannelsOutput SPIMISO Master In Slave Out I/O MOSI Master Out Slave In I/O SPCK SPI Serial ClockI/O NPCS0SPI Peripheral Chip Select 0I/O Low NPCS1-NPCS3SPI Peripheral Chip Select 1 to 3OutputLowTable 1. Signal Description List (Continued)Signal NameFunctionTypeActive LevelComments6AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Two-Wire InterfaceTWD Two-wire Serial Data I/O TWCKTwo-wire Serial ClockI/OAnalog-to-Digital ConverterAD0-AD3Analog Inputs Analog Digital pulled-up inputs at reset AD4-AD7Analog Inputs Analog Analog InputsADTRG ADC Trigger Input ADVREFADC ReferenceAnalogFast Flash Programming InterfacePGMEN0-PGMEN1Programming Enabling Input PGMM0-PGMM3Programming Mode Input PGMD0-PGMD15Programming Data I/O PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input LowPGMCK Programming Clock Input PGMNCMDProgramming CommandInputLow Table 1. Signal Description List (Continued)Signal NameFunctionTypeActive LevelComments7AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Package and PinoutThe AT91SAM7S256 is available in a 64-lead LQFP package.64-lead LQFP Mechanical OverviewFigure 2 shows the orientation of the 64-lead LQFP package. A detailed mechanicaldescription is given in the section Mechanical Characteristics of the full datasheet.Figure 2. 64-lead LQFP Package Pinout (Top View)Pinout334948321716164Table 2. AT91SAM7S256 Pinout in 64-lead LQFP Package1ADVREF 17GND 33TDI 49TDO 2GND 18VDDIO 34P A6/PGMNOE 50JTAGSEL 3AD419P A16/PGMD435P A5/PGMRDY 51TMS 4AD520P A15/PGMD336P A4/PGMNCMD 52P A315AD621P A14/PGMD237P A27/PGMD1553TCK 6AD722P A13/PGMD138P A2854VDDCORE 7VDDIN 23P A24/PGMD1239NRST 55ERASE 8VDDOUT 24VDDCORE 40TST 56DDM 9P A17/PGMD5/AD025P A25/PGMD1341P A2957DDP 10P A18/PGMD6/AD126P A26/PGMD1442P A3058VDDIO 11P A21/PGMD927P A12/PGMD043P A359VDDFLASH12VDDCORE 28P A11/PGMM344P A260GND 13P A19/PGMD7/AD229P A10/PGMM245VDDIO 61XOUT 14P A22/PGMD1030P A9/PGMM146GND 62XIN/PGMCK 15P A23/PGMD1131P A8/PGMM047P A1/PGMEN163PLLRC 16P A20/PGMD8/AD332P A7/PGMNVALID48P A0/PGMEN064VDDPLL8AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Power ConsiderationsPower SuppliesThe AT91SAM7S256 has six types of power supply pins and integrates a voltage regu-lator, allowing the device to be supplied with only one voltage. The six power supply pin types are:•VDDIN pin. It powers the voltage regulator; voltage ranges from 3.0V to 3.6V , 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND.•VDDOUT pin. It is the output of the 1.8V voltage regulator.•VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V to 3.6V , 3.3V nominal.•VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.•VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V , 1.8V typical. It can be connected to the VDDOUT pin with decouplingcapacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly.•VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin.No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.Power ConsumptionThe AT91SAM7S256 has a static current of less than 60 µA on VDDCORE at 25°C,including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current.The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.Voltage RegulatorThe AT91SAM7S256 embeds a voltage regulator that is managed by the System Controller.In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current.The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 20 µA static current and draws 1 mA of output current.Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND.Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.9AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Typical Powering SchematicsThe AT91SAM7S256 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 3 shows the power schematics to be used for USB bus-powered systems.Figure 3. 3.3V System Single Power Supply SchematicPower Source ranges from 4.5V (USB)to 18V3.3VVDDINVoltage RegulatorVDDOUTVDDIODC/DC ConverterVDDCOREVDDFLASHVDDPLL10AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04I/O Lines ConsiderationsJTAG Port PinsTMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not.TMS, TDI and TCK do not integrate a pull-up resistor.TDO is an output, driven at up to VDDIO, and has no pull-up resistor.The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level. The pin JTAGSEL integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations.Test PinThe pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S256 when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the pin TST and the pins PA0 and PA1 should be tied high.Driving the pin TST at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.Reset PinThe pin NRST is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low exter-nally to reset the microcontroller. There is no constraint on the length of the reset pulse,and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset all the components of the system.The pin NRST integrates a permanent pull-up resistor to VDDIO .ERASE PinThe pin ERASE is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 k Ω to GND, so that it can be left unconnected for normal operations.PIO Controller A LinesAll the I/O lines PA0 to PA31 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset.I/O Line Drive LevelsThe PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently.The remaining I/O lines (PA4 to PA31) can draw only 8 mA.However, the total current drawn by all the I/O lines cannot exceed 150 mA.11AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Processor and ArchitectureARM7TDMI Processor•RISC processor based on ARMv4T Von Neumann architecture –Runs at up to 55 MHz, providing 0.9 MIPS/MHz •Two instruction sets–ARM ® high-performance 32-bit instruction set –Thumb ® high code density 16-bit instruction set •Three-stage pipeline architecture–Instruction Fetch (F)–Instruction Decode (D)–Execute (E)Debug and Test Features •Integrated embedded in-circuit emulator –Two watchpoint units–Test access port accessible through a JTAG protocol –Debug communication channel•Debug Unit –Two-pinUART –Debug communication channel interrupt handling –Chip ID Register•IEEE1149.1 JTAG Boundary-scan on all digital pinsMemory Controller•Bus Arbiter –Handles requests from the ARM7TDMI and the Peripheral Data Controller •Address decoder provides selection signals for –Three internal 1 Mbyte memory areas –One 256 Mbyte embedded peripheral area•Abort Status Registers –Source, Type and all parameters of the access leading to an abort are saved –Facilitates debug by detection of bad pointers •Misalignment Detector –Alignment checking of all data accesses –Abort generation in case of misalignment•Remap Command –Remaps the SRAM in place of the embedded non-volatile memory –Allows handling of dynamic exception vectors•Embedded Flash Controller –Embedded Flash interface, up to three programmable wait states–Prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing the required wait states–Key-protected program, erase and lock/unlock sequencer –Single command for erasing, programming and locking operations –Interrupt generation in case of forbidden operation12AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Peripheral Data Controller•Handles data transfer between peripherals and memories •Eleven channels –Two for each USART –Two for the Debug Unit–Two for the Serial Synchronous Controller –Two for the Serial Peripheral Interface –One for the Analog-to-digital Converter•Low bus arbitration overhead –One Master Clock cycle needed for a transfer from memory to peripheral –Two Master Clock cycles needed for a transfer from peripheral to memory•Next Pointer management for reducing interrupt latency requirements13AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Memory•256 Kbytes of Flash Memory –1024 pages of 256 bytes–Fast access time, 30 MHz single-cycle access in Worst Case conditions –Page programming time: 4 ms, including page auto-erase –Page programming without auto-erase: 2 ms –Full chip erase time: 10 ms–10,000 write cycles, 10-year data retention capability –16 lock bits, each protecting 16 sectors of 64 pages –Protection Mode to secure contents of the Flash •64 Kbytes of Fast SRAM–Single-cycle access at full speedMemory MappingInternal SRAMThe AT91SAM7S256 embeds a high-speed 64-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x00200000. After Remap, the SRAM also becomes available at address 0x0.Internal FlashThe AT91SAM7S256 features one bank of 256 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command.Figure 4. Internal Memory Mapping256M BytesFlash Before Remap SRAM After Remap Undefined Areas(Abort)0x000F FFFF0x001F FFFF0x002F FFFF 0x0FFF FFFF1 M Bytes1 M Bytes1 M Bytes253 M BytesInternal FlashInternal SRAM0x0000 00000x0010 00000x0020 00000x0030 000014AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Embedded FlashFlash OverviewThe Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. The 262,144bytes are organized in 32-bit words.The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions.Embedded Flash ControllerThe Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows:•programming of the access parameters of the Flash (number of wait states, timings, etc.)•starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc.•getting the end status of the last command •getting error status•programming interrupts on the end of the last commands or on errorsThe Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that opti-mizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.Lock RegionsThe Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S256contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.If a locked-regions erase or program command occurs, the command is aborted and the EFC trigs an interrupt.The 16 NVM bits are software programmable through the EFC User Interface. The com-mand "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region.Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.Security Bit FeatureThe AT91SAM7S256 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.This security bit can only be enabled, through the Command "Set Security Bit" of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deac-tivated, all accesses to the flash are permitted.It is important to note that the assertion of the ERASE pin should always be longer than 50 ms.As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.15AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04Non-volatile Brownout Detector ControlTwo general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state.These two GPNVM bits can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface.•GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default.•The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.Calibration BitsEight NVM bits are used to calibrate the brownout detector and the voltage regulator.These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.Fast Flash Programming InterfaceThe Fast Flash Programming Interface allows programming the device through either aserial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high.The Flash of the AT91SAM7S256 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words.The Flash contains a 256-byte write buffer, accessible through a 32-bit interface.16AT91SAM7S256 Summary Preliminary6117AS–ATARM–20-Oct-04System ControllerThe System Controller manages all vital blocks of the microcontroller: interrupts, clocks,power, time, debug and reset.Figure 5. System Controller Block DiagramNRSTSLCKAdvanced Interrupt ControllerReal-Time Timer Periodic Interval Timer Reset ControllerP A0-P A31periph_nreset System ControllerWatchdog Timerwdt_fault WDRPROCPIO ControllerPORBODRCOSCgpnvm[0]calenPower Management ControllerOSCPLLXIN XOUTPLLRC MAINCKPLLCKpit_irqMCK proc_nresetwdt_irq periph_irq{2]periph_nreset periph_clk[2..14]PCK MCKpmc_irqUDPCK nirqnfiq rtt_irqEmbedded Peripheralsperiph_clk[2]pck[0-2]in out enableARM7TDMISLCKSLCK irq0-irq1fiq irq0-irq1fiqperiph_irq[4..14]periph_irq[2..14]intintperiph_nresetperiph_clk[4..14]Embedded Flashflash_poejtag_nresetflash_poe gpnvm[0..1]flash_wrdis flash_wrdis proc_nresetperiph_nreset dbgu_txddbgu_rxdpit_irq rtt_irq dbgu_irq pmc_irq rstc_irqwdt_irq rstc_irqSLCKgpnvm[1]Boundary Scan TAP Controllerjtag_nresetice_nreset debugPCK debug idledebugMemory ControllerMCK proc_nresetbod_rst_enproc_nreset periph_nreset periph_nresetidleDebug Unitdbgu_irq MCKdbgu_rxd periph_nresetforce_ntrst dbgu_txdUSB DevicePortUDPCK periph_nreset periph_clk[11]periph_irq[11]usb_suspendusb_suspendVoltage RegulatorstandbyVoltage Regulator Mode Controllersecurity_bitcalice_nreset force_ntrstcal。
创新实习论文答辩
的指导下，从最基础的实验做起。综合运用电梯上 的各种电子电路，一步步完成了ARM I/O的输入/输 出实验、ARM定时器实验、ARM的串口发送接收实 验等十个实验，圆满完成课程设计任务。并且，我 们的创新思维和工程经历也进一步增强提高。
电梯控制系统
系统结构 总系统
硬件
由工程训练 中心提供
软件
在老师的指 导下自主完 成
Company name
电梯控制系统的电路实现图
芯片的外设
AT91SAM7S64为每个外设都分配了 16K的存储空间，外设有三个16位定 时器\计数器TC0、TC1、TC2，USB设 备接口，可编程的波特率发生器 USART0，USART1，PWM控制器， SSC，两线接口TWI，串行同步控制器， 8通道的模数转换器ADC，串行外设接 口SPI
电梯的机械结构
电梯模型的基本结构：由曳轮系统、井架、门机、厅门、 轿厢等五部分组成。 曳轮系统主要由电动机、曳轮、钢丝绳、导向轮和配重 等组成。 电动机：为12V直流电机，功率10瓦、转速42转/ 分，带动轿厢以2.4米/分的速度上下运行。井架 主要由 型架、导轨、底板等组成。 门机主要由电动机、主滑块组件、带轮组件等组成。 厅门主要由开关门机构、门板组件、导向轮组件等组成。 轿厢主要由厢体、按键板、顶板、底板等组成。
楼层的开始层设为shownum，shownum在头文件中声明的时 候被一个宏赋值，这样只需要修改宏，就可以实现修改楼层的第 一层所对应得电梯的层号。
在代码中通过相关宏设定达到要求。在头文件宏定义 intpinbi1pinbi2,pinbi3等变量，置零则表示屏蔽该层。以第三层代码为例。
if(pinbi3)//屏蔽选择层的判断 {if(0 == iInterSwitchStaLast[2] && iSen_Inter_Switch_G03Floor) { //形成请求 if (iInterSwitchReq[2]) {} else{ iInterSwitchReq[2] = 1;//形成请求 } } iInterSwitchStaLast[2] = !(!iSen_Inter_Switch_G03Floor); if(0 == iExternSwitchUpStaLast[2] && iSen_External_Switch_3FloorGoUp) { //形成请求 if(iExternSwitchUpReq[2]){} else{iExternSwitchUpReq[2] = 1;//形成请求} } iExternSwitchUpStaLast[2] = !(!iSen_External_Switch_3FloorGoUp); if(0 == iExternSwitchDownStaLast[2] && iSen_External_Switch_3FloorGoDown) {//形成请求 if(iExternSwitchDownReq[2]){} else{ iExternSwitchDownReq[2] = 1;//形成请求 } } iExternSwitchDownStaLast[2] = !(!iSen_External_Switch_3FloorGoDown); }
毕业设计任务书
常州大学毕业设计任务书信息科学与工程学院计算机专业093 班侯松同学：现给你下达毕业设计（论文）任务如下，要求你在预定时间内，完成此项任务。
一、毕业设计（论文）题目基于AT91SAM7S64的USB通信模块设计二、毕业设计（论文）背景USB 技术已经越来越普及和成熟，低成本、高稳定性、较高的数据传输速率和即插即用的方便性，使其备受硬件厂商的青睐。
目前许多微型计算机和工业计算机的配置中，RS232串口通信已经逐步被USB通信接口替代。
因此开发工业控制领域中的USB 通信电路是非常有价值的。
目前有很多可以用于嵌入式系统的USB Device模块，还有一些Soc 芯片集成了USB Device模块。
其中ATMEL公司的AT91SAM7SXX系列ARM芯片内部就集成有USB Device部件。
三、毕业设计（论文）目标、研究内容和技术要求基于AT91SAM7S64的ARM平台，设计其USB通信功能，具体完成如下工作：(1) 熟悉USB接口规范，设计AT91SAM7S64 下的USB接口电路；(2) 完成上位机的USB的驱动程序(3) 编写AT91SAM7S64下的USB通信程序，(4) 编写PC机方的应用测试程序，实现和AT91SAM7S64 的USB双向通信过程。
四、课题所涉及主要参考资料[1] 刁志刚. 基于ARM单片机的USB数据传输的设计与应用[J].信息技术：2010(8)：181-183[2] 蔡欣荣.基于ARM的HID类自定义功能键盘研究与实现[J]. 工业控制计算机:2011,24（57）：14-18[3] 仲伟峰，李全利，徐军. 基于ARM的嵌入式USB主机系统设计[J].哈尔滨理工大学学报：2010,15(6):42-46[4] 张永安，杨松，孙丽. 基于ARM架构的嵌入式USB驱动的设计[J]. 内蒙古农大学学报：2008,29（4）:200-202[5] 黄敏. 基于ARM下的USB设备固件程序初始化设计[J]. 六盘水师范高等专科学校学报：2007,19（6） :25-26[6] 方旭．基于STM32处理器和PC主机的USB通信协议的实现[D]．山东：山东大学，2009．[7] 王平，施文灶，黄唏，江华丽. 基于嵌人式ARM9的USB设计与实现[J]. 现代电子技术：2009 :33-36[8] 熊骁. USB2.0运用ARM芯片进行通信接口的设计[J].软件导刊：2010,9（8）：96-97五、进度安排周次工作内容预定目标1 毕业设计调研实习明确毕业课题的意义；实习总结撰写规范2-4 翻译相关英文资料；熟悉任务要求，熟悉AT91SAM7S64平台及相关编程软件。
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ARM入门笔记（1）前言如果您是一个单片机爱好者，当见到一款功能强大、性价比高的处理器时，一定会有一股很想掌握它、运用它的冲动，起码我是这样。
5年前第一次接触单片机（标准的51系列），就被它强大的功能所吸引，而痴迷于它，一直到今天。
在这期间的不同时期，各种增强型51，PIC、AVR，DSP和ARM等不同程度的吸引和诱惑着我。
有的已经玩过了，有的则没有，但很想玩的这股冲动一直存在心里，特别是对ARM。
记得2002年我就知道了ARM这个东东，眼睁睁地看着它一天天的火热，但由于对其开发工具及开发过程的不了解等原因一直只处于认识的阶段，尽管也曾玩过ZLG的2104开发板！可能是ZLG团队做的太出色的原因吧（详细的教材与源码，还有非常方便的工程模板），没过多久、没费多少劲就把里面的实验做完了，然后由于自已性格上的缺陷把它给扔在了一边，导致不到一个月就把大部分的东东还给了周老师。
直到前段时间，让我有机会真真正正的玩起了ARM！像最初玩8051那样的尽兴（出现问题时，吃不下饭、睡不着觉的那种痛苦和解决问题后的那种畅快）。
这篇文档就是记录了我在前段时间学习、调试目前最低价的ARM核处理器——AT91SAM7Sxx 时出现的问题与解决方法。
它尽量完整地记录了我从开始不懂ARM，到最终完成AT91SAM7S64各种外围实验的各个环节及整个过程，包括我在开始一个实验前的一些想法，实验目的，以及各个实验中，我以单片机的思维去思考时遇到的各种问题，和这些问题的解决方法。
现将自己的一点经验以及体会拿出来与大家共同分享，一来是希望能够为那些在ARM门口徘徊迷茫的人提供一些借鉴，使他们顺利越过这道门槛；二来是希望能够抛砖引玉，以结识更多有共同爱好的朋友。
由于我也是新手上路，文章中难免疏漏与错误，希望大家不吝指正，如果在调试AT91SAM7Sxx时有什么问题，欢迎大家共同讨论。
第一章开发工具与调试环境一．目标板所用实验板是参考ATMEL公司官方网站上发布的《AT91SAM7S-EK Evaluation Board User Guide》设计的，相当于AT91SAM7Sxx评估测试板，主要用于各种外围实验，结构框图如图1-1所示。
大家可以自己搭板子，或者直接购买现成的 AT91SAM7Sxx评估板。
图1-1. 结构框图实验板主要以AT91SAM7S64微控制器为核心，外部扩展4路模拟量输入，4个按钮和4个LED， I2C接口存储器，两个UART接口（其中一个可作程序下载的DBUG接口），1个USB 设备接口。
AT91SAM7S 系列微控制器是ATMEL公司最近推出的全球首个起步价低于3美元的ARM7内核闪存控制器，共有AT91SAM7S32/64/128/256四个型号，内部分别具有32KB/64KB/128KB/256KB的Flash ROM和8KB/16KB/16KB/32KB的SRAM，无需扩展存储器；除AT91SAM7S32外，其它都集成了USB 2.0 Device，另外还有10位的ADC、12路的DMA、I2C、SPI、PWM、实时时钟等众多外围部件，功能强大，特别适合具有8位单片机基础转学 32 ARM的用户。
二．开发工具在8位单片机的开发过程中，都会用到诸集成调试环境和仿真器。
同8位单片机一样，ARM也有自己的集成开发环境和硬件访真器。
本次实验就是使用ADS1.2集成开发环境和技创的TecorICE并口JTAG仿真器，使用时类似于51的仿真器直接挂接在keil下使用那样。
我个人认为无论是ARM、DSP还是51或PIC等，其开发工具和开发过程都是类似的。
简单的讲都是先在集成开发环境中编辑用户程序，然后经过编译、连接产生目标文件，再通过硬件仿真器进行仿真调试。
而对于普通51仿真器与ARM仿真器，使用起来并没明显的不同，主要的差别大概在于仿真接口（或者说是仿真头）。
普通51仿真器是使用与目标单片机管脚兼容的仿真头替代目标单片机，用户程序是在仿真器内部的仿真芯片上运行。
ARM核处理器内置ICE （仿真调试模块），该模块通过标准的JTAG接口引脚与ARM仿真器相连，此时ARM仿真器作为上位调试软件与ARM核芯片之间的协议转换器。
用户的目标调试文件被下载到目标板上的存储器（可以是外部的或ARM处理器内部的存储器）中，通过控制目标芯片的仿真模块实现仿真调试。
ARM入门笔记（2）第二章我的第一个实验――将程序执行到C文件的main函数二．实验目的运用ADS编写一个小程序，使程序能够从起始的汇编代码运行到C程序的main()函数（这也可称作非常简单的起动代码），并通过仿真器连接目标板，最终能够在AT91SAM7S64里正确运行。
三．实验程序和参数设置1>连接器的选项设置选项设置如图2-1所示。
因为在AT91SAM7S64中FLASH存储器的地址是以0x0开始，而SRAM的地址是以0x00200000开始，所以我将下图中的RO Base和RW Base分别设置成了0x0和0x00200000。
其它设置请参考有关书籍。
图2-1. 选项设置图2>启动代码在 ARM应用系统中，芯片复位后，在进入C语言的main()函数前，都要执行一段启动代码。
该代码一般都是用汇编语言编写，用来完成系统运行环境和应用程序的初始化，详情请参考有关书籍。
由于本实验的目的很简单，就是想让程序复位后，进入main()函数，所以有些初始化代码尽量精简，留下了下述代码。
另外，__main是C语言的内部库函数，可以在进入用户main()之前完成内部RAM的初始化工作，类似KeilC51中的startup.a51。
当执行完__main这段代码后，再跳转到main()函数。
AREA init,CODE,READONLYCODE32Mode_USR EQU 0x10 ;CPSR中各种处理器模式对应的控制位I_Bit EQU 0x80 ;CPSR中的中断禁止位F_Bit EQU 0x40USR_Stack EQU 0x00203000 ;定义RAM的最高地址,无重映射ENTRYB InitReset ; 0x00 Reset handlerundefvec B undefvec ; 0x04 Undefined Instructionswivec B swivec ; 0x08 Software Interruptpabtvec B pabtvec ; 0x0C Prefetch Abortdabtvec B dabtvec ; 0x10 Data Abortrsvdvec B rsvdvec ; 0x14 reservedirqvec B irqvec ; 0x18 IRQfiqvec B fiqvec ; 0x1c FIQInitResetMSR CPSR_c,#Mode_USR | I_Bit | F_Bit ;改成用户模式且禁止IRQ和FIQ中断LDR SP,=USR_StackIMPORT __mainb __main ;跳转到__main执行，它位于C运行时库中END3>C语言主函数在C语言主函数中做了一个死循环，如下述所示。
int main(void){while (1);}四．出现的问题与解决方法当完成上述操作后，先用软件仿真，很快达到了目的，但将程序通过仿真器在目标板运行时出现了下述问题。
1> 当执行单步运行时，PC一直停留在0x0处，而且Debug Log窗口中显示“RDI Warning 00148: Can't set point”。
原因是仿真器在ROM中设置的断点数是有限的，且单步运行时内部还要占用断点。
可以使用“Option->Config Processor”打开“Processor Properties-ARM7TDMI”窗口，且按照下图设置以关断相的断点。
图2－22> 装载的代码与实践程序不一样原因是由于程序没有装载到AT91SAM7S64的FLASH ROM里，在调试器中显示的是FLASH ROM中原先就有的程序。
因为在连接器的选项设置中，将RO Base和Image entry point指向了0地址，而在AT91SAM7S64的这段空间为FLASH ROM区，而仿真器不能直接将代码下载到FLASH ROM里。
用仿真器只能将代码下载到AT91SAM7S64的内部SRAM 里进行调试，必须将ARM Linker->Output->Simple image->RO Base和Image entry point的0，改成SRAM的地址0x002000000。
3>在软件仿真的情况下，执行“B __main”指令，能使程序跳到C文件的main函数，但用硬件仿真时，还没执行到main函数时就进入了异常中断。
原因是执行“B __main”指令后，程序先跳到__main库函数的入口，再进行一些初始化操作，最后再跳入用户的main函数。
但在初始化过程中，由于堆栈或其它原因造成程序出错。
有两种方法可以解决这个问题。
第一：将“B __main”指令直接改成“B main”，使程序不进行初始化而直接跳入用户的main()函数。
第二：合理初始化堆栈。
由于考虑到刚接触ARM和将问题简单化，我选择了第一种方法。
五．总结1> 在用仿真器时，必须将程序下载到AT91SAM7S64的内部SRAM中，而不是Flash ROM。
2> 从汇编代码进入C文件函数时，可以直接使用C语言中的标号（可参考书中混合编程部分），如执行“B main”则直接跳到C语言的main()函数入口。
3> 在起动代码中，可以调用__main()库函数进行存储器的初始化，也可以自己编写更有效的代码进行初始化，在初始化后就可以使用“B __main”指令直接跳转到C的main()函数。
ARM入门笔记（3）第三章点亮我的LED――I/O输出实验一．背景当完成上述实验后，我就可以像使用51单片机那样，在C文件的main()函数中通过设置相应的寄存器来达到对相应外设（如I/O的输入、输出等）的控制目的。
二．实验目的通过控制PIO的相关寄存器，使特定的I/O口输出高电平和低电平，来点亮LED。
三．实验程序和参数设置1> 连接器选项设置RO Base = 0x00200000;RW Base = 0x00202000;Image entry point=0x00200000;2> 启动代码启动代码与第一个实验中修改后的相同，即将“__main()”改成main()。
3> C语言的代码＃i nclude "AT91SAM7S64.h" //特殊功能寄存器头文件。