h09_hw3

HOMEWORK #3(Due: Tuesday, April 19, 2005, 1:00 pm PT)1. kT/C Noise. A basic track and hold circuit is shown below. Assume that the inputsignal V i has a full-scale range from 0 to 1V. If several track-and-hold circuits of this type are used in an 10-bit ADC and the total input-referred thermal noise power is found to be 10·kT/C H, how large a capacitor C H is needed to make the total input-referred thermal noise rms voltage equal to 0.25LSB when T = 25°C? Compared to the case where only quantization noise is present, how much is the dynamic range reduced by the input-referred kT/C noise?Figure 12. SC Integrator. Consider the sampled data integrator shown in Figure 2. This circuithas a sampling capacitor C S, together with an integration capacitor C I. You are to assume that Φ1 and Φ2 are two-phase, non-overlapping clocks. When a clock signal is high, all switches controlled by it conduct, and when the clock is low the switches are open circuits. Assume that the OpAmp is ideal (infinite gain and bandwidth).a) Derive an expression for the discrete-time output voltage of the integrator justafter Φ2 transitions low in terms of the input sample for that clock cycle and theoutput sample of the preceding cycle. Please refer to Figure 3 for the definition ofa clock cycle. Note that the output value for a given cycle is considered the valueat the output when Φ2 is high.b) Assuming that all noise sources are uncorrelated and the OpAmp is noiseless,what is the power of the output-referred kT/C noise in this circuit? What is thepower of the input-referred kT/C noise in this circuit? Hint: You can usesuperposition of the two different states.c) Now, assume that the OpAmp has a finite bandwidth such that the integrator has aclosed-loop bandwidth that is 10 times smaller than the bandwidth associated with the two switches and C S during Φ2. What is the power of the output-referred kT/C noise in this circuit? What is the power of the input-referred kT/C noise in thiscircuit? Assume the OpAmp still has an infinite gain.Figure 2Figure 33. Flip-around T/H. Consider the track-and-hold amplifier shown in Figure4. Assumethat all the switches are ideal and that at t = 0 a sample from the ideal voltage source V s is taken. The switches S1 and S2 are closed for t < 0 while S3 is open. At t = 0, S1 and S2 are opened followed by S3 closing which holds the sampled value.a) Assume that the OpAmp is ideal with infinite gain and no input offset voltage.Find Vo after S3 is closed.b) Assume that the op amp has a finite gain of A = 60dB and is otherwise ideal. FindV o after S3 is closed. Also, determine the gain error of this track-and-holdamplifier. The gain error is defined as the fractional deviation in the outputvoltage, V o, from its ideal value, V o,ideal.c) Assume that the OpAmp has a finite gain of A = 60dB with an input referredoffset voltage of Voff = 100mV. Find Vo after S3 is closed. Please indicate thegain error and the offset. The offset is defined as the value that would bemeasured at Vo if Vs = 0. What happens to the offset as A →∞?V oFigure 44. Project Warm-up. Consider the switched capacitor stage shown in Figure5. Amodel of the fully differential OTA used in this implementation is given in Figure 6.For all HSpice simulations, utilize the subcircuit netlists available inusr/class/ee315/hw3 and in the private handout section (clocks.txt, ota1.txt,switches.txt, utils.txt). Use the ideal switch models “nswi315” for all simulations, except for (h). Given parameters: G m=1mS, A vo=60dB, n f=2, g m/I D=15S/A,f T=13GHz, C SP,M= C FP,M=100fF, C LP,M=300fF, V ic=0.6V, V oc=0.9V, V DD=1.8Va) Calculate the output-referred noise contribution caused by sampling during Φ1.b) Calculate the output noise component added during the redistribution phase (Φ2).For simplicity, neglect the noise from the switches, i.e. consider only noisecontributed by the OTA.c) Calculate the gain error of this stage in % (≡static settling error).d) Assuming V id=10mV, calculate the dynamic settling error εd (in%) at t=t0. εd isdefined as the relative error with respect to the final settling value for t→∞.Ignore the impact of feedforward zeros.e) Repeat (c) for V id=600mV. Note that the amplifier will slew under this condition.f) Verify (b) with HSpice using a .noise simulation. Generate a plot that shows thenoise power spectral density and the square root of the running integral of thenoise power spectral density.g) Verify (c)-(e) with HSpice using .tran simulations. Zoom into the relevant plotregions of V od and annotate the calculated values in your simulation diagrams.Show the OTA current I o in all your plots.h) Replace the ideal switches with 30µm/0.18µm NMOS devices (except for theswitch at the OTA output) and run a transient simulation with V in=10mV.Generate a plot that shows the total differential voltage across the samplingcapacitors V cs=[V tm-V bm]-[V tp-V bp]) and V od. What is the error of V cs after thefalling edge of Φ1 in mV? Why is the final output voltage at t=t o closer to theideal value of 10mV? Explain briefly. In a separate diagram, plot the voltageacross a single capacitor, e.g. V tm-V bm. Explain the various transients on thiswaveform.Note: Use “.option accurate method=gear” to improve the accuracy of your transient simulations. Also, use a sufficiently small transient print step to obtain smooth plots.LMFMV od V ocV idV icV ic V ic V icV icΦ1Φ2Φ1e t o0.5nsFigure 5V bp V bmV opV omTmbdf 2G 21C π=m f 2n G kT 38n f i ⋅=∆()⎪⎪⎩⎪⎪⎨⎧>⋅=else2V G I 2V G forV sign I I bd m max bdmbd maxo mvoo G A R =Dm m maxI /g G I =Single stage OTA model (HSpice: OTA1.txt)+V bd -Figure 6。