SN54LV166A中文资料

SN54LV166A, SN74LV166A8-BIT PARALLEL-LOAD SHIFT REGISTERS

SCLS456A – FEBRUARY 2001 – REVISED JULY 2003

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D2-V to 5.5-V VCC OperationDMax tpd of 10.5 ns at 5 VDTypical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°CDTypical VOHV (Output VOH Undershoot)>2.3 V at VCC = 3.3 V, TA = 25°CDIoff Supports Partial-Power-Down-ModeOperationDSynchronous LoadDDirect Overriding Clear

DParallel-to-Serial Conversion

DLatch-Up Performance Exceeds 100 mA Per

JESD 78, Class IIDESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)– 200-V Machine Model (A115-A)– 1000-V Charged-Device Model (C101)

SN54LV166A...J OR W PACKAGESN74LV166A...D, DB, DGV, NS, OR PW PACKAGE(TOP VIEW)

SN54LV166A...FK PACKAGE(TOP VIEW)

NC – No internal connection12345678

161514131211109

SERABCDCLK INHCLKGNDVCCSH/LDHQH

G

FECLR

32120199101112134

5678

1817161514

HQH

NC

GF

BCNCDCLK INH

ASERNCCLREVSH/LD

CLKGND

NC

CC

description/ordering informationThe ’LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V VCC operation.ORDERING INFORMATIONTAPACKAGE†ORDERABLEPART NUMBERTOP-SIDEMARKING

SOICDTube of 40SN74LV166ADSOIC – DReel of 2500SN74LV166ADRLV166ASOP – NSReel of 2000SN74LV166ANSR74LV166A40Cto85SSOP – DBReel of 2000SN74LV166ADBRLV166A–40°C to 85°CTube of 90SN74LV166APW

TSSOP – PWReel of 2000SN74LV166APWRLV166AReel of 250SN74LV166APWTTVSOP – DGVReel of 2000SN74LV166ADGVRLV166ACDIP – JTube of 25SNJ54LV166AJSNJ54LV166AJ–55°C to 125°CCFP – WTube of 150SNJ54LV166AWSNJ54LV166AW

LCCC – FKTube of 55SNJ54LV166AFKSNJ54LV166AFK†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Copyright  2003, Texas Instruments IncorporatedPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTIONDATA information current as of publication date. Products conform tospecifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of allparameters.SN54LV166A, SN74LV166A8-BIT PARALLEL-LOAD SHIFT REGISTERS

SCLS456A – FEBRUARY 2001 – REVISED JULY 2003

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description/ordering information (continued)The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and anoverriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input.When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with eachclock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurson the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on thelow-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as aclock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either lowenables the other clock input. This allows the system clock to be free running, and the register can be stoppedon command with the other clock input. CLK INH should be changed to the high level only when CLK is high.CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the

outputs, preventing damaging current backflow through the devices when they are powered down.

FUNCTION TABLEOUTPUTSINPUTSINTERNAL

CLRSH/LDCLK INHCLKSERPARALLELA...HQAQB

QH

LXXXXXLLLHXLLXXQA0QB0QH0

HLL↑Xa...habhHHL↑HXHQAnQGn

HHL↑LXLQAnQGn

HXH↑XXQA0QB0QH0