PCA9633DP1,118;PCA9633DP2,118;PCA9633BS,118;PCA9633PW,112;PCA9633D16,112;中文规格书,Datasheet资料
MAX9632-MAX9633低噪音

MAX9632/MAX9633 低噪音
Maxim 的新轨至轨运算放大器提供高电压性能在低频率,精确的规格,高收益,能够在工业应用精密的信号调理。
位于美国加州Sunnyvale,2010 年11 月9 日,MAXIM 集成产品公司(NASDAQ:MXIM)推出MAX9632/MAX9633 的36V,低噪音,低失真精密运算放大器。
在Maxim 的高电压,精密运算放大器新系列的第一个器件,MAX9632/MAX9633 的设计采用了一个专有的高速互补BiCMOS 工艺
(CB5HV)。
这个高电压模拟工艺优化交流优秀的动态性能,超低噪声,工作电压范围宽,低漂移信号调理。
MAX9632/MAX9633 目标的工业数据采集系统的精度要求在低频信号调理。
在MAX9632 是单运放具有超低输入电压噪声密度0.94nV /,低偏移的125μV(最大值),和偏移量温度系数的0.5μV/° C(最大)。
在MAX9633 是一款双用的3nV 输入电压噪声密度运算放大器/,对200μ偏移(最大)一,和偏移量温度系数的0.9μV/° C(最大)。
这两款器件提供高规格的信号保真度和总谐波失真调节优于-一三六分贝,能够在专业音响设备和高端测试和仪器仪表应用。
增益带宽积(GBWP)是典型的MAX9632 和MAX9633 27MHz 时为55MHz 的。
这可用带宽,慷慨的4.5V 至36V 工作电压范围,典型的三点九毫安(MAX9632)电流消耗相结合,。
PCA9633中文资料

Software programmable LED Group and three Sub Call I2C addresses allow all or defined groups of PCA9633 devices to respond to a common I2C address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C-bus commands.
I Software Reset feature (SWRST Call) allows the device to be reset through the I2C-bus
元器件交易网
PCA9633
4-bit Fm+ I2C-bus LED driver
Rev. 03 — 20 December 2006
Product data sheet
ห้องสมุดไป่ตู้
1. General description
The PCA9633 is an I2C-bus controlled 4-bit LED driver optimized for Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. A fifth 8-bit resolution (256 steps) Group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs with the same value.
RGB LED彩灯驱动控制技术

RGB LED彩灯驱动控制技术北京乐华贝特微电子近期推出RGB LED彩灯驱动控制方案,LED是一种性能优良的显示器件,具有寿命长、节电、高亮度、多种发光颜色、响应速度快和驱动电压低等优点,在节省能源的同时还可以通过PWM 器件调节LED发光强度,依据R、G、B三原色混光原理调出多种颜色,再通过MCU智能控制实现多种显示效果。
现正大量应用于城市亮化、建筑景观照明、舞台灯光设计等领域。
本设计方案采用恩智浦半导体(NXP)的电源管理芯片、微控制器、I2C器件、LED驱动器件,为LED 灯光系统设计提供全套的方案设计。
主要芯片:PCA9633/34/35:NXP I2总线RGB/RGBA LED闪烁/混光芯片;TEA152x:NXP电源芯片;LPC92x:NXP 900系列MCU;P82B96/PCA9600:NXP I2C总线驱动芯片。
主要应用:1. 点光源:应用LED彩色屏显示原理,将其像素放大,降低整体造价成本,每个模块为一个彩色像素点。
应用环境:酒吧、KTV、舞台、商场、展厅,作为音乐旋律显示,背景墙装饰、幕墙广告等。
2. LED彩虹管:每条灯管由多个彩色像素点(RGB)组成,每个单色像素点可产生256个灰度级的变化。
应用环境:立交桥、河道护栏、建筑外墙等不同场所的装饰照明。
系统硬件设计:LED彩灯控制系统主要包含驱动模块、控制模块、LED电源三部分。
1. 驱动模块设计如何实现让LED模块呈现不同的颜色,主要依靠人的视觉间歇惰性原理,利用对R、G、B三原色的LED的占空比实现颜色的混合。
本设计方案的LED颜色显示主要依靠NXP公司的I2C接口LED闪烁/混光驱动芯片PCA9633(PCA9633-4位PWM输出,PCA9634-8位PWM输出,PCA9635-16位PWM输出)输出256灰度级的颜色来实现彩色显示。
控制器只需要传送该模块的RGB颜色的灰度值即可实现颜色显示。
PCA9633是I2C总线控制的可编程PWM输出的四位LED驱动器件,主要应用于LEDRGB/RGBA(Red/Green/Blue/Amber)混光,主要性能指标如下:1. 4路LED驱动,每路驱动可以通过软件编程为四种状态,分别是:开、关、可编程PWM闪烁控制输出、可编程每路灰度级别,同时支持四路整体亮度调节的PWM混光输出。
4位RGBLED彩灯控制器PCA9633的应用

( 1 ) 4路 L E D 驱 动 , 每 路 驱 动 可 以 通 过 软 件 编 程 为
灯发光 , 最 后 给 出应 用 实 例 。 关 键 词 :P C A 9 6 3 3; R GB L E D; I 2 C 时 序
中 图 分 类 号 :T P 3 0 2 文 献 标 识 码 :A 文 章 编 号 :1 6 7 4 — 7 7 2 0( 2 0 1 5) 0 7 — 0 0 3 0 — 0 4
Ap pl i c a t i o n o f 4 b i t RGB L ED d r i v e r PCA9 6 3 3
Fe n g Yue qi n
( N a n j i n g I n s t i t u t e o f T e c h n o l o g y , N a n j i n g 2 1 1 1 6 7, C h i n WM 器 件 调 节 L E D发 光强 度 , 依
据 RG B三 原 色 混 光 原 理 调 出 多 种 颜 色 , 再 通 过 MC U 智 能控制 实现 多种 显示效 果 。 本 文 主 要 是 介 绍 飞 利 浦 公 司
设 置为没有 P WM ( P u l s e Wi d t h Mo d u l a t i o n)控 制 的 关 或 开 , 或 者 由 其 独 立 的 P WM 控 制 器 的 值 和 组
P WM 控 制 器 的 值 确 定 。L E D 驱 动 输 出的信 号 频 率 为 9 7 k H z , 占空 比 在 0 %~ 9 9 . 6 %可调 。本 文 介 绍 P C A9 6 3 3的 I 2 C协 议 , 重 点 介 绍 它与 C P U 的 硬 件 电 路 图 以 及 通 过 C语 言 编 程 实 现 I 2 C时序 , 驱动 L E D
ic电子x

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IR1000014+ IRG4PC40SPBF IR1000014+ IRG4PC40UDPBF IR1000014+ PCA9515DP NXP500015+ PCA9507DP NXP500015+ PCA9507D NXP500015+ PCA9512ADP NXP500015+ P82B96DP NXP500015+ PCA9509DP NXP500015+ P82B96TD/S900NXP500015+ PCA9600DP NXP500015+ PCA9511ADP NXP500015+ PCA9512AD NXP500015+ PCA9513ADP NXP500015+ PCA9510ADP NXP500015+ P82B96TD NXP500015+ P82B715TD NXP500015+ PTN36241BBS NXP500015+ PCA9515AD NXP500015+ PCA9508DP NXP500015+ PCA9508D NXP500015+ PCA9517ATP NXP500015+ PCA9515D NXP500015+ PCA9509D NXP500015+ PCA9601D NXP500015+ PCA9527DP NXP500015+ PCA9511AD NXP500015+ PCA9512BDP NXP500015+ PCA9514ADP NXP500015+ PCA9614DP NXP500015+ PCA9616PW NXP500015+ PCA9601DP NXP500015+ PCA9646PW NXP500015+ PCA9509AGM NXP500015+ PCA9512BD NXP500015+ PCA9615DPJ NXP500015+ PCA9509PDP NXP500015+PCA9509ADP NXP500015+ PCA9516APW NXP500015+ PCA9514AD NXP500015+ PCA9513AD NXP500015+ PCA9517AD NXP500015+ PTN36221AHXZ NXP500015+ PCA9517D NXP500015+ PCA9600D NXP500015+ PTN36242LBS NXP500015+ PCA9525DP NXP500015+ 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FUJI1000014+ MTA-001SHINDENGEN1000014+ MB90098APF-G-164-EFE1FUJI1000014+MB8464C-10L FUJI1000014+ MB7138H-SK FUJI1000014+ M54530P MIT1000014+ MB86437PFV-G-BND-EF FUJI1000014+ MB831000-15P FUJI1000014+ MT48LC4M16A2P-75G MT1000014+ M5K4164AL-15MIT1000014+ M57917L-01MIT1000014+ MTD1120F SHINDENGEN1000014+ MB831000-20P FUJI1000014+ MB90004PMT2-G-709-BND FUJI1000014+ MB88346LPV-G-BNP-EF FUJI1000014+ MB653459PF-G-BNO FUJI1000014+ MTD20N03HDLTT4G1000014+ MB14110FUJI1000014+ MB3761PF-G-BND-HN FUJI1000014+ M51366SP-G MIT1000014+ MSM6654A-521GS-KR1-7OKI1000014+ MT46V32M16P-6T∶F MICRON1000014+ MB3771PF-G-BND MBM1000014+ MBR4045WT ON1000014+ MT48LC4M32B2TG-7MT1000014+ M5M51008AVP-10VLL MIT1000014+ MBCG61394-110PFV-G FUJI1000014+ MBCG24692-4109PF-G FUJI1000014+ M5M51008AVP-10VHT MIT1000014+ M5M5256DP-70LL MIT1000014+ MB81C1000-10PSZ FUJI1000014+ M5216MIT1000014+ MBCG24942-6618PFV-G FUJI1000014+ MBM29QM12DH60PBT-E FUJI1000014+ M5201FP MIT1000014+ MB426FUJI1000014+ MIP2E3D M1000014+ M53401C-93OKI1000014+ M54640P MIT1000014+ MB74ALS73MOT1000014+ MB.PI-1250-OR5P NEC1000014+ M5105A4E8ACER1000014+ MB434112PF-BND-EF(811600-2FUJI1000014+ MSP4410K-QA-B3-500G MICRONAS1000014+ M50601P MIT1000014+ MSL9370RS OKI1000014+ MB3756M-G FUJI1000014+ MB89193AF-G-472FUJI1000014+ MB1515PFV-G-BND FUJI1000014+ MIC5209-3.6BM MICREL1000014+ MT41J128M16HA-15E:D MT1000014+ M51523AL MIT1000014+ MBM29F400TC-90PFTN FUJI1000014+MSM532001B-44GS-KR1OKI1000014+ MB64H143M-G FUJI1000014+ MSM6100QUALCOMM1000014+ MB81V18165B-60PFTN FUJI1000014+ MST9015BX MSTAR1000014+ M51366SP MIT1000014+ MB3206FUJI1000014+ MBL68B09E FUJI1000014+ MB670535PF-G-BND FUJI1000014+ MB89183PFM-G-209-BND FUJI1000014+ MSM7500-0-543CSP-TR-02-90NQUALCOMM1000014+ M5M28F101AFP-10MIT1000014+ MB4132FUJI1000014+ MIC4681BM MICREL1000014+ MBM29DL322TE-90PFTN FUJI1000014+ M5247FP-600C MIT1000014+ MB90F574BPFV-G-433-BND FUJI1000014+ M50467-182FP MIT1000014+ MT48LC64M4A2TG-7E:D MICRON1000014+ MSP3417G-QG-BB-V3-G MICRONAS1000014+ MT4LC4M16R6TG-5F MT1000014+ MB674611UP-G-SK FUJI1000014+ MB88347PFV-G-BND-ER FUJI1000014+ M50FW040N5ST1000014+ MB88544PF-G-203M-BND FUJI1000014+ MSM56V16160DP-10TKR1OKI1000014+ M5M80C85AFP-2-T2MIT1000014+ MT28F800B3WG-9BF MT1000014+ MTSF3N03HDR2ON1000014+ MB80822PFM-G-121E1FUJI1000014+ MBM29LV400TC-70PFTN FUJI1000014+ M5536OKI1000014+ MT9M002C12STCV MT1000014+ MB3773FUJI1000014+ MB8AA1260BGL-GE1FUJI1000014+ MB8874N FUJI1000014+ MT8865XE MT1000014+ M52742SP MIT1000014+ M50726-345SP MIT1000014+ MIC4423CWM MIC1000014+ MSP3411G-QA-C12MICRONAS1000014+ MB90522BPFV-GS-238-BND FUJI1000014+ M51V18165DSL-6OKI1000014+ MB85431BC-01FUJI1000014+ MB40C318PFV-G-BND FUJI1000014+ MM3286DFBE MITSUMI1000014+ MB834200B-15P-G-11C FUJI1000014+ MB90098APF-G-131-BND-ER FUJI1000014+ MB625518U FUJI1000014+ MIC2026-2YM MIC1000014+。
PCA9538BS-T中文资料

Philips Semiconductors
Philips Semiconductors
Product data sheet
8-bit I2C-bus and SMBus low power I/O port with interrupt and reset
PCA9538
DESCRIPTION
The PCA9538 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I2C/SMBus applications and was developed to enhance the Philips family of I2C I/O expanders. I/O expanders provides a simple solution when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc. The PCA9538 consists of an 8-bit Configuration register (Input or Output selection); 8-bit Input register, 8-bit Output register and an 8-bit Polarity inversion register (Active HIGH or Active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the input port register can be inverted with the Polarity Inversion Register. All registers can be read by the system master. The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and different address range. The PCA9538 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without depowering the device. Two hardware pins (A0 and A1) vary the fixed I2C address and allow up to four devices to share the same I2C/SMBus.
PCA9543资料

元器件交易网SO14:plastic small outline package; 14 leads; body width 3.9 mm SOT108-1TSSOP14:plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1DefinitionsShort-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.DisclaimersLife support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.Contact informationFor additional information please visit.Fax: +31 40 27 24825For sales offices addresses send e-mail to:© Koninklijke Philips Electronics N.V. 2004All rights reserved. Published in the U.S.A.Date of release: 10-04Document number:9397 750 14112。
PCA9533D

1.General descriptionThe PCA9533is a 4-bit I 2C-bus and SMBus I/O expander optimized for dimming LEDs in 256 discrete steps for Red/Green/Blue (RGB) color mixing and back light applications.The PCA9533 contains an internal oscillator with two user programmable blink rates and duty cycles coupled to the output PWM. The LED brightness is controlled by setting the blink rate high enough (>100Hz)that the blinking cannot be seen and then using the duty cycle to vary the amount of time the LED is on and thus the average current through the LED.The initial setup sequence programs the two blink rates/duty cycles for each individual PWM.From then on,only one command from the bus master is required to turn individual LEDs ON, OFF , BLINK RATE 1 or BLINK RATE 2. Based on the programmed frequency and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the LEDs to appear at a different brightness or blink at periods up to 1.69second. The open-drain outputs directly drive the LEDs with maximum output sink current of 25mA per bit and 100mA per package.To blink LEDs at periods greater than 1.69second the bus master (MCU, MPU, DSP ,chip set, etc.) must send repeated commands to turn the LED on and off as is currently done when using normal I/O expanders like the NXP Semiconductors PCF8574 or PCA9554. Any bits not used for controlling the LEDs can be used for General Purpose parallel Input/Output (GPIO)expansion,which provides a simple solution when additional I/O is needed for ACPI power switches, sensors, push-buttons, alarm monitoring, fans,etc.The Power-On Reset (POR) initializes the registers to their default state, causing the bits to be set HIGH (LED off).Due to pin limitations, the PCA9533 is not featured with hardware address pins. The PCA9533/01 and the PCA9533/02 have different fixed I 2C-bus addresses allowing operation of both on the same bus.2.FeaturesI 4 LED drivers (on, off, flashing at a programmable rate)I Two selectable, fully programmable blink rates (frequency and duty cycle) between 0.591Hz and 152Hz (1.69second and 6.58milliseconds)I 256 brightness stepsI Input/outputs not used as LED drivers can be used as regular GPIOs I Internal oscillator requires no external components I I 2C-bus interface logic compatible with SMBusPCA95334-bit I 2C-bus LED dimmerRev. 03 — 27 April 2009Product data sheetI Internal power-on resetI Noise filter on SCL/SDA inputsI 4 open-drain outputs directly drive LEDs to 25mA I Edge rate control on outputs I No glitch on power-up I Supports hot insertion I Low standby currentI Operating power supply voltage range of 2.3V to 5.5V I 0Hz to 400kHz clock frequencyIESD protection exceeds 2000V HBM per JESD22-A114, 150V MM per JESD22-A115 and 1000V CDM per JESD22-C101I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA I Packages offered: SO8, TSSOP8 (MSOP8)3.Ordering information3.1Ordering optionsTable 1.Ordering informationType numberPackage NameDescriptionVersion PCA9533D/01SO8plastic small outline package; 8leads;body width 3.9mmSOT96-1PCA9533D/02PCA9533DP/01TSSOP8plastic thin shrink small outline package; 8leads;body width 3mmSOT505-1PCA9533DP/02Table 2.Ordering optionsType number Topside mark Temperature range PCA9533D/01P9533/1T amb =−40°C to +85°C PCA9533D/02P9533/2T amb =−40°C to +85°C PCA9533DP/01P33/1T amb =−40°C to +85°C PCA9533DP/02P33/2T amb =−40°C to +85°C4.Block diagram5.Pinning information5.1Pinning5.2Pin descriptionRemark:Only one I/O shown for clarity.Fig 1.Block diagram of PCA9533002aae626I 2C-BUS CONTROLINPUT FILTERSPCA9533POWER-ON RESETSCL SDAV DDV SSLEDnOSCILLATORPRESCALER 1REGISTERPRESCALER 0REGISTER PWM1REGISTERPWM0REGISTER INPUT REGISTERLED SELECT (LSn)REGISTERBLINK0BLINK11Fig 2.Pin configuration for SO8Fig 3.Pin configuration for TSSOP8PCA9533D/01PCA9533D/02LED0V DD LED1SDA LED2SCL V SSLED3002aae62412346587LED0V DD LED1SDA LED2SCL V SSLED3002aae62512346587PCA9533DP/01PCA9533DP/02Table 3.Pin descriptionSymbol Pin Description LED01LED driver 0LED12LED driver 1LED23LED driver 2V SS 4supply ground LED35LED driver 36.Functional descriptionRefer to Figure 1 “Block diagram of PCA9533”.6.1Device addressFollowing a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9533/01 is shown in Figure 4 and the address of PCA9533/02 is shown in Figure 5.The last bit of the address byte defines the operation to be performed.When set to logic 1a read is selected, while a logic 0 selects a write operation.6.2Control registerFollowing the successful acknowledgement of the slave address,the bus master will send a byte to the PCA9533, which will be stored in the Control register.The lowest 3bits are used as a pointer to determine which register will be accessed.If the Auto-Increment (AI) flag is set, the three low order bits of the Control register are automatically incremented after a read or write. This allows the user to program theregisters sequentially.The contents of these bits will rollover to ‘000’after the last register is accessed.When Auto-Increment flag is set (AI =1) and a read sequence is initiated, the sequence must start by reading a register different from the INPUT register (B2B1B0≠000).Only the 3 least significant bits are affected by the AI flag. Unused bits must be programmed with zeroes.SCL 6serial clock line SDA 7serial data line V DD8supply voltageTable 3.Pin description …continuedSymbol Pin Description Fig 4.PCA9533/01 slave address Fig 5.PCA9533/02 slave address002aae627111R/Wslave address002aae6281111R/Wslave address Reset state: 00hFig 6.Control registerB0002aad744000AI 0B2B1register addressAuto-Incrementflag6.2.1Control register definition6.3Register descriptions6.3.1INPUT - Input registerThe INPUT register reflects the state of the device pins. Writes to this register will be acknowledged but will have no effect.Remark:The default value ‘X’is determined by the externally applied logic level (normally logic 1) when used for directly driving LED with pull-up to V DD .6.3.2PCS0 - Frequency Prescaler 0PSC0 is used to program the period of the PWM output.The period of BLINK0=(PSC0+1)/152.6.3.3PWM0 - Pulse Width Modulation 0The PWM0register determines the duty cycle of BLINK0.The outputs are LOW (LED on)when the count is less than the value in PWM0 and HIGH (LED off) when it is greater. If PWM0 is programmed with 00h, then the PWM0 output is always HIGH (LED off).The duty cycle of BLINK0=PWM0/256.Table 4.Register summaryB2B1B0Symbol Access Description 000INPUT read only input register 001PSC0read/write frequency prescaler 0010PWM0read/write PWM register 0011PSC1read/write frequency prescaler 1100PWM1read/write PWM register 111LS0read/writeLED selectorTable 5.INPUT - Input register descriptionBit 76543210Symbol ----LED3LED2LED1LED0DefaultXXXXTable 6.PSC0 - Frequency Prescaler 0 register descriptionBit 76543210Symbol PSC0[7]PSC0[6]PSC0[5]PSC0[4]PSC0[3]PSC0[2]PSC0[1]PSC0[0]DefaultTable 7.PWM0 - Pulse Width Modulation 0 register descriptionBit 76543210Symbol PWM0[7]PWM0[6]PWM0[5]PWM0[4]PWM0[3]PWM0[2]PWM0[1]PWM0[0]Default16.3.4PCS1 - Frequency Prescaler 1PSC1 is used to program the period of the PWM output.The period of BLINK1=(PSC1+1)/152.6.3.5PWM1 - Pulse Width Modulation 1The PWM1register determines the duty cycle of BLINK1.The outputs are LOW (LED on)when the count is less than the value in PWM1 and HIGH (LED off) when it is greater. If PWM1 is programmed with 00h, then the PWM1 output is always HIGH (LED off).The duty cycle of BLINK1=PWM1/256.6.3.6LS0 - LED selectorThe LSn LED selector register determines the source of the LED data.00=output is set high-impedance (LED off; default)01=output is set LOW (LED on)10=output blinks at PWM0 rate 11=output blinks at PWM1 rateTable 8.PSC1 - Frequency Prescaler 1 register descriptionBit 76543210Symbol PSC1[7]PSC1[6]PSC1[5]PSC1[4]PSC1[3]PSC1[2]PSC1[1]PSC1[0]DefaultTable 9.PWM1 - Pulse Width Modulation 1 register descriptionBit 76543210Symbol PWM1[7]PWM1[6]PWM1[5]PWM1[4]PWM1[3]PWM1[2]PWM1[1]PWM1[0]Default1Table 10.LS0 - LED selector register bit description Legend: * default value.Register Bit Value Description LS07:600*LED3 selected 5:400*LED2 selected 3:200*LED1 selected 1:000*LED0 selected6.4Pins used as GPIOsLEDn pins not used to control LEDs can be used as General Purpose I/Os (GPIOs).For use as input, set LEDn to high-impedance (00) and then read the pin state via the INPUT register.For use as output, connect external pull-up resistor to the pin and size it according to the DC recommended operating characteristics. LEDn output pin is HIGH when the output is programmed as high-impedance,and LOW when the output is programmed LOW through the ‘LED selector’ register. The output can be pulse-width controlled when PWM0 orPWM1 are used.6.5Power-on resetWhen power is applied to V DD, an internal Power-On Reset (POR) holds the PCA9533 ina reset condition until V DD has reached V POR.At that point,the reset condition is releasedand the PCA9533 registers are initialized to their default states, all the outputs in theOFF state. Thereafter, V DD must be lowered below 0.2V to reset the device.7.Characteristics of the I 2C-busThe I 2C-bus is for 2-way,2-line communication between different ICs or modules.The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must beconnected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.7.1Bit transferOne data bit is transferred during each clock pulse.The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 7).7.1.1START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOWtransition of the data line while the clock is HIGH is defined as the START condition (S).A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 8).7.2System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 9).Fig 7.Bit transfermba607data line stable;data validchange of data allowedSDASCLFig 8.Definition of START and STOP conditionsmba608SDASCLPSTOP conditionSSTART condition7.3AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by oneacknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,whereas the master generates an extra acknowledge related clock pulse.A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse,so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account.A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.Fig 9.System configuration002aaa966MASTER TRANSMITTER/RECEIVERSLAVE RECEIVERSLAVETRANSMITTER/RECEIVERMASTER TRANSMITTERMASTER TRANSMITTER/RECEIVERSDA SCLI 2C-BUS MULTIPLEXERSLAVEFig 10.Acknowledgement on the I 2C-bus002aaa987S START condition9821clock pulse for acknowledgementnot acknowledgeacknowledgedata output by transmitterdata output by receiverSCL from master7.4Bus transactionsFig 11.Write to register0ASslave address (PCA9533/01)START condition R/Wacknowledge from slave002aae629AI0B2B1B00command byteAacknowledge from slave12345678SCL9SDA DATA 1Awrite to registerdata out from portt v(Q)acknowledge from slaveDATA 1 VALIDdata to register111Fig 12.Read from register110AS1START conditionR/Wacknowledge from slave002aae630Aacknowledge from slaveSDA APacknowledge from masterdata from registerDATA (first byte)slave address (PCA9533/01)STOP conditionS(repeated)START condition (cont.)(cont.)1AR/W acknowledge from slaveslave address (PCA9533/01)at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitterNA no acknowledgefrom masterdata from register DATA (last byte)command byte 0AI0B2B10B0Auto-Increment register address if AI = 1111Remark:This figure assumes the command byte has previously been programmed with 00h.Fig 13.Read input port register111AS1START conditionR/Wacknowledge from slave002aae631Aacknowledge from masterSDA NA read fromportdata intoportPt h(D)data from port no acknowledge from masterdata from port DATA 4slave address (PCA9533/01)DATA 1STOP conditionDATA 2DATA 3DATA 4t su(D)DATA 18.Application design-in information8.1Minimizing I DD when the I/Os are used to control LEDsWhen the I/Os are used to control LEDs, they are normally connected to V DD through a resistor as shown in Figure 14. Since the LED acts as a diode, when the LED is off the I/O V I is about 1.2V less than V DD . The supply current, I DD , increases as V I becomes lower than V DD and is specified as ∆I DD in Table 13 “Static characteristics”.Designs needing to minimize current consumption, such as battery power applications,should consider maintaining the I/O pins greater than or equal to V DD when the LED is off.Figure 15 shows a high value resistor in parallel with the LED.Figure 16 shows V DD less than the LED supply voltage by at least 1.2V . Both of these methods maintain the I/O V I at or above V DD and prevents additional supply current consumption when the LED is off.Fig 14.Typical applicationPCA9533LED0LED1SDA SCL5 VI 2C-BUS/SMBusMASTER002aae632SDASCLV DDV SS5 VLED2LED310 k Ω10 k ΩFig 15.High value resistor in parallel withthe LEDFig 16.Device supplied by a lower voltage002aac189LEDV DDLEDn 100 k ΩV DD002aac190LEDV DDLEDn3.3 V5 V8.2Programming exampleThe following example will show how to set LED0and LED1off.It will set LED2to blink at 1Hz at a 50% duty cycle. LED3 will be set to be dimmed at 25% of their maximum brightness (duty cycle =25%). PCA9533/01 is used in this example.9.Limiting valuesTable 11.Programming PCA9533Program sequenceI 2C-bus ST ARTS PCA9533 addressC4h PSC0 subaddress + Auto-Increment11h Set prescaler PSC0 to achieve a period of 1second:PSC0=15197hSet PWM0 duty cycle to 50%:PWM0=12880hSet prescaler PCS1 to dim at maximum frequency:PSC1=000h Set PWM1 output duty cycle to 25%:PWM1=6440h Set LED0 on, LED1 off; LED2 set to blink at PSC0, PWM0; LED3 set to blink at PSC1, PWM1E1h STOPP Blink period 1PSC01+152-----------------------==PWM0256-----------------0.5=Blink period max =PWM1256-----------------0.25=Table 12.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter ConditionsMin Max Unit V DD supply voltage−0.5+6.0V V I/O voltage on an input/output pin V SS −0.5 5.5V I O(LEDn)output current on pin LEDn -25mA I SS ground supply current -100mA P tot total power dissipation -400mW T stg storage temperature −65+150°C T ambambient temperatureoperating −40+85°C10.Static characteristics[1]Typical limits at V DD =3.3V , T amb =25°C.[2]V DD must be lowered to 0.2V in order to reset part.[3]Each I/O must be externally limited to a maximum of 25mA and the device must be limited to a maximum current of 100mA.Table 13.Static characteristicsV DD =2.3V to 5.5V; V SS =0V; T amb =−40°C to +85°C; unless otherwise specified.Symbol ParameterConditionsMinTyp [1]MaxUnitSupplies V DD supply voltage 2.3- 5.5V I DD supply current operating mode; V DD =5.5V; no load;V I =V DD or V SS ; f SCL =100kHz -350550µA I stb standby currentStandby mode; V DD =5.5V; no load;V I =V DD or V SS ; f SCL =0kHz- 1.9 3.0µA ∆I DDadditional quiescent supply current Standby mode; V DD =5.5V;every LED I/O at V I =4.3V;f SCL =0kHz --325µAV POR power-on reset voltage no load; V I =V DD or V SS[2]- 1.7 2.2V Input SCL; input/output SDAV IL LOW-level input voltage −0.5-+0.3V DD V V IH HIGH-level input voltage 0.7V DD- 5.5V I OL LOW-level output current V OL =0.4V 3 6.5-mA I L leakage current V I =V DD =V SS −1-+1µA C i input capacitance V I =V SS- 3.75pF I/Os V IL LOW-level input voltage −0.5-+0.8V V IH HIGH-level input voltage 2.0- 5.5V I OLLOW-level output currentV OL =0.4V V DD =2.3V [3]9--mA V DD =3.0V [3]12--mA V DD =5.0V [3]15--mA V OL =0.7V V DD =2.3V [3]15--mA V DD =3.0V [3]20--mA V DD =5.0V[3]25--mA I LI input leakage current V DD =3.6V; V I =0V or V DD−1-+1µA C ioinput/output capacitance-2.15pF(1)maximum (2)average (3)minimum(1)maximum (2)average (3)minimumFig 17.Typical frequency variation over process atV DD =2.3V to 3.0V Fig 18.Typical frequency variation over process atV DD =3.0V to 5.5V−20 %0 %20 %percent variation−40 %T amb (°C)−40100−20002aac191020406080(2)(1)(3)−20 %0 %20 %percent variation−40 %T amb (°C)−40100−20002aac192020406080(1)(2)(3)11.Dynamic characteristics[1]t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.[2]t VD;DA T = minimum time for SDA data output to be valid following SCL LOW.[3]C b =total capacitance of one bus line in pF .Table 14.Dynamic characteristics SymbolParameterConditionsStandard-modeI 2C-bus Fast-mode I 2C-busUnitMinMax Min Max f SCL SCL clock frequency01000400kHz t BUF bus free time between a STOP and ST ART condition4.7- 1.3-µs t HD;STA hold time (repeated) START condition 4.0-0.6-µs t SU;ST A set-up time for a repeated ST ART condition4.7-0.6-µs t SU;STO set-up time for STOP condition 4.0-0.6-µs t HD;DA T data hold time0-0-ns t VD;ACK data valid acknowledge time [1]-600-600ns t VD;DA T data valid time LOW-level [2]-600-600ns HIGH-level[2]-1500-600ns t SU;DA T data set-up time250-100-ns t LOW LOW period of the SCL clock 4.7- 1.3-µs t HIGH HIGH period of the SCL clock 4.0-0.6-µs t r rise time of both SDA and SCL signals -100020+0.1C b [3]300ns t f fall time of both SDA and SCL signals -30020+0.1C b [3]300ns t SPpulse width of spikes that must be suppressed by the input filter -50-50nsPort timing t v(Q)data output valid time -200-200ns t su(D)data input set-up time 100-100-ns t h(D)data input hold time1-1-µs12.Test informationFig 19.Definition of timingt SPt BUFt HD;STAPPSt LOWt rt HD;DAT t ft HIGH t SU;DATt SU;STASrt HD;STAt SU;STOSDASCL002aaa986Rise and fall times refer to V IL and V IH .Fig 20.I 2C-bus timing diagramSCLSDAt HD;STA t SU;DA T t HD;DA T t ft BUFt SU;ST At LOWt HIGHt VD;ACK 002aab175t SU;STOprotocolST ART condition (S)bit 7MSB (A7)bit 6(A6)bit 0(R/W)acknowledge(A)STOP condition (P)1/fSCLt rt VD;DA T R L = load resistor for LEDn. R L for SDA and SCL > 1k Ω (3mA or less current).C L = load capacitance includes jig and probe capacitance.R T = termination resistance should be equal to the output impedance Z o of the pulse generators.Fig 21.Test circuitry for switching timesPULSE GENERATORV OC L 50 pFR L 500 Ω002aab880R TV IV DDDUTV DD open V SS13.Package outlineFig 22.Package outline SOT96-1 (SO8)UNIT Amax.A 1A 2A 3b p c D (1)E (2)(1)e H E L L p Q Z y w v θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IEC JEDEC JEITAmm inches1.750.250.101.451.250.250.490.360.250.195.04.8 4.03.8 1.276.25.81.050.70.60.70.380o o 0.250.10.25DIMENSIONS (inch dimensions are derived from the original mm dimensions)Notes1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.1.00.4SOT96-1Xw MθAA 1A 2b pD H EL pQdetail XE Z ecL v M A(A )3A45pin 1 index18y076E03MS-0120.0690.0100.0040.0570.0490.010.0190.0140.01000.00750.200.190.160.150.050.2440.2280.0280.0240.0280.0120.010.010.0410.0040.0390.0160 2.5 5 mmscaleSO8: plastic small outline package; 8 leads; body width 3.9 mmSOT96-199-12-2703-02-18Fig 23.Package outline SOT505-1 (TSSOP8)UNIT A 1A max.A 2A 3b p L H E L p w y v c e D (1)E (2)Z (1)θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE IECJEDECJEITAmm0.150.050.950.800.450.250.280.153.12.93.12.90.655.14.70.700.356°0°0.10.10.10.94DIMENSIONS (mm are the original dimensions)Notes1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.0.70.4SOT505-199-04-0903-02-18w Mb pD Ze0.251485θAA 2A 1L p (A 3)detail XLH EE cv M AXAy2.5 5 mm0scaleTSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-11.1pin 1 index14.Handling informationAll input and output pins are protected against ElectroStatic Discharge (ESD) undernormal handling. When handling ensure that the appropriate precautions are taken asdescribed in JESD625-A or equivalent standards.15.Soldering of SMD packagesThis text provides a very brief insight into a complex technology.A more in-depth accountof soldering ICs can be found in Application Note AN10365 “Surface mount reflowsoldering description”.15.1Introduction to solderingSoldering is one of the most common methods through which packages are attached toPrinted Circuit Boards(PCBs),to form electrical circuits.The soldered joint provides boththe mechanical and the electrical connection. There is no single soldering method that isideal for all IC packages. Wave soldering is often preferred when through-hole andSurface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is notsuitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.15.2Wave and reflow solderingWave soldering is a joining technology in which the joints are made by solder coming froma standing wave of liquid solder. The wave soldering process is suitable for the following:•Through-hole components•Leaded or leadless SMDs, which are glued to the surface of the printed circuit boardNot all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered,due to an increased probability of bridging.The reflow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature profile. Leaded packages,packages with solder balls, and leadless packages are all reflow solderable.Key characteristics in both wave and reflow soldering are:•Board specifications, including the board finish, solder masks and vias•Package footprints, including solder thieves and orientation•The moisture sensitivity level of the packages•Package placement•Inspection and repair•Lead-free soldering versus SnPb soldering15.3Wave solderingKey characteristics in wave soldering are:•Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components areexposed to the wave•Solder bath specifications, including temperature and impurities15.4Reflow solderingKey characteristics in reflow soldering are:•Lead-free versus SnPb soldering;note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure24) than a SnPb process, thusreducing the process window•Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board•Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peaktemperature is high enough for the solder to make reliable solder joints(a solder pastecharacteristic). In addition, the peak temperature must be low enough that thepackages and/or boards are not damaged. The peak temperature of the packagedepends on package thickness and volume and is classified in accordance withTable15 and16Table 15.SnPb eutectic process (from J-STD-020C)Package thickness (mm)Package reflow temperature (°C)Volume (mm3)< 350≥ 350< 2.5235220≥ 2.5220220Table 16.Lead-free process (from J-STD-020C)Package thickness (mm)Package reflow temperature (°C)Volume (mm3)< 350350 to 2000> 2000 < 1.62602602601.6 to2.5260250245> 2.5250245245Moisture sensitivity precautions, as indicated on the packing, must be respected at alltimes.Studies have shown that small packages reach higher temperatures during reflowsoldering, see Figure24.For further information on temperature profiles, refer to Application Note AN10365“Surface mount reflow soldering description”.16.AbbreviationsMSL: Moisture Sensitivity LevelFig 24.Temperature profiles for large and small components001aac844temperaturetimeminimum peak temperature = minimum soldering temperaturemaximum peak temperature = MSL limit, damage levelpeak temperatureTable 17.AbbreviationsAcronym DescriptionACPI Advanced Configuration and Power Interface CDM Charged Device Model DSP Digital Signal Processor DUT Device Under Test ESD ElectroStatic Discharge GPIO General Purpose Input/Output HBM Human Body Model I 2C-bus Inter-Integrated Circuit bus LED Light Emitting Diode MCU MicroController Unit MM Machine Model MPU MicroProcessor Unit POR Power-On ResetRC Resistor-Capacitor network SMBusSystem Management Bus。
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I 1 MHz Fast-mode Plus I2C-bus interface with 30 mA high drive capability on SDA output for driving high capacitive buses
I 256-step (8-bit) linear programmable brightness per LED output varying from fully off (default) to maximum brightness using a 97 kHz PWM signal
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9633 through the I2C-bus, identical to the Power-On Reset (POR) that initializes the registers to their default state causing the outputs to be set HIGH (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition.
Software programmable LED Group and three Sub Call I2C addresses allow all or defined groups of PCA9633 devices to respond to a common I2C address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C-bus commands.
The PCA9633 is one of the first LED controller devices in a new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated bus operation (up to 4000 pF).
I Four totem pole outputs (sink 25 mA and source 10 mA at 5 V) with software programmable open-drain LED outputs selection (default at totem pole). No input function.
PCA9633
4-bit Fm+ I2C-bus LED driver
Rev. 05 — 25 July 2008
Product data sheet
1. General description
The PCA9633 is an I2C-bus controlled 4-bit LED driver optimized for Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own 8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set to a specific brightness value. A fifth 8-bit resolution (256 steps) Group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all LEDs with the same value.
I 2 hardware address pins (10-pin version) and 7 hardware address pins (16-pin version) allow respectively up to 4 and 126 devices to be connected to the same I2C-bus. No hardware address pins in the 8-pin version.
The PCA9633 is offered with 3 different I2C-bus address options: fixed I2C-bus address (8-pin version), 4 different I2C-bus addresses from 2 programmable address pins (10-pin version), and 126 different I2C-bus addresses from 7 programmable address pins (16-pin version). They are software identical except for the different number of address combinations.
I Active LOW Output Enable (OE) input pin. LED outputs programmable to ‘1’, ‘0’ or ‘high-impedance’ (default at power-up) when OE is HIGH, thus allowing hardware blinking and dimming of the LEDs (16-pin version only).
I Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’).
I Software Reset feature (SWRST Call) allows the device to be reset through the I2C-bus
The active LOW Output Enable input pin (OE) allows asynchronous control of the LED outputs and can be used to set all the outputs to a defined I2C-bus programmable logic state. The OE can also be used to externally PWM the outputs, which is useful when multiple devices need to be dimmed or blinked together using software control. This feature is available for the 16-pin version only.
I 4 software programmable I2C-bus addresses (one LED Group Call address and three LED Sub Call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for ‘All Call’ so that all the PCA9633s on the I2C-bus can be addressed at the same time and the second register used for three different addresses so that 1⁄3 of all devices on the bus can be addressed at the same time in a group). Software enable and disable for I2C-bus address.