哈工大模拟cmos第一章

• BSIM3v3 is most popular spice model provided by foundry for MOS. （UC Berkeley） BSIM web site: /~bsim3 • Spice simulators：
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• 0.3 Analog and Mixed-signal IC
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0.4 structure of the course
AD/DA Ch12 Switch capacitor PLL Ch14 oscillator
Ch13 nonlinear and mismatch
ΦMS is the difference between the work functions of polysilicon gate and the sillicon substrate；
q is electron charge, Nsubis the doping concentration, Qdepis the charge in the depletion, Cox is the gate oxide capacitance per unit area;
VTH 0
VTH
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其中，γ为体效应系数
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– 1.3.2 Channel-length modulation
The actual length of the inverted channel gradually decreases as the potential difference of VDS increases. i.e. L‟ is in fact a function of VDS. L‟=L-ΔL， ΔL/L=λVDS
CGB series of gate oxide cap. C1 and the depletion cap. Cd (C2)
• Deep triode, VDVS， • Saturation,
In triode and saturation, CGB is usually neglected.
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(VGS VTH ) 2I D
2I D VGS VTH
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？gm∝ID or ∝ID1/2
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– 1.4.3 MOS SPICE models
• SPICE: Simulation Program With Integrated Circuit • During simulation，SPICE requires that every device must has a accurate model. • Progress
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• MOSFET: 4-terminals device
• CMOS process
N阱
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Байду номын сангаас
– 1.1.2 MOS symbol
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• 1.2 I/V characteristic of MOS
– 1.1.1 Threshold voltage
It is typically adjusted bye implantation of dopants into the channel area during device fabrication.
For NMOS，typically adjusted to 0.7V.
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– 1.1.2 I/V of MOS device NMOS
λis the channel-length modulation coefficient.
1/ L
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– 1.3.3 Subthreshold conduction
For VGSVTH or < VTH slightly, a „weak‟ inversion layer still exists. When VDS greater than roughly 200mV, Where ζ>1，VT＝kT/q
（NFET）
耗尽depletion (b); 反型开始onset of inversion (c)； 反型inversion（d）
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• Threshold （VTH） The VTH of an NFET is usually defined as the gate voltage for which the interface is “as much n-type as the substrate is p-type.” ( NFET的VTH通常定义为界面 的电子浓度等于P型衬底的多子浓度时的栅压。)
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Analog design is art and science at the same time.
- Willy Sansen KULeuven, Belgium
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0. Introduction
• Basic Circuit Theory: Analog Circuit Basic, Device Model, Foundation of Integrated Circuits
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• 1.4 MOS device model
– 1.4.1 MOS device capacitances
• Oxide cap. between gate and channel • Depletion cap. (channel vs substrate)
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Where Cj0is capacitance under reverse voltage cross the junction, ΦB is junction built-in potential. m=0.3~0.4
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Effective capacitances: • Cut-off: CGD=CGS=CovW，
– 1st generation：MOS1，MOS2，MOS3； – 2nd generation：BSIM (Berkeley Short-Channel IGFET Model) ， HSPICE level＝28，BSIM2 – 3rd generation：BSIM3，MOS model9，EKV(Enz-Krummenacher-Vittoz)
• Reference:
Design of Analog CMOS Integrated Circuits (模拟CMOS集成电路设计)， [美]毕查德.拉扎维 著，陈贵灿 程军 张瑞智 等译，西安交通大学出版 社。(英文版&中文版) 集成电路设计 ，叶以正、来逢昌 著，清华大学出版社。 CMOS模拟电路设计（第二版）（英文版），[美] Phillip E. Allen, Douglas R. Holberg 著，电子工业出版社。 模拟集成电路的分析与设计，Paul R. Gray， Paul J. Hurst， Stephen H. Lewis，Robert G. Meyer著，(影印版), 高等教育 出版社。
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Why Analog Integrated Circuits?
Eggshell Analogy of Analog IC Design (Paul Gray)

Why CMOS Analog Integrated Circuits?
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• 0.2 Design Flow of Analog IC
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ch2 MOS device
Ch1 Introduction
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1. Device Physics
• 1.1 Basic
– 1.1.1 Structure of MOSFET
（NFET）
• 栅（G: gate）、源（S: source）、漏（D: drain）、衬底（B: bulk）
– HSPICE；SPECTRE；PSPICE；ELDO – WinSPICE；Spice OPUS Free!
Systems
complex
Ch9 opamp
Ch10 stability and freq. compensation Ch7 Noise Ch4 differential amp.
Ch11 Band-gap Reference
Ch8 Feedback Ch5 Current Source
Ch6 frequency response Ch3 single-stage amp. simple Circuits Devices
Design of Analog Integrated Circuits
Introduction Semi-conductor Device Physics and Model
Outline
• 0. Introduction • 1. MOS Device Physics and Model
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• 1.4 MOS device model
– 1.4.1 MOS device capacitances
• Overlap cap. (Gate poly vs S or D) C3，C4,
Cov: overlap capacitance per unit.
• Junction cap. (S/D vs substrate) C5，C6. Junction cap.
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εsi denotes the dielectric constant. 13