1 Reducing Inter-Vector-Conflicts in Complex Memory Systems

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In complex memory systems where several memory modules are mapped in every bus [1, 2], the interconnection network(1) cost can be decreased by reducing the number of independent access paths to memory modules. This causes the appearance of inter-conflicts within the interconnection network, as well as producing memory module inter-conflicts. The coupling of both inter-conflicts causes the performance of the memory subsystem to be lower than the highest reachable. These inter-conflicts are named linked conflicts or complex conflicts [1]. The present study focuses on reducing the inter-conflicts (henceforth, inter-conflicts will be called conflicts) in complex memory subsystems. In this case, it is necessary to order the accesses to vector stream elements to eliminate the interconnection network and memory module conflicts. Our proposal consists of: a) defining one order to access vector stream elements to reference the memory modules in one stride independent order, and b) applying a mapping of memory modules in buses (sections). The relative order to access the referenced memory modules and sections is stride independent; the stride and the first memory module referenced determine the set of memory modules and corresponding buses to be accessed. Parallel with our work, D.L. Lee proposes in [3] to apply the sequential order of memory modules in a prime-way memory system. Nevertheless, D.L. Lee indicates that this order in not generally applicable in interleaved memory systems with a power of two memory modules. The time needed to complete a vector operation can be computed with the expression
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conflict-free phase, r ∞ is the maximum reachable. If a conflict-free phase is not reached, r ∞ is less than the maximum reachable and the number of cycles required to access the memory increases [12]. By conflict-free phase we mean a steady-state phase without inter-conflicts. The method proposed in this paper to access complex memory systems has an asymptotic behavior of r ∞ which is superior to the behavior of the classical access order to vector elements (Ai=Ai-1+ S) in memory systems like CRAY-X MP[2]. Figure 1 shows the number of operations per cycle ( R ∞ = ops × r ∞ ) for the proposal and the classical method applied in a memory systems like CRAY-X MP. The results are for the simulation of 4 odd strided vector streams concurrently accessing a complex memory system with M = 16, SC = 4 and nc = 4. The R∞ for the proposed method is 3.908, and for the classical order is 1.465.
Abstract In vector processors, the concurrent memory access of several vector streams causes interconflicts between the references. In a complex memory system where several memory modules are mapped in every bus the number of conflicts increases because the bus must be shared by the vector streams. In addition to the memory module access conflicts, bus access conflicts could appear, and also couplings of both conflicts. This paper proposes an access order to the vector stream elements and a mapping model of memory modules in buses that reduce the interconflicts in the steady-state.
Section 2 outlines the architecture model, on which the present study is based. The interaction between vector streams in a complex memory system is studied in section 3; section 4 presents the proposal we make in this paper to avoid conflicts. Finally, section 5 deals with the performance of the proposed method.
1. between
processor and memory modules.
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OPSperCYCLE 4 3.5 3 2.5 2 1.5 1 0.5 0 50 100 150 200 250 VL 300 R∞ = 1.465 R∞ = 3.908
Figuy system with nc = 4 and SC = 4.
Keywords: Complex Memory System, Vector Stream, Inter-conflicts, Inter-Complex Conflicts, Stride.
1. Introduction
The most common data structures in vector processors are vectors stored in consecutive positions in memory. The access patterns are regular and, sometimes, consecutive positions are accessed. The memory module reservation time is, in general, much longer than the processor cycle time. Therefore, the performance of a vector processor is strongly related to the bandwidth of a memory subsystem (number of accesses per cycle). A memory module conflict appears when two or more references are concurrently issued to the same memory module or, a busy memory module is referenced. The most common technique is multiple memory modules that are accessed independently in order to obtain the necessary bandwidth. After the initial latency, a datum can be obtained every cycle. Memory vector instructions generate periodical conflicts as these type of instructions generate periodical streams of references (vector stream). In this paper, our interest is centered on the reduction of conflicts generated between references of different vector streams concurrently accessing the memory (interconflicts).